isa_traits.hh revision 3808:3406c3ffa645
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2003-2005 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286657Snate@binkert.org * Authors: Gabe Black 296657Snate@binkert.org * Ali Saidi 306657Snate@binkert.org */ 316657Snate@binkert.org 326657Snate@binkert.org#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 336657Snate@binkert.org#define __ARCH_SPARC_ISA_TRAITS_HH__ 346657Snate@binkert.org 356657Snate@binkert.org#include "arch/sparc/types.hh" 366657Snate@binkert.org#include "arch/sparc/sparc_traits.hh" 376657Snate@binkert.org#include "config/full_system.hh" 386657Snate@binkert.org 396657Snate@binkert.orgclass StaticInstPtr; 406657Snate@binkert.org 416657Snate@binkert.orgnamespace BigEndianGuest {} 426657Snate@binkert.org 436657Snate@binkert.orgnamespace SparcISA 446657Snate@binkert.org{ 456657Snate@binkert.org class RegFile; 466657Snate@binkert.org 476657Snate@binkert.org //This makes sure the big endian versions of certain functions are used. 486657Snate@binkert.org using namespace BigEndianGuest; 496657Snate@binkert.org 506657Snate@binkert.org // SPARC has a delay slot 516657Snate@binkert.org #define ISA_HAS_DELAY_SLOT 1 526657Snate@binkert.org 536657Snate@binkert.org // SPARC NOP (sethi %(hi(0), g0) 546657Snate@binkert.org const MachInst NoopMachInst = 0x01000000; 556657Snate@binkert.org 566657Snate@binkert.org // These enumerate all the registers for dependence tracking. 576657Snate@binkert.org enum DependenceTags { 586657Snate@binkert.org FP_Base_DepTag = 33, 596657Snate@binkert.org Ctrl_Base_DepTag = 97, 606657Snate@binkert.org }; 616657Snate@binkert.org 626657Snate@binkert.org // semantically meaningful register indices 636657Snate@binkert.org const int ZeroReg = 0; // architecturally meaningful 646657Snate@binkert.org // the rest of these depend on the ABI 656657Snate@binkert.org const int StackPointerReg = 14; 666657Snate@binkert.org const int ReturnAddressReg = 31; // post call, precall is 15 676657Snate@binkert.org const int ReturnValueReg = 8; // Post return, 24 is pre-return. 686657Snate@binkert.org const int FramePointerReg = 30; 696657Snate@binkert.org const int ArgumentReg0 = 8; 70 const int ArgumentReg1 = 9; 71 const int ArgumentReg2 = 10; 72 const int ArgumentReg3 = 11; 73 const int ArgumentReg4 = 12; 74 const int ArgumentReg5 = 13; 75 // Some OS syscall use a second register (o1) to return a second value 76 const int SyscallPseudoReturnReg = ArgumentReg1; 77 78 //XXX These numbers are bogus 79 const int MaxInstSrcRegs = 8; 80 const int MaxInstDestRegs = 9; 81 82 //8K. This value is implmentation specific; and should probably 83 //be somewhere else. 84 const int LogVMPageSize = 13; 85 const int VMPageSize = (1 << LogVMPageSize); 86 87 //Why does both the previous set of constants and this one exist? 88 const int PageShift = 13; 89 const int PageBytes = 1ULL << PageShift; 90 91 const int BranchPredAddrShiftAmt = 2; 92 93 StaticInstPtr decodeInst(ExtMachInst); 94 95#if FULL_SYSTEM 96 ////////// Interrupt Stuff /////////// 97 enum InterruptLevels 98 { 99 INTLEVEL_MIN = 1, 100 INTLEVEL_MAX = 15, 101 102 NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN 103 }; 104 105 // I don't know what it's for, so I don't 106 // know what SPARC's value should be 107 // For loading... XXX This maybe could be USegEnd?? --ali 108 const Addr LoadAddrMask = ULL(0xffffffffff); 109 110 /////////// TLB Stuff //////////// 111 const Addr StartVAddrHole = ULL(0x0000800000000000); 112 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 113 const Addr VAddrAMask = ULL(0xFFFFFFFF); 114 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 115 const Addr BytesInPageMask = ULL(0x1FFF); 116 117#endif 118} 119 120#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 121