isa_traits.hh revision 13912:53531772924f
19242SN/A/* 29242SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 39242SN/A * All rights reserved. 49242SN/A * 59242SN/A * Redistribution and use in source and binary forms, with or without 69242SN/A * modification, are permitted provided that the following conditions are 79242SN/A * met: redistributions of source code must retain the above copyright 89242SN/A * notice, this list of conditions and the following disclaimer; 99242SN/A * redistributions in binary form must reproduce the above copyright 109242SN/A * notice, this list of conditions and the following disclaimer in the 119242SN/A * documentation and/or other materials provided with the distribution; 129242SN/A * neither the name of the copyright holders nor the names of its 139242SN/A * contributors may be used to endorse or promote products derived from 149242SN/A * this software without specific prior written permission. 159242SN/A * 169242SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179242SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189242SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199242SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209242SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219242SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229242SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259242SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269242SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279242SN/A * 289242SN/A * Authors: Gabe Black 299242SN/A * Ali Saidi 309242SN/A */ 319242SN/A 329242SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 339242SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 349242SN/A 359242SN/A#include "arch/sparc/sparc_traits.hh" 369242SN/A#include "arch/sparc/types.hh" 379242SN/A#include "base/types.hh" 389242SN/A#include "cpu/static_inst_fwd.hh" 399242SN/A 409242SN/Anamespace BigEndianGuest {} 419402SN/A 429402SN/Anamespace SparcISA 439402SN/A{ 449402SN/A// This makes sure the big endian versions of certain functions are used. 459402SN/Ausing namespace BigEndianGuest; 469242SN/A 479242SN/A// real address virtual mapping 4810218Sandreas.hansson@arm.com// sort of like alpha super page, but less frequently used 499242SN/Aconst Addr SegKPMEnd = ULL(0xfffffffc00000000); 509242SN/Aconst Addr SegKPMBase = ULL(0xfffffac000000000); 519728SN/A 5210720Sandreas.hansson@arm.comconst Addr PageShift = 13; 539827SN/Aconst Addr PageBytes = ULL(1) << PageShift; 549827SN/A 559827SN/AStaticInstPtr decodeInst(ExtMachInst); 569242SN/A 579242SN/A/////////// TLB Stuff //////////// 589242SN/Aconst Addr StartVAddrHole = ULL(0x0000800000000000); 599242SN/Aconst Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 609242SN/Aconst Addr VAddrAMask = ULL(0xFFFFFFFF); 619242SN/Aconst Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 629242SN/Aconst Addr BytesInPageMask = ULL(0x1FFF); 639242SN/A 649242SN/A// Memory accesses cannot be unaligned 659242SN/Aconst bool HasUnalignedMemAcc = false; 669242SN/A 679242SN/Aconst bool CurThreadInfoImplemented = false; 689242SN/Aconst int CurThreadInfoReg = -1; 699242SN/A 709242SN/A} 719242SN/A 729242SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 739242SN/A