isa_traits.hh revision 10318:98771a936b61
12381SN/A/* 212780Snikos.nikoleris@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * Redistribution and use in source and binary forms, with or without 68711SN/A * modification, are permitted provided that the following conditions are 78711SN/A * met: redistributions of source code must retain the above copyright 88711SN/A * notice, this list of conditions and the following disclaimer; 98711SN/A * redistributions in binary form must reproduce the above copyright 108711SN/A * notice, this list of conditions and the following disclaimer in the 118711SN/A * documentation and/or other materials provided with the distribution; 128711SN/A * neither the name of the copyright holders nor the names of its 138711SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272381SN/A * 282381SN/A * Authors: Gabe Black 292381SN/A * Ali Saidi 302381SN/A */ 312381SN/A 322381SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 332381SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 342381SN/A 352381SN/A#include "arch/sparc/sparc_traits.hh" 362381SN/A#include "arch/sparc/types.hh" 372381SN/A#include "base/types.hh" 382381SN/A#include "cpu/static_inst_fwd.hh" 392665SN/A 402665SN/Anamespace BigEndianGuest {} 412772SN/A 428715SN/Anamespace SparcISA 438922SN/A{ 442381SN/A// This makes sure the big endian versions of certain functions are used. 452381SN/Ausing namespace BigEndianGuest; 462381SN/A 472982SN/A// SPARC has a delay slot 4810405Sandreas.hansson@arm.com#define ISA_HAS_DELAY_SLOT 1 492381SN/A 502381SN/A// SPARC NOP (sethi %(hi(0), g0) 5110405Sandreas.hansson@arm.comconst MachInst NoopMachInst = 0x01000000; 5210405Sandreas.hansson@arm.com 532381SN/A// real address virtual mapping 549291SN/A// sort of like alpha super page, but less frequently used 5511168Sandreas.hansson@arm.comconst Addr SegKPMEnd = ULL(0xfffffffc00000000); 562381SN/Aconst Addr SegKPMBase = ULL(0xfffffac000000000); 579235SN/A 586215SN/Aconst Addr PageShift = 13; 592381SN/Aconst Addr PageBytes = ULL(1) << PageShift; 6010888Sandreas.hansson@arm.com 6110405Sandreas.hansson@arm.comStaticInstPtr decodeInst(ExtMachInst); 629712SN/A 632381SN/A/////////// TLB Stuff //////////// 649036SN/Aconst Addr StartVAddrHole = ULL(0x0000800000000000); 6510405Sandreas.hansson@arm.comconst Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 6610405Sandreas.hansson@arm.comconst Addr VAddrAMask = ULL(0xFFFFFFFF); 6710405Sandreas.hansson@arm.comconst Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 6810405Sandreas.hansson@arm.comconst Addr BytesInPageMask = ULL(0x1FFF); 699036SN/A 7010405Sandreas.hansson@arm.comenum InterruptTypes 719036SN/A{ 729036SN/A IT_TRAP_LEVEL_ZERO, 7310405Sandreas.hansson@arm.com IT_HINTP, 742381SN/A IT_INT_VEC, 759031SN/A IT_CPU_MONDO, 769036SN/A IT_DEV_MONDO, 772381SN/A IT_RES_ERROR, 789091SN/A IT_SOFT_INT, 7910405Sandreas.hansson@arm.com NumInterruptTypes 8010405Sandreas.hansson@arm.com}; 8110405Sandreas.hansson@arm.com 8210405Sandreas.hansson@arm.com// Memory accesses cannot be unaligned 8310405Sandreas.hansson@arm.comconst bool HasUnalignedMemAcc = false; 8410405Sandreas.hansson@arm.com 859093SN/Aconst bool CurThreadInfoImplemented = false; 869093SN/Aconst int CurThreadInfoReg = -1; 8710405Sandreas.hansson@arm.com 8810405Sandreas.hansson@arm.com} 8910405Sandreas.hansson@arm.com 9010405Sandreas.hansson@arm.com#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 919091SN/A