isa_traits.hh revision 6974
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282972Sgblack@eecs.umich.edu * Authors: Gabe Black 293804Ssaidi@eecs.umich.edu * Ali Saidi 302023SN/A */ 312023SN/A 322023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 332023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 342023SN/A 352972Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 363752Sgblack@eecs.umich.edu#include "arch/sparc/sparc_traits.hh" 376216Snate@binkert.org#include "base/types.hh" 382225SN/A#include "config/full_system.hh" 392225SN/A 402225SN/Aclass StaticInstPtr; 412023SN/A 422458SN/Anamespace BigEndianGuest {} 432023SN/A 442458SN/Anamespace SparcISA 452458SN/A{ 463809Sgblack@eecs.umich.edu const int MachineBytes = 8; 473809Sgblack@eecs.umich.edu 482972Sgblack@eecs.umich.edu //This makes sure the big endian versions of certain functions are used. 492972Sgblack@eecs.umich.edu using namespace BigEndianGuest; 502972Sgblack@eecs.umich.edu 513437Sgblack@eecs.umich.edu // SPARC has a delay slot 523093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 1 533093Sksewell@umich.edu 543414Sgblack@eecs.umich.edu // SPARC NOP (sethi %(hi(0), g0) 553414Sgblack@eecs.umich.edu const MachInst NoopMachInst = 0x01000000; 562972Sgblack@eecs.umich.edu 572458SN/A //8K. This value is implmentation specific; and should probably 582458SN/A //be somewhere else. 592458SN/A const int LogVMPageSize = 13; 602458SN/A const int VMPageSize = (1 << LogVMPageSize); 612458SN/A 624070Ssaidi@eecs.umich.edu // real address virtual mapping 634070Ssaidi@eecs.umich.edu // sort of like alpha super page, but less frequently used 644070Ssaidi@eecs.umich.edu const Addr SegKPMEnd = ULL(0xfffffffc00000000); 654070Ssaidi@eecs.umich.edu const Addr SegKPMBase = ULL(0xfffffac000000000); 664070Ssaidi@eecs.umich.edu 672458SN/A //Why does both the previous set of constants and this one exist? 682458SN/A const int PageShift = 13; 693756Sgblack@eecs.umich.edu const int PageBytes = 1ULL << PageShift; 702458SN/A 712458SN/A const int BranchPredAddrShiftAmt = 2; 722458SN/A 732469SN/A StaticInstPtr decodeInst(ExtMachInst); 742458SN/A 753804Ssaidi@eecs.umich.edu /////////// TLB Stuff //////////// 763804Ssaidi@eecs.umich.edu const Addr StartVAddrHole = ULL(0x0000800000000000); 773804Ssaidi@eecs.umich.edu const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 783804Ssaidi@eecs.umich.edu const Addr VAddrAMask = ULL(0xFFFFFFFF); 793804Ssaidi@eecs.umich.edu const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 803804Ssaidi@eecs.umich.edu const Addr BytesInPageMask = ULL(0x1FFF); 813804Ssaidi@eecs.umich.edu 824997Sgblack@eecs.umich.edu#if FULL_SYSTEM 834997Sgblack@eecs.umich.edu // I don't know what it's for, so I don't 844997Sgblack@eecs.umich.edu // know what SPARC's value should be 854997Sgblack@eecs.umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 864997Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 874997Sgblack@eecs.umich.edu 884103Ssaidi@eecs.umich.edu enum InterruptTypes 894103Ssaidi@eecs.umich.edu { 904103Ssaidi@eecs.umich.edu IT_TRAP_LEVEL_ZERO, 914103Ssaidi@eecs.umich.edu IT_HINTP, 924103Ssaidi@eecs.umich.edu IT_INT_VEC, 934103Ssaidi@eecs.umich.edu IT_CPU_MONDO, 944103Ssaidi@eecs.umich.edu IT_DEV_MONDO, 954103Ssaidi@eecs.umich.edu IT_RES_ERROR, 964103Ssaidi@eecs.umich.edu IT_SOFT_INT, 974103Ssaidi@eecs.umich.edu NumInterruptTypes 984103Ssaidi@eecs.umich.edu }; 994103Ssaidi@eecs.umich.edu 1003804Ssaidi@eecs.umich.edu#endif 1016974Stjones1@inf.ed.ac.uk 1026974Stjones1@inf.ed.ac.uk// Memory accesses cannot be unaligned 1036974Stjones1@inf.ed.ac.ukconst bool HasUnalignedMemAcc = false; 1042458SN/A} 1052458SN/A 1062023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 107