isa_traits.hh revision 6216
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282972Sgblack@eecs.umich.edu * Authors: Gabe Black 293804Ssaidi@eecs.umich.edu * Ali Saidi 302023SN/A */ 312023SN/A 322023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 332023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 342023SN/A 352972Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 365228Sgblack@eecs.umich.edu#include "arch/sparc/max_inst_regs.hh" 373752Sgblack@eecs.umich.edu#include "arch/sparc/sparc_traits.hh" 386216Snate@binkert.org#include "base/types.hh" 392225SN/A#include "config/full_system.hh" 402225SN/A 412225SN/Aclass StaticInstPtr; 422023SN/A 432458SN/Anamespace BigEndianGuest {} 442023SN/A 452458SN/Anamespace SparcISA 462458SN/A{ 472972Sgblack@eecs.umich.edu class RegFile; 482972Sgblack@eecs.umich.edu 493809Sgblack@eecs.umich.edu const int MachineBytes = 8; 503809Sgblack@eecs.umich.edu 512972Sgblack@eecs.umich.edu //This makes sure the big endian versions of certain functions are used. 522972Sgblack@eecs.umich.edu using namespace BigEndianGuest; 535228Sgblack@eecs.umich.edu using SparcISAInst::MaxInstSrcRegs; 545228Sgblack@eecs.umich.edu using SparcISAInst::MaxInstDestRegs; 552972Sgblack@eecs.umich.edu 563437Sgblack@eecs.umich.edu // SPARC has a delay slot 573093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 1 583093Sksewell@umich.edu 593414Sgblack@eecs.umich.edu // SPARC NOP (sethi %(hi(0), g0) 603414Sgblack@eecs.umich.edu const MachInst NoopMachInst = 0x01000000; 612972Sgblack@eecs.umich.edu 622469SN/A // These enumerate all the registers for dependence tracking. 632469SN/A enum DependenceTags { 644641Sgblack@eecs.umich.edu FP_Base_DepTag = 32*3+9, 653980Sgblack@eecs.umich.edu Ctrl_Base_DepTag = FP_Base_DepTag + 64 662469SN/A }; 672469SN/A 682458SN/A // semantically meaningful register indices 695543Ssaidi@eecs.umich.edu const int ZeroReg = 0; // architecturally meaningful 702458SN/A // the rest of these depend on the ABI 715958Sgblack@eecs.umich.edu const int ReturnAddressReg = 31; // post call, precall is 15 726110Ssteve.reinhardt@amd.com const int ReturnValueReg = 8; // Post return, 24 is pre-return. 732458SN/A const int StackPointerReg = 14; 742458SN/A const int FramePointerReg = 30; 754772Sgblack@eecs.umich.edu 762510SN/A // Some OS syscall use a second register (o1) to return a second value 775958Sgblack@eecs.umich.edu const int SyscallPseudoReturnReg = 9; 782458SN/A 792458SN/A //8K. This value is implmentation specific; and should probably 802458SN/A //be somewhere else. 812458SN/A const int LogVMPageSize = 13; 822458SN/A const int VMPageSize = (1 << LogVMPageSize); 832458SN/A 844070Ssaidi@eecs.umich.edu // real address virtual mapping 854070Ssaidi@eecs.umich.edu // sort of like alpha super page, but less frequently used 864070Ssaidi@eecs.umich.edu const Addr SegKPMEnd = ULL(0xfffffffc00000000); 874070Ssaidi@eecs.umich.edu const Addr SegKPMBase = ULL(0xfffffac000000000); 884070Ssaidi@eecs.umich.edu 892458SN/A //Why does both the previous set of constants and this one exist? 902458SN/A const int PageShift = 13; 913756Sgblack@eecs.umich.edu const int PageBytes = 1ULL << PageShift; 922458SN/A 932458SN/A const int BranchPredAddrShiftAmt = 2; 942458SN/A 952469SN/A StaticInstPtr decodeInst(ExtMachInst); 962458SN/A 973804Ssaidi@eecs.umich.edu /////////// TLB Stuff //////////// 983804Ssaidi@eecs.umich.edu const Addr StartVAddrHole = ULL(0x0000800000000000); 993804Ssaidi@eecs.umich.edu const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 1003804Ssaidi@eecs.umich.edu const Addr VAddrAMask = ULL(0xFFFFFFFF); 1013804Ssaidi@eecs.umich.edu const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 1023804Ssaidi@eecs.umich.edu const Addr BytesInPageMask = ULL(0x1FFF); 1033804Ssaidi@eecs.umich.edu 1044997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1054997Sgblack@eecs.umich.edu // I don't know what it's for, so I don't 1064997Sgblack@eecs.umich.edu // know what SPARC's value should be 1074997Sgblack@eecs.umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 1084997Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 1094997Sgblack@eecs.umich.edu 1104103Ssaidi@eecs.umich.edu enum InterruptTypes 1114103Ssaidi@eecs.umich.edu { 1124103Ssaidi@eecs.umich.edu IT_TRAP_LEVEL_ZERO, 1134103Ssaidi@eecs.umich.edu IT_HINTP, 1144103Ssaidi@eecs.umich.edu IT_INT_VEC, 1154103Ssaidi@eecs.umich.edu IT_CPU_MONDO, 1164103Ssaidi@eecs.umich.edu IT_DEV_MONDO, 1174103Ssaidi@eecs.umich.edu IT_RES_ERROR, 1184103Ssaidi@eecs.umich.edu IT_SOFT_INT, 1194103Ssaidi@eecs.umich.edu NumInterruptTypes 1204103Ssaidi@eecs.umich.edu }; 1214103Ssaidi@eecs.umich.edu 1223804Ssaidi@eecs.umich.edu#endif 1232458SN/A} 1242458SN/A 1252023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 126