isa_traits.hh revision 4772
12023SN/A/*
22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32023SN/A * All rights reserved.
42023SN/A *
52023SN/A * Redistribution and use in source and binary forms, with or without
62023SN/A * modification, are permitted provided that the following conditions are
72023SN/A * met: redistributions of source code must retain the above copyright
82023SN/A * notice, this list of conditions and the following disclaimer;
92023SN/A * redistributions in binary form must reproduce the above copyright
102023SN/A * notice, this list of conditions and the following disclaimer in the
112023SN/A * documentation and/or other materials provided with the distribution;
122023SN/A * neither the name of the copyright holders nor the names of its
132023SN/A * contributors may be used to endorse or promote products derived from
142023SN/A * this software without specific prior written permission.
152023SN/A *
162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282972Sgblack@eecs.umich.edu * Authors: Gabe Black
293804Ssaidi@eecs.umich.edu *          Ali Saidi
302023SN/A */
312023SN/A
322023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
332023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__
342023SN/A
352972Sgblack@eecs.umich.edu#include "arch/sparc/types.hh"
363752Sgblack@eecs.umich.edu#include "arch/sparc/sparc_traits.hh"
372225SN/A#include "config/full_system.hh"
383809Sgblack@eecs.umich.edu#include "sim/host.hh"
392225SN/A
402225SN/Aclass StaticInstPtr;
412023SN/A
422458SN/Anamespace BigEndianGuest {}
432023SN/A
442458SN/Anamespace SparcISA
452458SN/A{
462972Sgblack@eecs.umich.edu    class RegFile;
472972Sgblack@eecs.umich.edu
483809Sgblack@eecs.umich.edu    const int MachineBytes = 8;
493809Sgblack@eecs.umich.edu
502972Sgblack@eecs.umich.edu    //This makes sure the big endian versions of certain functions are used.
512972Sgblack@eecs.umich.edu    using namespace BigEndianGuest;
522972Sgblack@eecs.umich.edu
533437Sgblack@eecs.umich.edu    // SPARC has a delay slot
543093Sksewell@umich.edu    #define ISA_HAS_DELAY_SLOT 1
553093Sksewell@umich.edu
563414Sgblack@eecs.umich.edu    // SPARC NOP (sethi %(hi(0), g0)
573414Sgblack@eecs.umich.edu    const MachInst NoopMachInst = 0x01000000;
582972Sgblack@eecs.umich.edu
592469SN/A    // These enumerate all the registers for dependence tracking.
602469SN/A    enum DependenceTags {
614641Sgblack@eecs.umich.edu        FP_Base_DepTag = 32*3+9,
623980Sgblack@eecs.umich.edu        Ctrl_Base_DepTag = FP_Base_DepTag + 64
632469SN/A    };
642469SN/A
652458SN/A    // semantically meaningful register indices
662458SN/A    const int ZeroReg = 0;	// architecturally meaningful
672458SN/A    // the rest of these depend on the ABI
682458SN/A    const int StackPointerReg = 14;
692458SN/A    const int ReturnAddressReg = 31; // post call, precall is 15
702458SN/A    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
712458SN/A    const int FramePointerReg = 30;
724772Sgblack@eecs.umich.edu
734772Sgblack@eecs.umich.edu    const int ArgumentReg[] = {8, 9, 10, 11, 12, 13};
744772Sgblack@eecs.umich.edu    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
754772Sgblack@eecs.umich.edu
762510SN/A    // Some OS syscall use a second register (o1) to return a second value
774772Sgblack@eecs.umich.edu    const int SyscallPseudoReturnReg = ArgumentReg[1];
782458SN/A
792458SN/A    //XXX These numbers are bogus
802525SN/A    const int MaxInstSrcRegs = 8;
812561SN/A    const int MaxInstDestRegs = 9;
822458SN/A
832458SN/A    //8K. This value is implmentation specific; and should probably
842458SN/A    //be somewhere else.
852458SN/A    const int LogVMPageSize = 13;
862458SN/A    const int VMPageSize = (1 << LogVMPageSize);
872458SN/A
884070Ssaidi@eecs.umich.edu    // real address virtual mapping
894070Ssaidi@eecs.umich.edu    // sort of like alpha super page, but less frequently used
904070Ssaidi@eecs.umich.edu    const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
914070Ssaidi@eecs.umich.edu    const Addr SegKPMBase = ULL(0xfffffac000000000);
924070Ssaidi@eecs.umich.edu
932458SN/A    //Why does both the previous set of constants and this one exist?
942458SN/A    const int PageShift = 13;
953756Sgblack@eecs.umich.edu    const int PageBytes = 1ULL << PageShift;
962458SN/A
972458SN/A    const int BranchPredAddrShiftAmt = 2;
982458SN/A
992469SN/A    StaticInstPtr decodeInst(ExtMachInst);
1002458SN/A
1013804Ssaidi@eecs.umich.edu#if FULL_SYSTEM
1023804Ssaidi@eecs.umich.edu    // I don't know what it's for, so I don't
1033804Ssaidi@eecs.umich.edu    // know what SPARC's value should be
1043804Ssaidi@eecs.umich.edu    // For loading... XXX This maybe could be USegEnd?? --ali
1053804Ssaidi@eecs.umich.edu    const Addr LoadAddrMask = ULL(0xffffffffff);
1063804Ssaidi@eecs.umich.edu
1073804Ssaidi@eecs.umich.edu    /////////// TLB Stuff ////////////
1083804Ssaidi@eecs.umich.edu    const Addr StartVAddrHole = ULL(0x0000800000000000);
1093804Ssaidi@eecs.umich.edu    const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
1103804Ssaidi@eecs.umich.edu    const Addr VAddrAMask = ULL(0xFFFFFFFF);
1113804Ssaidi@eecs.umich.edu    const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
1123804Ssaidi@eecs.umich.edu    const Addr BytesInPageMask = ULL(0x1FFF);
1133804Ssaidi@eecs.umich.edu
1144103Ssaidi@eecs.umich.edu    enum InterruptTypes
1154103Ssaidi@eecs.umich.edu    {
1164103Ssaidi@eecs.umich.edu        IT_TRAP_LEVEL_ZERO,
1174103Ssaidi@eecs.umich.edu        IT_HINTP,
1184103Ssaidi@eecs.umich.edu        IT_INT_VEC,
1194103Ssaidi@eecs.umich.edu        IT_CPU_MONDO,
1204103Ssaidi@eecs.umich.edu        IT_DEV_MONDO,
1214103Ssaidi@eecs.umich.edu        IT_RES_ERROR,
1224103Ssaidi@eecs.umich.edu        IT_SOFT_INT,
1234103Ssaidi@eecs.umich.edu        NumInterruptTypes
1244103Ssaidi@eecs.umich.edu    };
1254103Ssaidi@eecs.umich.edu
1263804Ssaidi@eecs.umich.edu#endif
1272458SN/A}
1282458SN/A
1292023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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