isa_traits.hh revision 3093
12023SN/A/*
22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32023SN/A * All rights reserved.
42023SN/A *
52023SN/A * Redistribution and use in source and binary forms, with or without
62023SN/A * modification, are permitted provided that the following conditions are
72023SN/A * met: redistributions of source code must retain the above copyright
82023SN/A * notice, this list of conditions and the following disclaimer;
92023SN/A * redistributions in binary form must reproduce the above copyright
102023SN/A * notice, this list of conditions and the following disclaimer in the
112023SN/A * documentation and/or other materials provided with the distribution;
122023SN/A * neither the name of the copyright holders nor the names of its
132023SN/A * contributors may be used to endorse or promote products derived from
142023SN/A * this software without specific prior written permission.
152023SN/A *
162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282972Sgblack@eecs.umich.edu * Authors: Gabe Black
292023SN/A */
302023SN/A
312023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
322023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__
332023SN/A
342972Sgblack@eecs.umich.edu#include "arch/sparc/types.hh"
352225SN/A#include "base/misc.hh"
362225SN/A#include "config/full_system.hh"
372225SN/A#include "sim/host.hh"
382225SN/A
392680Sktlim@umich.educlass ThreadContext;
402023SN/Aclass FastCPU;
412023SN/A//class FullCPU;
422225SN/Aclass Checkpoint;
432023SN/A
442225SN/Aclass StaticInst;
452225SN/Aclass StaticInstPtr;
462023SN/A
472458SN/Anamespace BigEndianGuest {}
482023SN/A
492650Ssaidi@eecs.umich.edu#if FULL_SYSTEM
502650Ssaidi@eecs.umich.edu#include "arch/sparc/isa_fullsys_traits.hh"
512650Ssaidi@eecs.umich.edu#endif
522023SN/A
532458SN/Anamespace SparcISA
542458SN/A{
552972Sgblack@eecs.umich.edu    class RegFile;
562972Sgblack@eecs.umich.edu
572972Sgblack@eecs.umich.edu    //This makes sure the big endian versions of certain functions are used.
582972Sgblack@eecs.umich.edu    using namespace BigEndianGuest;
592972Sgblack@eecs.umich.edu
603093Sksewell@umich.edu    // Alpha Does NOT have a delay slot
613093Sksewell@umich.edu    #define ISA_HAS_DELAY_SLOT 1
623093Sksewell@umich.edu
632972Sgblack@eecs.umich.edu    //TODO this needs to be a SPARC Noop
642972Sgblack@eecs.umich.edu    // Alpha UNOP (ldq_u r31,0(r0))
652972Sgblack@eecs.umich.edu    const MachInst NoopMachInst = 0x2ffe0000;
662972Sgblack@eecs.umich.edu
672972Sgblack@eecs.umich.edu    const int NumIntRegs = 32;
682972Sgblack@eecs.umich.edu    const int NumFloatRegs = 64;
692972Sgblack@eecs.umich.edu    const int NumMiscRegs = 40;
702469SN/A
712469SN/A    // These enumerate all the registers for dependence tracking.
722469SN/A    enum DependenceTags {
732469SN/A        // 0..31 are the integer regs 0..31
742972Sgblack@eecs.umich.edu        // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
752972Sgblack@eecs.umich.edu        FP_Base_DepTag = NumIntRegs,
762972Sgblack@eecs.umich.edu        Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
772501SN/A        //XXX These are here solely to get compilation and won't work
782501SN/A        Fpcr_DepTag = 0,
792501SN/A        Uniq_DepTag = 0
802469SN/A    };
812469SN/A
822023SN/A
832972Sgblack@eecs.umich.edu    // MAXTL - maximum trap level
842972Sgblack@eecs.umich.edu    const int MaxPTL = 2;
852972Sgblack@eecs.umich.edu    const int MaxTL  = 6;
862972Sgblack@eecs.umich.edu    const int MaxGL  = 3;
872972Sgblack@eecs.umich.edu    const int MaxPGL = 2;
882458SN/A
892972Sgblack@eecs.umich.edu    // NWINDOWS - number of register windows, can be 3 to 32
902972Sgblack@eecs.umich.edu    const int NWindows = 32;
912458SN/A
922458SN/A    // semantically meaningful register indices
932458SN/A    const int ZeroReg = 0;	// architecturally meaningful
942458SN/A    // the rest of these depend on the ABI
952458SN/A    const int StackPointerReg = 14;
962458SN/A    const int ReturnAddressReg = 31; // post call, precall is 15
972458SN/A    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
982458SN/A    const int FramePointerReg = 30;
992458SN/A    const int ArgumentReg0 = 8;
1002458SN/A    const int ArgumentReg1 = 9;
1012458SN/A    const int ArgumentReg2 = 10;
1022458SN/A    const int ArgumentReg3 = 11;
1032458SN/A    const int ArgumentReg4 = 12;
1042458SN/A    const int ArgumentReg5 = 13;
1052510SN/A    // Some OS syscall use a second register (o1) to return a second value
1062458SN/A    const int SyscallPseudoReturnReg = ArgumentReg1;
1072458SN/A
1082458SN/A    //XXX These numbers are bogus
1092525SN/A    const int MaxInstSrcRegs = 8;
1102561SN/A    const int MaxInstDestRegs = 9;
1112458SN/A
1122458SN/A    //8K. This value is implmentation specific; and should probably
1132458SN/A    //be somewhere else.
1142458SN/A    const int LogVMPageSize = 13;
1152458SN/A    const int VMPageSize = (1 << LogVMPageSize);
1162458SN/A
1172458SN/A    //Why does both the previous set of constants and this one exist?
1182458SN/A    const int PageShift = 13;
1192458SN/A    const int PageBytes = ULL(1) << PageShift;
1202458SN/A
1212458SN/A    const int BranchPredAddrShiftAmt = 2;
1222458SN/A
1232474SN/A    const int MachineBytes = 8;
1242458SN/A    const int WordBytes = 4;
1252458SN/A    const int HalfwordBytes = 2;
1262458SN/A    const int ByteBytes = 1;
1272458SN/A
1282458SN/A    void serialize(std::ostream & os);
1292458SN/A
1302458SN/A    void unserialize(Checkpoint *cp, const std::string &section);
1312458SN/A
1322469SN/A    StaticInstPtr decodeInst(ExtMachInst);
1332458SN/A
1342458SN/A    // return a no-op instruction... used for instruction fetch faults
1352458SN/A    extern const MachInst NoopMachInst;
1362458SN/A}
1372458SN/A
1382023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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