isa_traits.hh revision 2680
12023SN/A/*
22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32023SN/A * All rights reserved.
42023SN/A *
52023SN/A * Redistribution and use in source and binary forms, with or without
62023SN/A * modification, are permitted provided that the following conditions are
72023SN/A * met: redistributions of source code must retain the above copyright
82023SN/A * notice, this list of conditions and the following disclaimer;
92023SN/A * redistributions in binary form must reproduce the above copyright
102023SN/A * notice, this list of conditions and the following disclaimer in the
112023SN/A * documentation and/or other materials provided with the distribution;
122023SN/A * neither the name of the copyright holders nor the names of its
132023SN/A * contributors may be used to endorse or promote products derived from
142023SN/A * this software without specific prior written permission.
152023SN/A *
162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Korey Sewell
292665Ssaidi@eecs.umich.edu *          Gabe Black
302023SN/A */
312023SN/A
322023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
332023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__
342023SN/A
352225SN/A#include "base/misc.hh"
362225SN/A#include "config/full_system.hh"
372225SN/A#include "sim/host.hh"
382225SN/A
392680Sktlim@umich.educlass ThreadContext;
402023SN/Aclass FastCPU;
412023SN/A//class FullCPU;
422225SN/Aclass Checkpoint;
432023SN/A
442225SN/Aclass StaticInst;
452225SN/Aclass StaticInstPtr;
462023SN/A
472458SN/Anamespace BigEndianGuest {}
482023SN/A
492225SN/A#if !FULL_SYSTEM
502225SN/Aclass SyscallReturn
512225SN/A{
522225SN/A  public:
532225SN/A    template <class T>
542225SN/A    SyscallReturn(T v, bool s)
552225SN/A    {
562225SN/A        retval = (uint64_t)v;
572225SN/A        success = s;
582225SN/A    }
592023SN/A
602225SN/A    template <class T>
612225SN/A    SyscallReturn(T v)
622225SN/A    {
632225SN/A        success = (v >= 0);
642225SN/A        retval = (uint64_t)v;
652225SN/A    }
662023SN/A
672225SN/A    ~SyscallReturn() {}
682023SN/A
692225SN/A    SyscallReturn& operator=(const SyscallReturn& s)
702225SN/A    {
712225SN/A        retval = s.retval;
722225SN/A        success = s.success;
732225SN/A        return *this;
742225SN/A    }
752023SN/A
762225SN/A    bool successful() { return success; }
772225SN/A    uint64_t value() { return retval; }
782023SN/A
792225SN/A    private:
802225SN/A    uint64_t retval;
812225SN/A    bool success;
822023SN/A};
832023SN/A
842023SN/A#endif
852023SN/A
862650Ssaidi@eecs.umich.edu#if FULL_SYSTEM
872650Ssaidi@eecs.umich.edu#include "arch/sparc/isa_fullsys_traits.hh"
882650Ssaidi@eecs.umich.edu#endif
892023SN/A
902458SN/Anamespace SparcISA
912458SN/A{
922469SN/A
932469SN/A    // These enumerate all the registers for dependence tracking.
942469SN/A    enum DependenceTags {
952469SN/A        // 0..31 are the integer regs 0..31
962469SN/A        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
972469SN/A        FP_Base_DepTag = 32,
982469SN/A        Ctrl_Base_DepTag = 96,
992501SN/A        //XXX These are here solely to get compilation and won't work
1002501SN/A        Fpcr_DepTag = 0,
1012501SN/A        Uniq_DepTag = 0
1022469SN/A    };
1032469SN/A
1042458SN/A    //This makes sure the big endian versions of certain functions are used.
1052458SN/A    using namespace BigEndianGuest;
1062023SN/A
1072458SN/A    typedef uint32_t MachInst;
1082458SN/A    typedef uint64_t ExtMachInst;
1092458SN/A
1102458SN/A    const int NumIntRegs = 32;
1112458SN/A    const int NumFloatRegs = 64;
1122458SN/A    const int NumMiscRegs = 32;
1132458SN/A
1142458SN/A    // semantically meaningful register indices
1152458SN/A    const int ZeroReg = 0;	// architecturally meaningful
1162458SN/A    // the rest of these depend on the ABI
1172458SN/A    const int StackPointerReg = 14;
1182458SN/A    const int ReturnAddressReg = 31; // post call, precall is 15
1192458SN/A    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
1202458SN/A    const int FramePointerReg = 30;
1212458SN/A    const int ArgumentReg0 = 8;
1222458SN/A    const int ArgumentReg1 = 9;
1232458SN/A    const int ArgumentReg2 = 10;
1242458SN/A    const int ArgumentReg3 = 11;
1252458SN/A    const int ArgumentReg4 = 12;
1262458SN/A    const int ArgumentReg5 = 13;
1272510SN/A    // Some OS syscall use a second register (o1) to return a second value
1282458SN/A    const int SyscallPseudoReturnReg = ArgumentReg1;
1292458SN/A
1302458SN/A    //XXX These numbers are bogus
1312525SN/A    const int MaxInstSrcRegs = 8;
1322561SN/A    const int MaxInstDestRegs = 9;
1332458SN/A
1342458SN/A    typedef uint64_t IntReg;
1352458SN/A
1362458SN/A    // control register file contents
1372458SN/A    typedef uint64_t MiscReg;
1382458SN/A
1392458SN/A    typedef double FloatReg;
1402458SN/A    typedef uint64_t FloatRegBits;
1412458SN/A
1422458SN/A    //8K. This value is implmentation specific; and should probably
1432458SN/A    //be somewhere else.
1442458SN/A    const int LogVMPageSize = 13;
1452458SN/A    const int VMPageSize = (1 << LogVMPageSize);
1462458SN/A
1472458SN/A    //Why does both the previous set of constants and this one exist?
1482458SN/A    const int PageShift = 13;
1492458SN/A    const int PageBytes = ULL(1) << PageShift;
1502458SN/A
1512458SN/A    const int BranchPredAddrShiftAmt = 2;
1522458SN/A
1532474SN/A    const int MachineBytes = 8;
1542458SN/A    const int WordBytes = 4;
1552458SN/A    const int HalfwordBytes = 2;
1562458SN/A    const int ByteBytes = 1;
1572458SN/A
1582458SN/A    void serialize(std::ostream & os);
1592458SN/A
1602458SN/A    void unserialize(Checkpoint *cp, const std::string &section);
1612458SN/A
1622469SN/A    StaticInstPtr decodeInst(ExtMachInst);
1632458SN/A
1642458SN/A    // return a no-op instruction... used for instruction fetch faults
1652458SN/A    extern const MachInst NoopMachInst;
1662458SN/A}
1672458SN/A
1682458SN/A#include "arch/sparc/regfile.hh"
1692458SN/A
1702458SN/Anamespace SparcISA
1712458SN/A{
1722458SN/A
1732458SN/A#if !FULL_SYSTEM
1742458SN/A    static inline void setSyscallReturn(SyscallReturn return_value,
1752458SN/A            RegFile *regs)
1762458SN/A    {
1772458SN/A        // check for error condition.  SPARC syscall convention is to
1782458SN/A        // indicate success/failure in reg the carry bit of the ccr
1792458SN/A        // and put the return value itself in the standard return value reg ().
1802458SN/A        if (return_value.successful()) {
1812646Ssaidi@eecs.umich.edu            // no error, clear XCC.C
1822646Ssaidi@eecs.umich.edu            regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF);
1832525SN/A            regs->setIntReg(ReturnValueReg, return_value.value());
1842458SN/A        } else {
1852646Ssaidi@eecs.umich.edu            // got an error, set XCC.C
1862646Ssaidi@eecs.umich.edu            regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10);
1872525SN/A            regs->setIntReg(ReturnValueReg, return_value.value());
1882458SN/A        }
1892458SN/A    }
1902023SN/A#endif
1912458SN/A};
1922023SN/A
1932023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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