operands.isa revision 8449:4be49ad47c74
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : 'int8_t', 33 'ub' : 'uint8_t', 34 'shw' : 'int16_t', 35 'uhw' : 'uint16_t', 36 'sw' : 'int32_t', 37 'uw' : 'uint32_t', 38 'sdw' : 'int64_t', 39 'udw' : 'uint64_t', 40 'tudw' : 'Twin64_t', 41 'tuw' : 'Twin32_t', 42 'sf' : 'float', 43 'df' : 'double' 44}}; 45 46output header {{ 47 // A function to "decompress" double and quad floating point 48 // register numbers stuffed into 5 bit fields. These have their 49 // MSB put in the LSB position but are otherwise normal. 50 static inline unsigned int 51 dfpr(unsigned int regNum) 52 { 53 return (regNum & (~1)) | ((regNum & 1) << 5); 54 } 55 56 static inline unsigned int 57 dfprl(unsigned int regNum) 58 { 59 return dfpr(regNum) & (~0x1); 60 } 61 62 static inline unsigned int 63 dfprh(unsigned int regNum) 64 { 65 return dfpr(regNum) | 0x1; 66 } 67}}; 68 69def operands {{ 70 # Int regs default to unsigned, but code should not count on this. 71 # For clarity, descriptions that depend on unsigned behavior should 72 # explicitly specify '.uq'. 73 74 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 75 # The Rd from the previous window 76 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 77 # The Rd from the next window 78 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 79 # For microcoded twin load instructions, RdTwin appears in the "code" 80 # for the instruction is replaced by RdLow or RdHigh by the format 81 # before it's processed by the iop. 82 # The low (even) register of a two register pair 83 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 84 # The high (odd) register of a two register pair 85 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 86 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 87 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 88 # A microcode register. Right now, this is the only one. 89 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 90 # Because double and quad precision register numbers are decoded 91 # differently, they get different operands. The single precision versions 92 # have an s post pended to their name. 93 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 94 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 95 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 96 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 97 # Each Frd_N refers to the Nth double precision register from Frd. 98 # Note that this adds twice N to the register number. 99 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 100 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 101 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 102 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 103 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 104 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 105 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 106 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 107 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 108 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 109 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 110 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 111 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 112 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 113 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 114 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 115 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 116 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 117 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 118 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 119 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 120 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 121 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 122 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 123 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 124 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 125 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 126 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 127 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 128 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 129 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 130 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 131 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 132 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 133 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 134 # Registers which are used explicitly in instructions 135 'R0': ('IntReg', 'udw', '0', None, 6), 136 'R1': ('IntReg', 'udw', '1', None, 7), 137 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 138 'R16': ('IntReg', 'udw', '16', None, 9), 139 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 140 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 141 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 142 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 143 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 144 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 145 146 # Control registers 147# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 148# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 149 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 150 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 151 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 152 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 153 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 154 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 155# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 156 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 157 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 158 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 159 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 160 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 161 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 162 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 163 164 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 165 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 166 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 167 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 168 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 169 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 170 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 171 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 172 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 173 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 174# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 175# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 176# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 177# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 178# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 179 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 180 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 181 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 182 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 183 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 184 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 185 186 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 187 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 188 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 189 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 190 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 191 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 192 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 193 194 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 195 # Mem gets a large number so it's always last 196 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 197 198}}; 199