operands.isa revision 4098
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : ('signed int', 8), 33 'ub' : ('unsigned int', 8), 34 'shw' : ('signed int', 16), 35 'uhw' : ('unsigned int', 16), 36 'sw' : ('signed int', 32), 37 'uw' : ('unsigned int', 32), 38 'sdw' : ('signed int', 64), 39 'udw' : ('unsigned int', 64), 40 'tudw' : ('twin int', 64), 41 'sf' : ('float', 32), 42 'df' : ('float', 64), 43 'qf' : ('float', 128) 44}}; 45 46output header {{ 47 // A function to "decompress" double and quad floating point 48 // register numbers stuffed into 5 bit fields. These have their 49 // MSB put in the LSB position but are otherwise normal. 50 static inline unsigned int dfpr(unsigned int regNum) 51 { 52 return (regNum & (~1)) | ((regNum & 1) << 5); 53 } 54}}; 55 56def operands {{ 57 # Int regs default to unsigned, but code should not count on this. 58 # For clarity, descriptions that depend on unsigned behavior should 59 # explicitly specify '.uq'. 60 61 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 62 # The Rd from the previous window 63 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 64 # The Rd from the next window 65 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 66 # For microcoded twin load instructions, RdTwin appears in the "code" 67 # for the instruction is replaced by RdLow or RdHigh by the format 68 # before it's processed by the iop. 69 # The low (even) register of a two register pair 70 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 71 # The high (odd) register of a two register pair 72 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 73 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 74 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 75 # A microcode register. Right now, this is the only one. 76 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 77 # Because double and quad precision register numbers are decoded 78 # differently, they get different operands. The single precision versions 79 # have an s post pended to their name. 80 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 81 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 82 # Each Frd_N refers to the Nth double precision register from Frd. 83 # Note that this adds twice N to the register number. 84 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 85 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 86 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 87 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 88 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 89 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 90 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 91 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 92 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 93 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 94 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 95 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 96 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 97 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 98 # Registers which are used explicitly in instructions 99 'R0': ('IntReg', 'udw', '0', None, 6), 100 'R1': ('IntReg', 'udw', '1', None, 7), 101 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 102 'R16': ('IntReg', 'udw', '16', None, 9), 103 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 104 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 105 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 106 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 107 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 108 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 109 110 # Control registers 111# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 112# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 113 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 114 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 115 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 116 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 117 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 118 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 119 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), 120 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 121 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 122 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 123 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 124 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 125 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 126 127 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 128 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 129 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 130 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 131 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 132 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 133 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 134 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 135 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 136 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 137# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 138# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 139# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 140# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 141# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 142 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 143 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 144 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 145 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 146 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 147 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 148 149 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 150 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 151 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 152 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 153 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 154 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 155 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 156 157 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), 158 # Mem gets a large number so it's always last 159 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 160 161}}; 162