operands.isa revision 3272:c28038eaefb8
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : ('signed int', 8), 33 'ub' : ('unsigned int', 8), 34 'shw' : ('signed int', 16), 35 'uhw' : ('unsigned int', 16), 36 'sw' : ('signed int', 32), 37 'uw' : ('unsigned int', 32), 38 'sdw' : ('signed int', 64), 39 'udw' : ('unsigned int', 64), 40 'sf' : ('float', 32), 41 'df' : ('float', 64), 42 'qf' : ('float', 128) 43}}; 44 45def operands {{ 46 # Int regs default to unsigned, but code should not count on this. 47 # For clarity, descriptions that depend on unsigned behavior should 48 # explicitly specify '.uq'. 49 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 50 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 51 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 52 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 53 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 54 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10), 55 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10), 56 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10), 57 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10), 58 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10), 59 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10), 60 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10), 61 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10), 62 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10), 63 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 64 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 65 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 66 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 67 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 68 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 69 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 70 'R0': ('IntReg', 'udw', '0', None, 6), 71 'R1': ('IntReg', 'udw', '1', None, 7), 72 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 73 'R16': ('IntReg', 'udw', '16', None, 9), 74 75 # Control registers 76 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 77 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 78 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 79 80 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 81 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 82 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 83 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 84 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), 85 86 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 87 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 88 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 89 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 90 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 91 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 92 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 93 94 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 95 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56) 96 97}}; 98