operands.isa revision 8449
13993Sgblack@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 328449Sgblack@eecs.umich.edu 'sb' : 'int8_t', 338449Sgblack@eecs.umich.edu 'ub' : 'uint8_t', 348449Sgblack@eecs.umich.edu 'shw' : 'int16_t', 358449Sgblack@eecs.umich.edu 'uhw' : 'uint16_t', 368449Sgblack@eecs.umich.edu 'sw' : 'int32_t', 378449Sgblack@eecs.umich.edu 'uw' : 'uint32_t', 388449Sgblack@eecs.umich.edu 'sdw' : 'int64_t', 398449Sgblack@eecs.umich.edu 'udw' : 'uint64_t', 408449Sgblack@eecs.umich.edu 'tudw' : 'Twin64_t', 418449Sgblack@eecs.umich.edu 'tuw' : 'Twin32_t', 428449Sgblack@eecs.umich.edu 'sf' : 'float', 438449Sgblack@eecs.umich.edu 'df' : 'double' 442023SN/A}}; 452023SN/A 463279Sgblack@eecs.umich.eduoutput header {{ 473279Sgblack@eecs.umich.edu // A function to "decompress" double and quad floating point 483279Sgblack@eecs.umich.edu // register numbers stuffed into 5 bit fields. These have their 493279Sgblack@eecs.umich.edu // MSB put in the LSB position but are otherwise normal. 507741Sgblack@eecs.umich.edu static inline unsigned int 517741Sgblack@eecs.umich.edu dfpr(unsigned int regNum) 523279Sgblack@eecs.umich.edu { 533381Sgblack@eecs.umich.edu return (regNum & (~1)) | ((regNum & 1) << 5); 543279Sgblack@eecs.umich.edu } 554362Sgblack@eecs.umich.edu 567741Sgblack@eecs.umich.edu static inline unsigned int 577741Sgblack@eecs.umich.edu dfprl(unsigned int regNum) 584362Sgblack@eecs.umich.edu { 594362Sgblack@eecs.umich.edu return dfpr(regNum) & (~0x1); 604362Sgblack@eecs.umich.edu } 614362Sgblack@eecs.umich.edu 627741Sgblack@eecs.umich.edu static inline unsigned int 637741Sgblack@eecs.umich.edu dfprh(unsigned int regNum) 644362Sgblack@eecs.umich.edu { 654362Sgblack@eecs.umich.edu return dfpr(regNum) | 0x1; 664362Sgblack@eecs.umich.edu } 673279Sgblack@eecs.umich.edu}}; 683279Sgblack@eecs.umich.edu 692023SN/Adef operands {{ 702023SN/A # Int regs default to unsigned, but code should not count on this. 712023SN/A # For clarity, descriptions that depend on unsigned behavior should 722023SN/A # explicitly specify '.uq'. 733761Sgblack@eecs.umich.edu 747799Sgblack@eecs.umich.edu 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 753761Sgblack@eecs.umich.edu # The Rd from the previous window 767799Sgblack@eecs.umich.edu 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 773761Sgblack@eecs.umich.edu # The Rd from the next window 787799Sgblack@eecs.umich.edu 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 793835Sgblack@eecs.umich.edu # For microcoded twin load instructions, RdTwin appears in the "code" 803952Sgblack@eecs.umich.edu # for the instruction is replaced by RdLow or RdHigh by the format 813835Sgblack@eecs.umich.edu # before it's processed by the iop. 823761Sgblack@eecs.umich.edu # The low (even) register of a two register pair 837799Sgblack@eecs.umich.edu 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 843761Sgblack@eecs.umich.edu # The high (odd) register of a two register pair 857799Sgblack@eecs.umich.edu 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 867799Sgblack@eecs.umich.edu 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 877799Sgblack@eecs.umich.edu 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 883761Sgblack@eecs.umich.edu # A microcode register. Right now, this is the only one. 897799Sgblack@eecs.umich.edu 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 903761Sgblack@eecs.umich.edu # Because double and quad precision register numbers are decoded 913761Sgblack@eecs.umich.edu # differently, they get different operands. The single precision versions 923761Sgblack@eecs.umich.edu # have an s post pended to their name. 937799Sgblack@eecs.umich.edu 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 947799Sgblack@eecs.umich.edu #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 957799Sgblack@eecs.umich.edu 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 967799Sgblack@eecs.umich.edu 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 973279Sgblack@eecs.umich.edu # Each Frd_N refers to the Nth double precision register from Frd. 983279Sgblack@eecs.umich.edu # Note that this adds twice N to the register number. 997799Sgblack@eecs.umich.edu #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 1007799Sgblack@eecs.umich.edu 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 1017799Sgblack@eecs.umich.edu 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 1027799Sgblack@eecs.umich.edu #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 1037799Sgblack@eecs.umich.edu 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 1047799Sgblack@eecs.umich.edu 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 1057799Sgblack@eecs.umich.edu #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 1067799Sgblack@eecs.umich.edu 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 1077799Sgblack@eecs.umich.edu 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 1087799Sgblack@eecs.umich.edu #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 1097799Sgblack@eecs.umich.edu 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 1107799Sgblack@eecs.umich.edu 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 1117799Sgblack@eecs.umich.edu #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 1127799Sgblack@eecs.umich.edu 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 1137799Sgblack@eecs.umich.edu 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 1147799Sgblack@eecs.umich.edu #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 1157799Sgblack@eecs.umich.edu 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 1167799Sgblack@eecs.umich.edu 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 1177799Sgblack@eecs.umich.edu #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 1187799Sgblack@eecs.umich.edu 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 1197799Sgblack@eecs.umich.edu 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 1207799Sgblack@eecs.umich.edu #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 1217799Sgblack@eecs.umich.edu 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 1227799Sgblack@eecs.umich.edu 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 1237799Sgblack@eecs.umich.edu 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 1247799Sgblack@eecs.umich.edu #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 1257799Sgblack@eecs.umich.edu 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 1267799Sgblack@eecs.umich.edu 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 1277799Sgblack@eecs.umich.edu 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 1287799Sgblack@eecs.umich.edu #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 1297799Sgblack@eecs.umich.edu 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 1307799Sgblack@eecs.umich.edu 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 1317790Sgblack@eecs.umich.edu 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 1327790Sgblack@eecs.umich.edu 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 1337790Sgblack@eecs.umich.edu 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 1343761Sgblack@eecs.umich.edu # Registers which are used explicitly in instructions 1357799Sgblack@eecs.umich.edu 'R0': ('IntReg', 'udw', '0', None, 6), 1367799Sgblack@eecs.umich.edu 'R1': ('IntReg', 'udw', '1', None, 7), 1377799Sgblack@eecs.umich.edu 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 1387799Sgblack@eecs.umich.edu 'R16': ('IntReg', 'udw', '16', None, 9), 1394098Ssaidi@eecs.umich.edu 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 1404098Ssaidi@eecs.umich.edu 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 1414098Ssaidi@eecs.umich.edu 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 1424098Ssaidi@eecs.umich.edu 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 1434098Ssaidi@eecs.umich.edu 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 1444098Ssaidi@eecs.umich.edu 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 1452646Ssaidi@eecs.umich.edu 1462469SN/A # Control registers 1477799Sgblack@eecs.umich.edu# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 1487799Sgblack@eecs.umich.edu# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 1497799Sgblack@eecs.umich.edu 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 1507799Sgblack@eecs.umich.edu 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 1517799Sgblack@eecs.umich.edu 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 1527799Sgblack@eecs.umich.edu 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 1537799Sgblack@eecs.umich.edu 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 1547799Sgblack@eecs.umich.edu 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 1557799Sgblack@eecs.umich.edu# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 1567799Sgblack@eecs.umich.edu 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 1577799Sgblack@eecs.umich.edu 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 1587799Sgblack@eecs.umich.edu 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 1597799Sgblack@eecs.umich.edu 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 1607799Sgblack@eecs.umich.edu 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 1617799Sgblack@eecs.umich.edu 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 1627799Sgblack@eecs.umich.edu 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 1632646Ssaidi@eecs.umich.edu 1647799Sgblack@eecs.umich.edu 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 1657799Sgblack@eecs.umich.edu 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 1667799Sgblack@eecs.umich.edu 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 1677799Sgblack@eecs.umich.edu 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 1687799Sgblack@eecs.umich.edu 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 1697799Sgblack@eecs.umich.edu 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 1707799Sgblack@eecs.umich.edu 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 1717799Sgblack@eecs.umich.edu 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 1727799Sgblack@eecs.umich.edu 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 1737799Sgblack@eecs.umich.edu 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 1747799Sgblack@eecs.umich.edu# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 1757799Sgblack@eecs.umich.edu# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 1767799Sgblack@eecs.umich.edu# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 1777799Sgblack@eecs.umich.edu# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 1787799Sgblack@eecs.umich.edu# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 1797799Sgblack@eecs.umich.edu 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 1807799Sgblack@eecs.umich.edu 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 1817799Sgblack@eecs.umich.edu 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 1827799Sgblack@eecs.umich.edu 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 1837799Sgblack@eecs.umich.edu 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 1843587Sgblack@eecs.umich.edu 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 1852646Ssaidi@eecs.umich.edu 1867799Sgblack@eecs.umich.edu 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 1877799Sgblack@eecs.umich.edu 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 1887799Sgblack@eecs.umich.edu 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 1897799Sgblack@eecs.umich.edu 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 1907799Sgblack@eecs.umich.edu 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 1917799Sgblack@eecs.umich.edu 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 1927799Sgblack@eecs.umich.edu 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 1932646Ssaidi@eecs.umich.edu 1947799Sgblack@eecs.umich.edu 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 1953388Sgblack@eecs.umich.edu # Mem gets a large number so it's always last 1967799Sgblack@eecs.umich.edu 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 1972646Ssaidi@eecs.umich.edu 1982023SN/A}}; 199