operands.isa revision 7720
13993Sgblack@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 322023SN/A 'sb' : ('signed int', 8), 332023SN/A 'ub' : ('unsigned int', 8), 342023SN/A 'shw' : ('signed int', 16), 352023SN/A 'uhw' : ('unsigned int', 16), 362023SN/A 'sw' : ('signed int', 32), 372023SN/A 'uw' : ('unsigned int', 32), 382023SN/A 'sdw' : ('signed int', 64), 392023SN/A 'udw' : ('unsigned int', 64), 404115Ssaidi@eecs.umich.edu 'tudw' : ('twin64 int', 64), 414115Ssaidi@eecs.umich.edu 'tuw' : ('twin32 int', 32), 422023SN/A 'sf' : ('float', 32), 432023SN/A 'df' : ('float', 64), 442023SN/A 'qf' : ('float', 128) 452023SN/A}}; 462023SN/A 473279Sgblack@eecs.umich.eduoutput header {{ 483279Sgblack@eecs.umich.edu // A function to "decompress" double and quad floating point 493279Sgblack@eecs.umich.edu // register numbers stuffed into 5 bit fields. These have their 503279Sgblack@eecs.umich.edu // MSB put in the LSB position but are otherwise normal. 513279Sgblack@eecs.umich.edu static inline unsigned int dfpr(unsigned int regNum) 523279Sgblack@eecs.umich.edu { 533381Sgblack@eecs.umich.edu return (regNum & (~1)) | ((regNum & 1) << 5); 543279Sgblack@eecs.umich.edu } 554362Sgblack@eecs.umich.edu 564362Sgblack@eecs.umich.edu static inline unsigned int dfprl(unsigned int regNum) 574362Sgblack@eecs.umich.edu { 584362Sgblack@eecs.umich.edu return dfpr(regNum) & (~0x1); 594362Sgblack@eecs.umich.edu } 604362Sgblack@eecs.umich.edu 614362Sgblack@eecs.umich.edu static inline unsigned int dfprh(unsigned int regNum) 624362Sgblack@eecs.umich.edu { 634362Sgblack@eecs.umich.edu return dfpr(regNum) | 0x1; 644362Sgblack@eecs.umich.edu } 653279Sgblack@eecs.umich.edu}}; 663279Sgblack@eecs.umich.edu 672023SN/Adef operands {{ 682023SN/A # Int regs default to unsigned, but code should not count on this. 692023SN/A # For clarity, descriptions that depend on unsigned behavior should 702023SN/A # explicitly specify '.uq'. 713761Sgblack@eecs.umich.edu 722501SN/A 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 733761Sgblack@eecs.umich.edu # The Rd from the previous window 743761Sgblack@eecs.umich.edu 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 753761Sgblack@eecs.umich.edu # The Rd from the next window 763761Sgblack@eecs.umich.edu 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 773835Sgblack@eecs.umich.edu # For microcoded twin load instructions, RdTwin appears in the "code" 783952Sgblack@eecs.umich.edu # for the instruction is replaced by RdLow or RdHigh by the format 793835Sgblack@eecs.umich.edu # before it's processed by the iop. 803761Sgblack@eecs.umich.edu # The low (even) register of a two register pair 813761Sgblack@eecs.umich.edu 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 823761Sgblack@eecs.umich.edu # The high (odd) register of a two register pair 833761Sgblack@eecs.umich.edu 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 843761Sgblack@eecs.umich.edu 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 853761Sgblack@eecs.umich.edu 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 863761Sgblack@eecs.umich.edu # A microcode register. Right now, this is the only one. 873761Sgblack@eecs.umich.edu 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 883761Sgblack@eecs.umich.edu # Because double and quad precision register numbers are decoded 893761Sgblack@eecs.umich.edu # differently, they get different operands. The single precision versions 903761Sgblack@eecs.umich.edu # have an s post pended to their name. 913279Sgblack@eecs.umich.edu 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 924362Sgblack@eecs.umich.edu #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 934362Sgblack@eecs.umich.edu 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 944362Sgblack@eecs.umich.edu 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 953279Sgblack@eecs.umich.edu # Each Frd_N refers to the Nth double precision register from Frd. 963279Sgblack@eecs.umich.edu # Note that this adds twice N to the register number. 974362Sgblack@eecs.umich.edu #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 984362Sgblack@eecs.umich.edu 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 994362Sgblack@eecs.umich.edu 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 1004362Sgblack@eecs.umich.edu #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 1014362Sgblack@eecs.umich.edu 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 1024362Sgblack@eecs.umich.edu 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 1034362Sgblack@eecs.umich.edu #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 1044362Sgblack@eecs.umich.edu 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 1054362Sgblack@eecs.umich.edu 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 1064362Sgblack@eecs.umich.edu #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 1074362Sgblack@eecs.umich.edu 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 1084362Sgblack@eecs.umich.edu 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 1094362Sgblack@eecs.umich.edu #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 1104362Sgblack@eecs.umich.edu 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 1114362Sgblack@eecs.umich.edu 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 1124362Sgblack@eecs.umich.edu #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 1134362Sgblack@eecs.umich.edu 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 1144362Sgblack@eecs.umich.edu 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 1154362Sgblack@eecs.umich.edu #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 1164362Sgblack@eecs.umich.edu 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 1174362Sgblack@eecs.umich.edu 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 1184362Sgblack@eecs.umich.edu #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 1194362Sgblack@eecs.umich.edu 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 1204362Sgblack@eecs.umich.edu 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 1213993Sgblack@eecs.umich.edu 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 1224362Sgblack@eecs.umich.edu #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 1234362Sgblack@eecs.umich.edu 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 1244362Sgblack@eecs.umich.edu 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 1253993Sgblack@eecs.umich.edu 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 1264362Sgblack@eecs.umich.edu #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 1274362Sgblack@eecs.umich.edu 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 1284362Sgblack@eecs.umich.edu 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 1297720Sgblack@eecs.umich.edu 'PCS': ('PCState', 'udw', None, (None, None, 'IsControl'), 30), 1303761Sgblack@eecs.umich.edu # Registers which are used explicitly in instructions 1312516SN/A 'R0': ('IntReg', 'udw', '0', None, 6), 1322561SN/A 'R1': ('IntReg', 'udw', '1', None, 7), 1332561SN/A 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 1342561SN/A 'R16': ('IntReg', 'udw', '16', None, 9), 1354098Ssaidi@eecs.umich.edu 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 1364098Ssaidi@eecs.umich.edu 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 1374098Ssaidi@eecs.umich.edu 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 1384098Ssaidi@eecs.umich.edu 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 1394098Ssaidi@eecs.umich.edu 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 1404098Ssaidi@eecs.umich.edu 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 1412646Ssaidi@eecs.umich.edu 1422469SN/A # Control registers 1433761Sgblack@eecs.umich.edu# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 1443761Sgblack@eecs.umich.edu# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 1453761Sgblack@eecs.umich.edu 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 1463761Sgblack@eecs.umich.edu 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 1472954Sgblack@eecs.umich.edu 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 1483587Sgblack@eecs.umich.edu 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 1493587Sgblack@eecs.umich.edu 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 1503587Sgblack@eecs.umich.edu 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 1514641Sgblack@eecs.umich.edu# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 1524641Sgblack@eecs.umich.edu 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 1533587Sgblack@eecs.umich.edu 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 1543587Sgblack@eecs.umich.edu 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 1553587Sgblack@eecs.umich.edu 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 1563587Sgblack@eecs.umich.edu 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 1573587Sgblack@eecs.umich.edu 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 1583587Sgblack@eecs.umich.edu 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 1592646Ssaidi@eecs.umich.edu 1603587Sgblack@eecs.umich.edu 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 1613587Sgblack@eecs.umich.edu 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 1623587Sgblack@eecs.umich.edu 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 1633587Sgblack@eecs.umich.edu 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 1643587Sgblack@eecs.umich.edu 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 1653587Sgblack@eecs.umich.edu 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 1663587Sgblack@eecs.umich.edu 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 1673587Sgblack@eecs.umich.edu 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 1683587Sgblack@eecs.umich.edu 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 1693793Sgblack@eecs.umich.edu 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 1703761Sgblack@eecs.umich.edu# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 1713761Sgblack@eecs.umich.edu# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 1723761Sgblack@eecs.umich.edu# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 1733761Sgblack@eecs.umich.edu# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 1743761Sgblack@eecs.umich.edu# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 1753761Sgblack@eecs.umich.edu 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 1763761Sgblack@eecs.umich.edu 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 1773761Sgblack@eecs.umich.edu 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 1783761Sgblack@eecs.umich.edu 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 1793761Sgblack@eecs.umich.edu 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 1803587Sgblack@eecs.umich.edu 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 1812646Ssaidi@eecs.umich.edu 1823587Sgblack@eecs.umich.edu 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 1833587Sgblack@eecs.umich.edu 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 1843587Sgblack@eecs.umich.edu 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 1853587Sgblack@eecs.umich.edu 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 1863587Sgblack@eecs.umich.edu 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 1873587Sgblack@eecs.umich.edu 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 1883600Sgblack@eecs.umich.edu 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 1892646Ssaidi@eecs.umich.edu 1904634Sgblack@eecs.umich.edu 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 1913388Sgblack@eecs.umich.edu # Mem gets a large number so it's always last 1923388Sgblack@eecs.umich.edu 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 1932646Ssaidi@eecs.umich.edu 1942023SN/A}}; 195