operands.isa revision 4158
13993Sgblack@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 322023SN/A 'sb' : ('signed int', 8), 332023SN/A 'ub' : ('unsigned int', 8), 342023SN/A 'shw' : ('signed int', 16), 352023SN/A 'uhw' : ('unsigned int', 16), 362023SN/A 'sw' : ('signed int', 32), 372023SN/A 'uw' : ('unsigned int', 32), 382023SN/A 'sdw' : ('signed int', 64), 392023SN/A 'udw' : ('unsigned int', 64), 404115Ssaidi@eecs.umich.edu 'tudw' : ('twin64 int', 64), 414115Ssaidi@eecs.umich.edu 'tuw' : ('twin32 int', 32), 422023SN/A 'sf' : ('float', 32), 432023SN/A 'df' : ('float', 64), 442023SN/A 'qf' : ('float', 128) 452023SN/A}}; 462023SN/A 473279Sgblack@eecs.umich.eduoutput header {{ 483279Sgblack@eecs.umich.edu // A function to "decompress" double and quad floating point 493279Sgblack@eecs.umich.edu // register numbers stuffed into 5 bit fields. These have their 503279Sgblack@eecs.umich.edu // MSB put in the LSB position but are otherwise normal. 513279Sgblack@eecs.umich.edu static inline unsigned int dfpr(unsigned int regNum) 523279Sgblack@eecs.umich.edu { 533381Sgblack@eecs.umich.edu return (regNum & (~1)) | ((regNum & 1) << 5); 543279Sgblack@eecs.umich.edu } 553279Sgblack@eecs.umich.edu}}; 563279Sgblack@eecs.umich.edu 572023SN/Adef operands {{ 582023SN/A # Int regs default to unsigned, but code should not count on this. 592023SN/A # For clarity, descriptions that depend on unsigned behavior should 602023SN/A # explicitly specify '.uq'. 613761Sgblack@eecs.umich.edu 622501SN/A 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 633761Sgblack@eecs.umich.edu # The Rd from the previous window 643761Sgblack@eecs.umich.edu 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 653761Sgblack@eecs.umich.edu # The Rd from the next window 663761Sgblack@eecs.umich.edu 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 673835Sgblack@eecs.umich.edu # For microcoded twin load instructions, RdTwin appears in the "code" 683952Sgblack@eecs.umich.edu # for the instruction is replaced by RdLow or RdHigh by the format 693835Sgblack@eecs.umich.edu # before it's processed by the iop. 703761Sgblack@eecs.umich.edu # The low (even) register of a two register pair 713761Sgblack@eecs.umich.edu 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 723761Sgblack@eecs.umich.edu # The high (odd) register of a two register pair 733761Sgblack@eecs.umich.edu 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 743761Sgblack@eecs.umich.edu 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 753761Sgblack@eecs.umich.edu 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 763761Sgblack@eecs.umich.edu # A microcode register. Right now, this is the only one. 773761Sgblack@eecs.umich.edu 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 783761Sgblack@eecs.umich.edu # Because double and quad precision register numbers are decoded 793761Sgblack@eecs.umich.edu # differently, they get different operands. The single precision versions 803761Sgblack@eecs.umich.edu # have an s post pended to their name. 813279Sgblack@eecs.umich.edu 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 823279Sgblack@eecs.umich.edu 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 833279Sgblack@eecs.umich.edu # Each Frd_N refers to the Nth double precision register from Frd. 843279Sgblack@eecs.umich.edu # Note that this adds twice N to the register number. 853279Sgblack@eecs.umich.edu 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 863279Sgblack@eecs.umich.edu 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 873279Sgblack@eecs.umich.edu 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 883279Sgblack@eecs.umich.edu 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 893279Sgblack@eecs.umich.edu 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 903279Sgblack@eecs.umich.edu 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 913279Sgblack@eecs.umich.edu 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 923279Sgblack@eecs.umich.edu 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 933993Sgblack@eecs.umich.edu 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 943279Sgblack@eecs.umich.edu 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 953993Sgblack@eecs.umich.edu 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 963279Sgblack@eecs.umich.edu 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 972954Sgblack@eecs.umich.edu 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 982954Sgblack@eecs.umich.edu 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 993761Sgblack@eecs.umich.edu # Registers which are used explicitly in instructions 1002516SN/A 'R0': ('IntReg', 'udw', '0', None, 6), 1012561SN/A 'R1': ('IntReg', 'udw', '1', None, 7), 1022561SN/A 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 1032561SN/A 'R16': ('IntReg', 'udw', '16', None, 9), 1044098Ssaidi@eecs.umich.edu 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 1054098Ssaidi@eecs.umich.edu 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 1064098Ssaidi@eecs.umich.edu 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 1074098Ssaidi@eecs.umich.edu 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 1084098Ssaidi@eecs.umich.edu 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 1094098Ssaidi@eecs.umich.edu 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 1102646Ssaidi@eecs.umich.edu 1112469SN/A # Control registers 1123761Sgblack@eecs.umich.edu# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 1133761Sgblack@eecs.umich.edu# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 1143761Sgblack@eecs.umich.edu 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 1153761Sgblack@eecs.umich.edu 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 1162954Sgblack@eecs.umich.edu 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 1173587Sgblack@eecs.umich.edu 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 1183587Sgblack@eecs.umich.edu 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 1193587Sgblack@eecs.umich.edu 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 1203587Sgblack@eecs.umich.edu 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), 1213587Sgblack@eecs.umich.edu 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 1223587Sgblack@eecs.umich.edu 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 1233587Sgblack@eecs.umich.edu 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 1243587Sgblack@eecs.umich.edu 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 1253587Sgblack@eecs.umich.edu 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 1263587Sgblack@eecs.umich.edu 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 1272646Ssaidi@eecs.umich.edu 1283587Sgblack@eecs.umich.edu 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 1293587Sgblack@eecs.umich.edu 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 1303587Sgblack@eecs.umich.edu 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 1313587Sgblack@eecs.umich.edu 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 1323587Sgblack@eecs.umich.edu 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 1333587Sgblack@eecs.umich.edu 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 1343587Sgblack@eecs.umich.edu 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 1353587Sgblack@eecs.umich.edu 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 1363587Sgblack@eecs.umich.edu 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 1373793Sgblack@eecs.umich.edu 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 1383761Sgblack@eecs.umich.edu# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 1393761Sgblack@eecs.umich.edu# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 1403761Sgblack@eecs.umich.edu# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 1413761Sgblack@eecs.umich.edu# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 1423761Sgblack@eecs.umich.edu# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 1433761Sgblack@eecs.umich.edu 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 1443761Sgblack@eecs.umich.edu 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 1453761Sgblack@eecs.umich.edu 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 1463761Sgblack@eecs.umich.edu 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 1473761Sgblack@eecs.umich.edu 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 1483587Sgblack@eecs.umich.edu 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 1492646Ssaidi@eecs.umich.edu 1503587Sgblack@eecs.umich.edu 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 1513587Sgblack@eecs.umich.edu 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 1523587Sgblack@eecs.umich.edu 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 1533587Sgblack@eecs.umich.edu 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 1543587Sgblack@eecs.umich.edu 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 1553587Sgblack@eecs.umich.edu 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 1563600Sgblack@eecs.umich.edu 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 1572646Ssaidi@eecs.umich.edu 1583587Sgblack@eecs.umich.edu 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), 1593388Sgblack@eecs.umich.edu # Mem gets a large number so it's always last 1603388Sgblack@eecs.umich.edu 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 1612646Ssaidi@eecs.umich.edu 1622023SN/A}}; 163