operands.isa revision 3279
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 322023SN/A 'sb' : ('signed int', 8), 332023SN/A 'ub' : ('unsigned int', 8), 342023SN/A 'shw' : ('signed int', 16), 352023SN/A 'uhw' : ('unsigned int', 16), 362023SN/A 'sw' : ('signed int', 32), 372023SN/A 'uw' : ('unsigned int', 32), 382023SN/A 'sdw' : ('signed int', 64), 392023SN/A 'udw' : ('unsigned int', 64), 402023SN/A 'sf' : ('float', 32), 412023SN/A 'df' : ('float', 64), 422023SN/A 'qf' : ('float', 128) 432023SN/A}}; 442023SN/A 453279Sgblack@eecs.umich.eduoutput header {{ 463279Sgblack@eecs.umich.edu // A function to "decompress" double and quad floating point 473279Sgblack@eecs.umich.edu // register numbers stuffed into 5 bit fields. These have their 483279Sgblack@eecs.umich.edu // MSB put in the LSB position but are otherwise normal. 493279Sgblack@eecs.umich.edu static inline unsigned int dfpr(unsigned int regNum) 503279Sgblack@eecs.umich.edu { 513279Sgblack@eecs.umich.edu return regNum | ((regNum & 1) << 5); 523279Sgblack@eecs.umich.edu } 533279Sgblack@eecs.umich.edu}}; 543279Sgblack@eecs.umich.edu 552023SN/Adef operands {{ 562023SN/A # Int regs default to unsigned, but code should not count on this. 572023SN/A # For clarity, descriptions that depend on unsigned behavior should 582023SN/A # explicitly specify '.uq'. 592501SN/A 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 602501SN/A 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 612501SN/A 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 622501SN/A 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 632501SN/A 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 643279Sgblack@eecs.umich.edu 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 653279Sgblack@eecs.umich.edu 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 663279Sgblack@eecs.umich.edu # Each Frd_N refers to the Nth double precision register from Frd. 673279Sgblack@eecs.umich.edu # Note that this adds twice N to the register number. 683279Sgblack@eecs.umich.edu 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 693279Sgblack@eecs.umich.edu 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 703279Sgblack@eecs.umich.edu 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 713279Sgblack@eecs.umich.edu 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 723279Sgblack@eecs.umich.edu 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 733279Sgblack@eecs.umich.edu 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 743279Sgblack@eecs.umich.edu 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 753279Sgblack@eecs.umich.edu 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 763279Sgblack@eecs.umich.edu 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 773279Sgblack@eecs.umich.edu 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 783279Sgblack@eecs.umich.edu 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 793279Sgblack@eecs.umich.edu 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 802954Sgblack@eecs.umich.edu 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 812954Sgblack@eecs.umich.edu 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 822954Sgblack@eecs.umich.edu 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 832077SN/A #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 842077SN/A #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 852516SN/A 'R0': ('IntReg', 'udw', '0', None, 6), 862561SN/A 'R1': ('IntReg', 'udw', '1', None, 7), 872561SN/A 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 882561SN/A 'R16': ('IntReg', 'udw', '16', None, 9), 892646Ssaidi@eecs.umich.edu 902469SN/A # Control registers 912954Sgblack@eecs.umich.edu 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 922954Sgblack@eecs.umich.edu 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 932954Sgblack@eecs.umich.edu 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 942646Ssaidi@eecs.umich.edu 952954Sgblack@eecs.umich.edu 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 962954Sgblack@eecs.umich.edu 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 972954Sgblack@eecs.umich.edu 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 982954Sgblack@eecs.umich.edu 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 992954Sgblack@eecs.umich.edu 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), 1002646Ssaidi@eecs.umich.edu 1012954Sgblack@eecs.umich.edu 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 1022954Sgblack@eecs.umich.edu 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 1032954Sgblack@eecs.umich.edu 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 1042954Sgblack@eecs.umich.edu 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 1052954Sgblack@eecs.umich.edu 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 1062954Sgblack@eecs.umich.edu 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 1072954Sgblack@eecs.umich.edu 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 1082646Ssaidi@eecs.umich.edu 1092962Sgblack@eecs.umich.edu 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 1102962Sgblack@eecs.umich.edu 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56) 1112646Ssaidi@eecs.umich.edu 1122023SN/A}}; 113