operands.isa revision 2646
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 322023SN/A 'sb' : ('signed int', 8), 332023SN/A 'ub' : ('unsigned int', 8), 342023SN/A 'shw' : ('signed int', 16), 352023SN/A 'uhw' : ('unsigned int', 16), 362023SN/A 'sw' : ('signed int', 32), 372023SN/A 'uw' : ('unsigned int', 32), 382023SN/A 'sdw' : ('signed int', 64), 392023SN/A 'udw' : ('unsigned int', 64), 402023SN/A 'sf' : ('float', 32), 412023SN/A 'df' : ('float', 64), 422023SN/A 'qf' : ('float', 128) 432023SN/A}}; 442023SN/A 452023SN/Adef operands {{ 462023SN/A # Int regs default to unsigned, but code should not count on this. 472023SN/A # For clarity, descriptions that depend on unsigned behavior should 482023SN/A # explicitly specify '.uq'. 492501SN/A 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 502501SN/A 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 512501SN/A 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 522501SN/A 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 532501SN/A 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 542077SN/A #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 552077SN/A #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 562077SN/A #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 572501SN/A 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 582516SN/A 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), 592516SN/A 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), 602077SN/A #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 612077SN/A #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 622516SN/A 'R0': ('IntReg', 'udw', '0', None, 6), 632561SN/A 'R1': ('IntReg', 'udw', '1', None, 7), 642561SN/A 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 652561SN/A 'R16': ('IntReg', 'udw', '16', None, 9), 662646Ssaidi@eecs.umich.edu 672469SN/A # Control registers 682646Ssaidi@eecs.umich.edu 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12), 692646Ssaidi@eecs.umich.edu 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17), 702646Ssaidi@eecs.umich.edu 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), 712646Ssaidi@eecs.umich.edu 722646Ssaidi@eecs.umich.edu 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), 732646Ssaidi@eecs.umich.edu 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 28), 742646Ssaidi@eecs.umich.edu 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28), 752469SN/A 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 762646Ssaidi@eecs.umich.edu 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), 772646Ssaidi@eecs.umich.edu 782469SN/A 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15), 792469SN/A 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34), 802469SN/A 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35), 812646Ssaidi@eecs.umich.edu 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37), 822469SN/A 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36), 832469SN/A 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38), 842646Ssaidi@eecs.umich.edu 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 12), 852646Ssaidi@eecs.umich.edu 862646Ssaidi@eecs.umich.edu 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47) 872646Ssaidi@eecs.umich.edu 882023SN/A}}; 89