operands.isa revision 2632
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312023SN/Adef operand_types {{ 322023SN/A 'sb' : ('signed int', 8), 332023SN/A 'ub' : ('unsigned int', 8), 342023SN/A 'shw' : ('signed int', 16), 352023SN/A 'uhw' : ('unsigned int', 16), 362023SN/A 'sw' : ('signed int', 32), 372023SN/A 'uw' : ('unsigned int', 32), 382023SN/A 'sdw' : ('signed int', 64), 392023SN/A 'udw' : ('unsigned int', 64), 402023SN/A 'sf' : ('float', 32), 412023SN/A 'df' : ('float', 64), 422023SN/A 'qf' : ('float', 128) 432023SN/A}}; 442023SN/A 452023SN/Adef operands {{ 462023SN/A # Int regs default to unsigned, but code should not count on this. 472023SN/A # For clarity, descriptions that depend on unsigned behavior should 482023SN/A # explicitly specify '.uq'. 492501SN/A 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 502501SN/A 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 512501SN/A 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 522501SN/A 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 532501SN/A 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 542077SN/A #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 552077SN/A #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 562077SN/A #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 572501SN/A 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 582516SN/A 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), 592516SN/A 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), 602077SN/A #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 612077SN/A #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 622516SN/A 'R0': ('IntReg', 'udw', '0', None, 6), 632561SN/A 'R1': ('IntReg', 'udw', '1', None, 7), 642561SN/A 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 652561SN/A 'R16': ('IntReg', 'udw', '16', None, 9), 662469SN/A # Control registers 672469SN/A 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 682469SN/A 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), 692469SN/A 'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3), 702469SN/A 'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4), 712469SN/A 'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5), 722469SN/A 'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6), 732469SN/A 'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7), 742469SN/A 'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8), 752469SN/A 'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9), 762469SN/A 'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10), 772469SN/A 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11), 782469SN/A 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12), 792469SN/A 'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13), 802469SN/A 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14), 812469SN/A 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15), 822469SN/A #'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16), 832469SN/A 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17), 842469SN/A 'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18), 852469SN/A 'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19), 862469SN/A 'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20), 872469SN/A 'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21), 882469SN/A 'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22), 892469SN/A 'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23), 902469SN/A 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22), 912469SN/A 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23), 922469SN/A 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24), 932516SN/A 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25), 942469SN/A 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), 952469SN/A 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), 962469SN/A #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), 972469SN/A 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29), 982469SN/A 'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32), 992469SN/A 'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33), 1002469SN/A 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34), 1012469SN/A 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35), 1022469SN/A 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36), 1032469SN/A 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37), 1042469SN/A 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38), 1052469SN/A 'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39), 1062469SN/A 'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40), 1072469SN/A 'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41), 1082469SN/A 'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42), 1092469SN/A 'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43), 1102469SN/A 'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44), 1112469SN/A 'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45), 1122469SN/A 'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46), 1132469SN/A 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47), 1142469SN/A 'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48), 1152469SN/A 'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49), 1162469SN/A 'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50), 1172469SN/A 'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51), 1182469SN/A 'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52), 1192469SN/A 'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53), 1202469SN/A 'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54), 1212469SN/A 'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55), 1222469SN/A 'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56), 1232469SN/A 'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57), 1242469SN/A 'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58), 1252469SN/A 'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59), 1262469SN/A 'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60), 1272469SN/A 'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61), 1282469SN/A 'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62), 1292469SN/A 'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63), 1302469SN/A 'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64), 1312469SN/A 'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65), 1322469SN/A 'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66), 1332469SN/A 'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67), 1342469SN/A 'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68), 1352469SN/A 'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69), 1362469SN/A 'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70), 1372469SN/A 'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71), 1382469SN/A 'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72), 1392469SN/A 'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73), 1402469SN/A 'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74), 1412469SN/A 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75), 1422469SN/A 'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76), 1432469SN/A 'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77), 1442469SN/A 'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78) 1452023SN/A}}; 146