operands.isa revision 2501 
1def operand_types {{
2    'sb' : ('signed int', 8),
3    'ub' : ('unsigned int', 8),
4    'shw' : ('signed int', 16),
5    'uhw' : ('unsigned int', 16),
6    'sw' : ('signed int', 32),
7    'uw' : ('unsigned int', 32),
8    'sdw' : ('signed int', 64),
9    'udw' : ('unsigned int', 64),
10    'sf' : ('float', 32),
11    'df' : ('float', 64),
12    'qf' : ('float', 128)
13}};
14
15def operands {{
16    # Int regs default to unsigned, but code should not count on this.
17    # For clarity, descriptions that depend on unsigned behavior should
18    # explicitly specify '.uq'.
19    'Rd': 		('IntReg', 'udw', 'RD', 'IsInteger', 1),
20    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
21    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
22    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 4),
23    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 5),
24    #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
25    #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
26    #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
27    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
28    #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
29    #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
30    #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
31    'R0':  		('IntReg', 'udw', '0', None, 1),
32    'R16': 		('IntReg', 'udw', '16', None, 1),
33    # Control registers
34    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
35    'PstateAg':		('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
36    'PstateIe':		('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
37    'PstatePriv':	('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
38    'PstateAm':		('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
39    'PstatePef':	('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
40    'PstateRed':	('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
41    'PstateMm':		('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
42    'PstateTle':	('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
43    'PstateCle':	('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
44    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
45    'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 12),
46    'YValue':		('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
47    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
48    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
49    #'Tt':		('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
50    'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
51    'CcrIcc':		('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
52    'CcrIccC':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
53    'CcrIccV':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
54    'CcrIccZ':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
55    'CcrIccN':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
56    'CcrXcc':		('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
57    'CcrXccC':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
58    'CcrXccV':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
59    'CcrXccZ':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
60    'CcrXccN':		('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
61    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
62    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 27),
63    #'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
64    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
65    'TickCounter':	('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
66    'TickNpt':		('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
67    'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
68    'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
69    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
70    'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
71    'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
72    'WstateNormal':	('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
73    'WstateOther':	('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
74    'Ver':		('ControlReg', 'udw', 'MISCREG_VER', None, 41),
75    'VerMaxwin':	('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
76    'VerMaxtl':		('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
77    'VerMask':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
78    'VerImpl':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
79    'VerManuf':		('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
80    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
81    'FsrCexc':		('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
82    'FsrCexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
83    'FsrCexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
84    'FsrCexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
85    'FsrCexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
86    'FsrCexcNvc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
87    'FsrAexc':		('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
88    'FsrAexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
89    'FsrAexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
90    'FsrAexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
91    'FsrAexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
92    'FsrAexcNvc':	('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
93    'FsrFcc0':		('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
94    'FsrQne':		('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
95    'FsrFtt':		('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
96    'FsrVer':		('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
97    'FsrNs':		('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
98    'FsrTem':		('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
99    'FsrTemNxm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
100    'FsrTemDzm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
101    'FsrTemUfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
102    'FsrTemOfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
103    'FsrTemNvm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
104    'FsrRd':		('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
105    'FsrFcc1':		('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
106    'FsrFcc2':		('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
107    'FsrFcc3':		('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
108    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
109    'FprsDl':		('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
110    'FprsDu':		('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
111    'FprsFef':		('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
112}};
113