xref: /gem5/src/arch/sparc/isa/operands.isa

def operand_types {{
    'sb' : ('signed int', 8),
    'ub' : ('unsigned int', 8),
    'shw' : ('signed int', 16),
    'uhw' : ('unsigned int', 16),
    'sw' : ('signed int', 32),
    'uw' : ('unsigned int', 32),
    'sdw' : ('signed int', 64),
    'udw' : ('unsigned int', 64),
    'sf' : ('float', 32),
    'df' : ('float', 64),
    'qf' : ('float', 128)
}};

def operands {{
    # Int regs default to unsigned, but code should not count on this.
    # For clarity, descriptions that depend on unsigned behavior should
    # explicitly specify '.uq'.
    'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
    'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
    'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
    #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
    #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
    #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
    'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
    #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
    #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
    #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
    # The next two are hacks for non-full-system call-pal emulation
    #'R0':  ('IntReg', 'uq', '0', None, 1),
    #'R16': ('IntReg', 'uq', '16', None, 1)
}};