nop.isa revision 4992
14992Sgblack@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Gabe Black 282632Sstever@eecs.umich.edu// Steve Reinhardt 292632Sstever@eecs.umich.edu 302022SN/A//////////////////////////////////////////////////////////////////// 312022SN/A// 322516SN/A// Nop instruction 332022SN/A// 342022SN/A 352636Sstever@eecs.umich.edu// Per-cpu-model nop execute method. 362636Sstever@eecs.umich.edudef template NopExec {{ 372636Sstever@eecs.umich.edu 382636Sstever@eecs.umich.edu Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 392636Sstever@eecs.umich.edu { 402636Sstever@eecs.umich.edu // Nothing to see here, move along 412636Sstever@eecs.umich.edu return NoFault; 422636Sstever@eecs.umich.edu } 432636Sstever@eecs.umich.edu}}; 442636Sstever@eecs.umich.edu 452022SN/Aoutput header {{ 462022SN/A /** 472516SN/A * Nop class. 482022SN/A */ 492516SN/A class Nop : public SparcStaticInst 502022SN/A { 512516SN/A public: 522224SN/A // Constructor 532516SN/A Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 542224SN/A SparcStaticInst(mnem, _machInst, __opClass) 552224SN/A { 564992Sgblack@eecs.umich.edu flags[IsNop] = true; 572224SN/A } 582022SN/A 592516SN/A // All Nop instructions do the same thing, so this can be 602636Sstever@eecs.umich.edu // defined here. Nops can be defined directly, so there 612636Sstever@eecs.umich.edu // needs to be a default implementation. Interpolate via 622636Sstever@eecs.umich.edu // template so i gets expanded to a set of 632636Sstever@eecs.umich.edu // cpu-model-specific functions. 642636Sstever@eecs.umich.edu %(NopExec)s 652516SN/A 662224SN/A std::string generateDisassembly(Addr pc, 672224SN/A const SymbolTable *symtab) const; 682022SN/A }; 692022SN/A}}; 702022SN/A 712022SN/Aoutput decoder {{ 722516SN/A std::string Nop::generateDisassembly(Addr pc, 732224SN/A const SymbolTable *symtab) const 742022SN/A { 752516SN/A std::stringstream response; 762516SN/A printMnemonic(response, mnemonic); 772516SN/A return response.str(); 782022SN/A } 792022SN/A}}; 802022SN/A 812516SN/Adef template NopExecute {{ 822224SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 832224SN/A Trace::InstRecord *traceData) const 842022SN/A { 852224SN/A //Nothing to see here, move along 862224SN/A return NoFault; 872022SN/A } 882022SN/A}}; 892022SN/A 902022SN/A// Primary format for integer operate instructions: 912516SN/Adef format Nop(code, *opt_flags) {{ 923792Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'Nop', code, opt_flags) 932022SN/A header_output = BasicDeclare.subst(iop) 942022SN/A decoder_output = BasicConstructor.subst(iop) 952469SN/A decode_block = BasicDecode.subst(iop) 962516SN/A exec_output = NopExecute.subst(iop) 972022SN/A}}; 98