util.isa revision 5893:41b18fe25a0e
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic); 82 if(store) 83 { 84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "["); 88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 { 90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]"); 95 if(load) 96 { 97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic); 112 if(save) 113 { 114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "["); 118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 { 120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 } 123 if(imm >= 0) 124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm); 127 if(load) 128 { 129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136 137//This template provides the execute functions for a load 138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(fp_enable_check)s; 145 %(op_decl)s; 146 %(op_rd)s; 147 %(ea_code)s; 148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 149 %(fault_check)s; 150 if(fault == NoFault) 151 { 152 %(EA_trunc)s 153 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 154 } 155 if(fault == NoFault) 156 { 157 %(code)s; 158 } 159 if(fault == NoFault) 160 { 161 //Write the resulting state to the execution context 162 %(op_wb)s; 163 } 164 165 return fault; 166 } 167}}; 168 169def template LoadInitiateAcc {{ 170 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 171 Trace::InstRecord * traceData) const 172 { 173 Fault fault = NoFault; 174 Addr EA; 175 %(fp_enable_check)s; 176 %(op_decl)s; 177 %(op_rd)s; 178 %(ea_code)s; 179 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 180 %(fault_check)s; 181 if(fault == NoFault) 182 { 183 %(EA_trunc)s 184 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 185 } 186 return fault; 187 } 188}}; 189 190def template LoadCompleteAcc {{ 191 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 192 Trace::InstRecord * traceData) const 193 { 194 Fault fault = NoFault; 195 %(op_decl)s; 196 %(op_rd)s; 197 Mem = pkt->get<typeof(Mem)>(); 198 %(code)s; 199 if(fault == NoFault) 200 { 201 %(op_wb)s; 202 } 203 return fault; 204 } 205}}; 206 207//This template provides the execute functions for a store 208def template StoreExecute {{ 209 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 210 Trace::InstRecord *traceData) const 211 { 212 Fault fault = NoFault; 213 //This is to support the conditional store in cas instructions. 214 //It should be optomized out in all the others 215 bool storeCond = true; 216 Addr EA; 217 %(fp_enable_check)s; 218 %(op_decl)s; 219 %(op_rd)s; 220 %(ea_code)s; 221 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 222 %(fault_check)s; 223 if(fault == NoFault) 224 { 225 %(code)s; 226 } 227 if(storeCond && fault == NoFault) 228 { 229 %(EA_trunc)s 230 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 231 EA, %(asi_val)s, 0); 232 } 233 if(fault == NoFault) 234 { 235 //Write the resulting state to the execution context 236 %(op_wb)s; 237 } 238 239 return fault; 240 } 241}}; 242 243def template StoreInitiateAcc {{ 244 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 245 Trace::InstRecord * traceData) const 246 { 247 Fault fault = NoFault; 248 bool storeCond = true; 249 Addr EA; 250 %(fp_enable_check)s; 251 %(op_decl)s; 252 253 %(op_rd)s; 254 %(ea_code)s; 255 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 256 %(fault_check)s; 257 if(fault == NoFault) 258 { 259 %(code)s; 260 } 261 if(storeCond && fault == NoFault) 262 { 263 %(EA_trunc)s 264 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 265 EA, %(asi_val)s, 0); 266 } 267 return fault; 268 } 269}}; 270 271def template StoreCompleteAcc {{ 272 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 273 Trace::InstRecord * traceData) const 274 { 275 Fault fault = NoFault; 276 %(op_decl)s; 277 278 %(op_rd)s; 279 %(postacc_code)s; 280 if (fault == NoFault) 281 { 282 %(op_wb)s; 283 } 284 return NoFault; 285 } 286}}; 287 288//This delcares the initiateAcc function in memory operations 289def template InitiateAccDeclare {{ 290 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 291}}; 292 293//This declares the completeAcc function in memory operations 294def template CompleteAccDeclare {{ 295 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 296}}; 297 298//Here are some code snippets which check for various fault conditions 299let {{ 300 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 301 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 302 303 # The LSB can be zero, since it's really the MSB in doubles and quads 304 # and we're dealing with doubles 305 BlockAlignmentFaultCheck = ''' 306 if(RD & 0xe) 307 fault = new IllegalInstruction; 308 else if(EA & 0x3f) 309 fault = new MemAddressNotAligned; 310 ''' 311 TwinAlignmentFaultCheck = ''' 312 if(RD & 0x1) 313 fault = new IllegalInstruction; 314 else if(EA & 0xf) 315 fault = new MemAddressNotAligned; 316 ''' 317 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 318 # are split into ones that are available in priv and hpriv, and 319 # those that are only available in hpriv 320 AlternateASIPrivFaultCheck = ''' 321 if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && 322 !AsiIsUnPriv((ASI)EXT_ASI)) || 323 (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))) 324 fault = new PrivilegedAction; 325 else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 326 fault = new PrivilegedAction; 327 ''' 328 329 TruncateEA = ''' 330#if !FULL_SYSTEM 331 EA = Pstate<3:> ? EA<31:0> : EA; 332#endif 333 ''' 334}}; 335 336//A simple function to generate the name of the macro op of a certain 337//instruction at a certain micropc 338let {{ 339 def makeMicroName(name, microPc): 340 return name + "::" + name + "_" + str(microPc) 341}}; 342 343//This function properly generates the execute functions for one of the 344//templates above. This is needed because in one case, ea computation, 345//fault checks and the actual code all occur in the same function, 346//and in the other they're distributed across two. Also note that for 347//execute functions, the name of the base class doesn't matter. 348let {{ 349 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 350 microParam["asi_val"] = asi; 351 iop = InstObjParams(name, Name, '', microParam, opt_flags) 352 (execf, initf, compf) = execute 353 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 354 355 356 def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute, 357 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 358 executeCode = '' 359 for (eaCode, name, Name) in ( 360 (eaRegCode, nameReg, NameReg), 361 (eaImmCode, nameImm, NameImm)): 362 microParams = {"code": code, "postacc_code" : postacc_code, 363 "ea_code": eaCode, "fault_check": faultCode, 364 "EA_trunc" : TruncateEA} 365 executeCode += doSplitExecute(execute, name, Name, 366 asi, opt_flags, microParams) 367 return executeCode 368}}; 369