util.isa revision 3835
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic); 82 if(store) 83 { 84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "["); 88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 { 90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]"); 95 if(load) 96 { 97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic); 112 if(save) 113 { 114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "["); 118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 { 120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 } 123 if(imm >= 0) 124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm); 127 if(load) 128 { 129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136 137//This template provides the execute functions for a load 138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(op_decl)s; 145 %(op_rd)s; 146 %(ea_code)s; 147 DPRINTF(Sparc, "The address is 0x%x\n", EA); 148 %(fault_check)s; 149 if(fault == NoFault) 150 { 151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 152 } 153 if(fault == NoFault) 154 { 155 %(code)s; 156 } 157 if(fault == NoFault) 158 { 159 //Write the resulting state to the execution context 160 %(op_wb)s; 161 } 162 163 return fault; 164 } 165 166 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 167 Trace::InstRecord * traceData) const 168 { 169 Fault fault = NoFault; 170 Addr EA; 171 uint%(mem_acc_size)s_t Mem; 172 %(ea_decl)s; 173 %(ea_rd)s; 174 %(ea_code)s; 175 %(fault_check)s; 176 if(fault == NoFault) 177 { 178 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 179 } 180 return fault; 181 } 182 183 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 184 Trace::InstRecord * traceData) const 185 { 186 Fault fault = NoFault; 187 %(code_decl)s; 188 %(code_rd)s; 189 Mem = pkt->get<typeof(Mem)>(); 190 %(code)s; 191 if(fault == NoFault) 192 { 193 %(code_wb)s; 194 } 195 return fault; 196 } 197}}; 198 199//This template provides the execute functions for a store 200def template StoreExecute {{ 201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 202 Trace::InstRecord *traceData) const 203 { 204 Fault fault = NoFault; 205 //This is to support the conditional store in cas instructions. 206 //It should be optomized out in all the others 207 bool storeCond = true; 208 Addr EA; 209 %(op_decl)s; 210 %(op_rd)s; 211 %(ea_code)s; 212 DPRINTF(Sparc, "The address is 0x%x\n", EA); 213 %(fault_check)s; 214 if(fault == NoFault) 215 { 216 %(code)s; 217 } 218 if(storeCond && fault == NoFault) 219 { 220 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 221 EA, %(asi_val)s, 0); 222 } 223 if(fault == NoFault) 224 { 225 //Write the resulting state to the execution context 226 %(op_wb)s; 227 } 228 229 return fault; 230 } 231 232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 233 Trace::InstRecord * traceData) const 234 { 235 Fault fault = NoFault; 236 bool storeCond = true; 237 Addr EA; 238 %(op_decl)s; 239 %(op_rd)s; 240 %(ea_code)s; 241 DPRINTF(Sparc, "The address is 0x%x\n", EA); 242 %(fault_check)s; 243 if(fault == NoFault) 244 { 245 %(code)s; 246 } 247 if(storeCond && fault == NoFault) 248 { 249 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 250 EA, %(asi_val)s, 0); 251 } 252 if(fault == NoFault) 253 { 254 //Write the resulting state to the execution context 255 %(op_wb)s; 256 } 257 return fault; 258 } 259 260 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 261 Trace::InstRecord * traceData) const 262 { 263 return NoFault; 264 } 265}}; 266 267//This delcares the initiateAcc function in memory operations 268def template InitiateAccDeclare {{ 269 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 270}}; 271 272//This declares the completeAcc function in memory operations 273def template CompleteAccDeclare {{ 274 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 275}}; 276 277//Here are some code snippets which check for various fault conditions 278let {{ 279 # The LSB can be zero, since it's really the MSB in doubles and quads 280 # and we're dealing with doubles 281 BlockAlignmentFaultCheck = ''' 282 if(RD & 0xe) 283 fault = new IllegalInstruction; 284 else if(EA & 0x3f) 285 fault = new MemAddressNotAligned; 286 ''' 287 TwinAlignmentFaultCheck = ''' 288 if(RD & 0xe) 289 fault = new IllegalInstruction; 290 else if(EA & 0x1f) 291 fault = new MemAddressNotAligned; 292 ''' 293 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 294 # are split into ones that are available in priv and hpriv, and 295 # those that are only available in hpriv 296 AlternateASIPrivFaultCheck = ''' 297 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || 298 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) 299 fault = new PrivilegedAction; 300 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 301 fault = new PrivilegedAction; 302 ''' 303 304}}; 305 306//A simple function to generate the name of the macro op of a certain 307//instruction at a certain micropc 308let {{ 309 def makeMicroName(name, microPc): 310 return name + "::" + name + "_" + str(microPc) 311}}; 312 313//This function properly generates the execute functions for one of the 314//templates above. This is needed because in one case, ea computation, 315//fault checks and the actual code all occur in the same function, 316//and in the other they're distributed across two. Also note that for 317//execute functions, the name of the base class doesn't matter. 318let {{ 319 def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam): 320 microParam["asi_val"] = asi; 321 codeParam = microParam.copy() 322 codeParam["ea_code"] = '' 323 codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) 324 eaIop = InstObjParams(name, Name, '', microParam["ea_code"], 325 opt_flags, microParam) 326 iop = InstObjParams(name, Name, '', code, opt_flags, microParam) 327 (iop.ea_decl, 328 iop.ea_rd, 329 iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) 330 (iop.code_decl, 331 iop.code_rd, 332 iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb) 333 return execute.subst(iop) 334 335 336 def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, 337 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 338 executeCode = '' 339 for (eaCode, name, Name) in ( 340 (eaRegCode, nameReg, NameReg), 341 (eaImmCode, nameImm, NameImm)): 342 microParams = {"ea_code" : eaCode, "fault_check": faultCode} 343 executeCode += doSplitExecute(code, execute, name, Name, 344 asi, opt_flags, microParams) 345 return executeCode 346}}; 347