blockmem.isa revision 3863
13388Sgblack@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 23388Sgblack@eecs.umich.edu// All rights reserved. 33388Sgblack@eecs.umich.edu// 43388Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 53388Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 63388Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 73388Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 83388Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 93388Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 103388Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 113388Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 123388Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 133388Sgblack@eecs.umich.edu// this software without specific prior written permission. 143388Sgblack@eecs.umich.edu// 153388Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163388Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173388Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183388Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193388Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203388Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213388Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223388Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233388Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243388Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253388Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263388Sgblack@eecs.umich.edu// 273388Sgblack@eecs.umich.edu// Authors: Ali Saidi 283388Sgblack@eecs.umich.edu// Gabe Black 293388Sgblack@eecs.umich.edu 303270SN/A//////////////////////////////////////////////////////////////////// 313270SN/A// 323270SN/A// Block Memory instructions 333270SN/A// 343270SN/A 353270SN/Aoutput header {{ 363270SN/A 373270SN/A class BlockMem : public SparcMacroInst 383270SN/A { 393270SN/A protected: 403270SN/A 413270SN/A // Constructor 423270SN/A // We make the assumption that all block memory operations 433270SN/A // Will take 8 instructions to execute 443388Sgblack@eecs.umich.edu BlockMem(const char *mnem, ExtMachInst _machInst) : 453388Sgblack@eecs.umich.edu SparcMacroInst(mnem, _machInst, No_OpClass, 8) 463270SN/A {} 473270SN/A }; 483270SN/A 493270SN/A class BlockMemImm : public BlockMem 503270SN/A { 513270SN/A protected: 523270SN/A 533270SN/A // Constructor 543388Sgblack@eecs.umich.edu BlockMemImm(const char *mnem, ExtMachInst _machInst) : 553388Sgblack@eecs.umich.edu BlockMem(mnem, _machInst) 563270SN/A {} 573270SN/A }; 583270SN/A 593440Sgblack@eecs.umich.edu class BlockMemMicro : public SparcMicroInst 603270SN/A { 613270SN/A protected: 623270SN/A 633270SN/A // Constructor 643270SN/A BlockMemMicro(const char *mnem, ExtMachInst _machInst, 653270SN/A OpClass __opClass, int8_t _offset) : 663440Sgblack@eecs.umich.edu SparcMicroInst(mnem, _machInst, __opClass), 673270SN/A offset(_offset) 683270SN/A {} 693270SN/A 703270SN/A std::string generateDisassembly(Addr pc, 713270SN/A const SymbolTable *symtab) const; 723270SN/A 733270SN/A const int8_t offset; 743270SN/A }; 753270SN/A 763270SN/A class BlockMemImmMicro : public BlockMemMicro 773270SN/A { 783270SN/A protected: 793270SN/A 803270SN/A // Constructor 813270SN/A BlockMemImmMicro(const char *mnem, ExtMachInst _machInst, 823270SN/A OpClass __opClass, int8_t _offset) : 833270SN/A BlockMemMicro(mnem, _machInst, __opClass, _offset), 843270SN/A imm(sext<13>(SIMM13)) 853270SN/A {} 863270SN/A 873270SN/A std::string generateDisassembly(Addr pc, 883270SN/A const SymbolTable *symtab) const; 893270SN/A 903270SN/A const int32_t imm; 913270SN/A }; 923270SN/A}}; 933270SN/A 943835Sgblack@eecs.umich.eduoutput header {{ 953835Sgblack@eecs.umich.edu 963835Sgblack@eecs.umich.edu class TwinMem : public SparcMacroInst 973835Sgblack@eecs.umich.edu { 983835Sgblack@eecs.umich.edu protected: 993835Sgblack@eecs.umich.edu 1003835Sgblack@eecs.umich.edu // Constructor 1013835Sgblack@eecs.umich.edu // We make the assumption that all block memory operations 1023835Sgblack@eecs.umich.edu // Will take 8 instructions to execute 1033835Sgblack@eecs.umich.edu TwinMem(const char *mnem, ExtMachInst _machInst) : 1043863Ssaidi@eecs.umich.edu SparcMacroInst(mnem, _machInst, No_OpClass, 2) 1053835Sgblack@eecs.umich.edu {} 1063835Sgblack@eecs.umich.edu }; 1073835Sgblack@eecs.umich.edu 1083835Sgblack@eecs.umich.edu class TwinMemImm : public BlockMem 1093835Sgblack@eecs.umich.edu { 1103835Sgblack@eecs.umich.edu protected: 1113835Sgblack@eecs.umich.edu 1123835Sgblack@eecs.umich.edu // Constructor 1133835Sgblack@eecs.umich.edu TwinMemImm(const char *mnem, ExtMachInst _machInst) : 1143835Sgblack@eecs.umich.edu BlockMem(mnem, _machInst) 1153835Sgblack@eecs.umich.edu {} 1163835Sgblack@eecs.umich.edu }; 1173835Sgblack@eecs.umich.edu 1183835Sgblack@eecs.umich.edu class TwinMemMicro : public SparcMicroInst 1193835Sgblack@eecs.umich.edu { 1203835Sgblack@eecs.umich.edu protected: 1213835Sgblack@eecs.umich.edu 1223835Sgblack@eecs.umich.edu // Constructor 1233835Sgblack@eecs.umich.edu TwinMemMicro(const char *mnem, ExtMachInst _machInst, 1243835Sgblack@eecs.umich.edu OpClass __opClass, int8_t _offset) : 1253835Sgblack@eecs.umich.edu SparcMicroInst(mnem, _machInst, __opClass), 1263835Sgblack@eecs.umich.edu offset(_offset) 1273835Sgblack@eecs.umich.edu {} 1283835Sgblack@eecs.umich.edu 1293835Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, 1303835Sgblack@eecs.umich.edu const SymbolTable *symtab) const; 1313835Sgblack@eecs.umich.edu 1323835Sgblack@eecs.umich.edu const int8_t offset; 1333835Sgblack@eecs.umich.edu }; 1343835Sgblack@eecs.umich.edu 1353835Sgblack@eecs.umich.edu class TwinMemImmMicro : public BlockMemMicro 1363835Sgblack@eecs.umich.edu { 1373835Sgblack@eecs.umich.edu protected: 1383835Sgblack@eecs.umich.edu 1393835Sgblack@eecs.umich.edu // Constructor 1403835Sgblack@eecs.umich.edu TwinMemImmMicro(const char *mnem, ExtMachInst _machInst, 1413835Sgblack@eecs.umich.edu OpClass __opClass, int8_t _offset) : 1423835Sgblack@eecs.umich.edu BlockMemMicro(mnem, _machInst, __opClass, _offset), 1433835Sgblack@eecs.umich.edu imm(sext<13>(SIMM13)) 1443835Sgblack@eecs.umich.edu {} 1453835Sgblack@eecs.umich.edu 1463835Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, 1473835Sgblack@eecs.umich.edu const SymbolTable *symtab) const; 1483835Sgblack@eecs.umich.edu 1493835Sgblack@eecs.umich.edu const int32_t imm; 1503835Sgblack@eecs.umich.edu }; 1513835Sgblack@eecs.umich.edu}}; 1523835Sgblack@eecs.umich.edu 1533270SN/Aoutput decoder {{ 1543280SN/A std::string BlockMemMicro::generateDisassembly(Addr pc, 1553270SN/A const SymbolTable *symtab) const 1563270SN/A { 1573270SN/A std::stringstream response; 1583270SN/A bool load = flags[IsLoad]; 1593270SN/A bool save = flags[IsStore]; 1603270SN/A 1613270SN/A printMnemonic(response, mnemonic); 1623270SN/A if(save) 1633270SN/A { 1643270SN/A printReg(response, _srcRegIdx[0]); 1653270SN/A ccprintf(response, ", "); 1663270SN/A } 1673270SN/A ccprintf(response, "[ "); 1683270SN/A printReg(response, _srcRegIdx[!save ? 0 : 1]); 1693270SN/A ccprintf(response, " + "); 1703270SN/A printReg(response, _srcRegIdx[!save ? 1 : 2]); 1713270SN/A ccprintf(response, " ]"); 1723270SN/A if(load) 1733270SN/A { 1743270SN/A ccprintf(response, ", "); 1753270SN/A printReg(response, _destRegIdx[0]); 1763270SN/A } 1773270SN/A 1783270SN/A return response.str(); 1793270SN/A } 1803270SN/A 1813280SN/A std::string BlockMemImmMicro::generateDisassembly(Addr pc, 1823270SN/A const SymbolTable *symtab) const 1833270SN/A { 1843270SN/A std::stringstream response; 1853270SN/A bool load = flags[IsLoad]; 1863270SN/A bool save = flags[IsStore]; 1873270SN/A 1883270SN/A printMnemonic(response, mnemonic); 1893270SN/A if(save) 1903270SN/A { 1913379SN/A printReg(response, _srcRegIdx[1]); 1923270SN/A ccprintf(response, ", "); 1933270SN/A } 1943270SN/A ccprintf(response, "[ "); 1953379SN/A printReg(response, _srcRegIdx[0]); 1963270SN/A if(imm >= 0) 1973270SN/A ccprintf(response, " + 0x%x ]", imm); 1983270SN/A else 1993270SN/A ccprintf(response, " + -0x%x ]", -imm); 2003270SN/A if(load) 2013270SN/A { 2023270SN/A ccprintf(response, ", "); 2033270SN/A printReg(response, _destRegIdx[0]); 2043270SN/A } 2053270SN/A 2063270SN/A return response.str(); 2073270SN/A } 2083270SN/A 2093270SN/A}}; 2103270SN/A 2113852Sgblack@eecs.umich.eduoutput decoder {{ 2123852Sgblack@eecs.umich.edu std::string TwinMemMicro::generateDisassembly(Addr pc, 2133852Sgblack@eecs.umich.edu const SymbolTable *symtab) const 2143852Sgblack@eecs.umich.edu { 2153852Sgblack@eecs.umich.edu std::stringstream response; 2163852Sgblack@eecs.umich.edu bool load = flags[IsLoad]; 2173852Sgblack@eecs.umich.edu bool save = flags[IsStore]; 2183852Sgblack@eecs.umich.edu 2193852Sgblack@eecs.umich.edu printMnemonic(response, mnemonic); 2203852Sgblack@eecs.umich.edu if(save) 2213852Sgblack@eecs.umich.edu { 2223852Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[0]); 2233852Sgblack@eecs.umich.edu ccprintf(response, ", "); 2243852Sgblack@eecs.umich.edu } 2253852Sgblack@eecs.umich.edu ccprintf(response, "[ "); 2263852Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[!save ? 0 : 1]); 2273852Sgblack@eecs.umich.edu ccprintf(response, " + "); 2283852Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[!save ? 1 : 2]); 2293852Sgblack@eecs.umich.edu ccprintf(response, " ]"); 2303852Sgblack@eecs.umich.edu if(load) 2313852Sgblack@eecs.umich.edu { 2323852Sgblack@eecs.umich.edu ccprintf(response, ", "); 2333852Sgblack@eecs.umich.edu printReg(response, _destRegIdx[0]); 2343852Sgblack@eecs.umich.edu } 2353852Sgblack@eecs.umich.edu 2363852Sgblack@eecs.umich.edu return response.str(); 2373852Sgblack@eecs.umich.edu } 2383852Sgblack@eecs.umich.edu 2393852Sgblack@eecs.umich.edu std::string TwinMemImmMicro::generateDisassembly(Addr pc, 2403852Sgblack@eecs.umich.edu const SymbolTable *symtab) const 2413852Sgblack@eecs.umich.edu { 2423852Sgblack@eecs.umich.edu std::stringstream response; 2433852Sgblack@eecs.umich.edu bool load = flags[IsLoad]; 2443852Sgblack@eecs.umich.edu bool save = flags[IsStore]; 2453852Sgblack@eecs.umich.edu 2463852Sgblack@eecs.umich.edu printMnemonic(response, mnemonic); 2473852Sgblack@eecs.umich.edu if(save) 2483852Sgblack@eecs.umich.edu { 2493852Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[1]); 2503852Sgblack@eecs.umich.edu ccprintf(response, ", "); 2513852Sgblack@eecs.umich.edu } 2523852Sgblack@eecs.umich.edu ccprintf(response, "[ "); 2533852Sgblack@eecs.umich.edu printReg(response, _srcRegIdx[0]); 2543852Sgblack@eecs.umich.edu if(imm >= 0) 2553852Sgblack@eecs.umich.edu ccprintf(response, " + 0x%x ]", imm); 2563852Sgblack@eecs.umich.edu else 2573852Sgblack@eecs.umich.edu ccprintf(response, " + -0x%x ]", -imm); 2583852Sgblack@eecs.umich.edu if(load) 2593852Sgblack@eecs.umich.edu { 2603852Sgblack@eecs.umich.edu ccprintf(response, ", "); 2613852Sgblack@eecs.umich.edu printReg(response, _destRegIdx[0]); 2623852Sgblack@eecs.umich.edu } 2633852Sgblack@eecs.umich.edu 2643852Sgblack@eecs.umich.edu return response.str(); 2653852Sgblack@eecs.umich.edu } 2663852Sgblack@eecs.umich.edu 2673852Sgblack@eecs.umich.edu}}; 2683852Sgblack@eecs.umich.edu 2693270SN/Adef template BlockMemDeclare {{ 2703270SN/A /** 2713270SN/A * Static instruction class for a block memory operation 2723270SN/A */ 2733270SN/A class %(class_name)s : public %(base_class)s 2743270SN/A { 2753270SN/A public: 2763270SN/A //Constructor 2773280SN/A %(class_name)s(ExtMachInst machInst); 2783270SN/A 2793274SN/A protected: 2803270SN/A class %(class_name)s_0 : public %(base_class)sMicro 2813270SN/A { 2823274SN/A public: 2833270SN/A //Constructor 2843280SN/A %(class_name)s_0(ExtMachInst machInst); 2853270SN/A %(BasicExecDeclare)s 2863391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 2873391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 2883270SN/A }; 2893270SN/A 2903270SN/A class %(class_name)s_1 : public %(base_class)sMicro 2913270SN/A { 2923274SN/A public: 2933270SN/A //Constructor 2943280SN/A %(class_name)s_1(ExtMachInst machInst); 2953270SN/A %(BasicExecDeclare)s 2963391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 2973391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 2983270SN/A }; 2993270SN/A 3003270SN/A class %(class_name)s_2 : public %(base_class)sMicro 3013270SN/A { 3023274SN/A public: 3033270SN/A //Constructor 3043280SN/A %(class_name)s_2(ExtMachInst machInst); 3053270SN/A %(BasicExecDeclare)s 3063391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3073391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3083270SN/A }; 3093270SN/A 3103270SN/A class %(class_name)s_3 : public %(base_class)sMicro 3113270SN/A { 3123274SN/A public: 3133270SN/A //Constructor 3143280SN/A %(class_name)s_3(ExtMachInst machInst); 3153270SN/A %(BasicExecDeclare)s 3163391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3173391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3183270SN/A }; 3193270SN/A 3203270SN/A class %(class_name)s_4 : public %(base_class)sMicro 3213270SN/A { 3223274SN/A public: 3233270SN/A //Constructor 3243280SN/A %(class_name)s_4(ExtMachInst machInst); 3253270SN/A %(BasicExecDeclare)s 3263391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3273391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3283270SN/A }; 3293270SN/A 3303270SN/A class %(class_name)s_5 : public %(base_class)sMicro 3313270SN/A { 3323274SN/A public: 3333270SN/A //Constructor 3343280SN/A %(class_name)s_5(ExtMachInst machInst); 3353270SN/A %(BasicExecDeclare)s 3363391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3373391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3383270SN/A }; 3393270SN/A 3403270SN/A class %(class_name)s_6 : public %(base_class)sMicro 3413270SN/A { 3423274SN/A public: 3433270SN/A //Constructor 3443280SN/A %(class_name)s_6(ExtMachInst machInst); 3453270SN/A %(BasicExecDeclare)s 3463391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3473391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3483270SN/A }; 3493270SN/A 3503270SN/A class %(class_name)s_7 : public %(base_class)sMicro 3513270SN/A { 3523274SN/A public: 3533270SN/A //Constructor 3543280SN/A %(class_name)s_7(ExtMachInst machInst); 3553270SN/A %(BasicExecDeclare)s 3563391Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3573391Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3583270SN/A }; 3593270SN/A }; 3603270SN/A}}; 3613270SN/A 3623835Sgblack@eecs.umich.edudef template TwinMemDeclare {{ 3633835Sgblack@eecs.umich.edu /** 3643835Sgblack@eecs.umich.edu * Static instruction class for a block memory operation 3653835Sgblack@eecs.umich.edu */ 3663835Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3673835Sgblack@eecs.umich.edu { 3683835Sgblack@eecs.umich.edu public: 3693835Sgblack@eecs.umich.edu //Constructor 3703835Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst); 3713835Sgblack@eecs.umich.edu 3723835Sgblack@eecs.umich.edu protected: 3733835Sgblack@eecs.umich.edu class %(class_name)s_0 : public %(base_class)sMicro 3743835Sgblack@eecs.umich.edu { 3753835Sgblack@eecs.umich.edu public: 3763835Sgblack@eecs.umich.edu //Constructor 3773835Sgblack@eecs.umich.edu %(class_name)s_0(ExtMachInst machInst); 3783835Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3793835Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3803835Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3813835Sgblack@eecs.umich.edu }; 3823835Sgblack@eecs.umich.edu 3833835Sgblack@eecs.umich.edu class %(class_name)s_1 : public %(base_class)sMicro 3843835Sgblack@eecs.umich.edu { 3853835Sgblack@eecs.umich.edu public: 3863835Sgblack@eecs.umich.edu //Constructor 3873835Sgblack@eecs.umich.edu %(class_name)s_1(ExtMachInst machInst); 3883835Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3893835Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3903835Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3913835Sgblack@eecs.umich.edu }; 3923835Sgblack@eecs.umich.edu }; 3933835Sgblack@eecs.umich.edu}}; 3943835Sgblack@eecs.umich.edu 3953270SN/A// Basic instruction class constructor template. 3963270SN/Adef template BlockMemConstructor {{ 3973280SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 3983388Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst) 3993270SN/A { 4003270SN/A %(constructor)s; 4013274SN/A microOps[0] = new %(class_name)s_0(machInst); 4023274SN/A microOps[1] = new %(class_name)s_1(machInst); 4033274SN/A microOps[2] = new %(class_name)s_2(machInst); 4043274SN/A microOps[3] = new %(class_name)s_3(machInst); 4053274SN/A microOps[4] = new %(class_name)s_4(machInst); 4063274SN/A microOps[5] = new %(class_name)s_5(machInst); 4073274SN/A microOps[6] = new %(class_name)s_6(machInst); 4083274SN/A microOps[7] = new %(class_name)s_7(machInst); 4093270SN/A } 4103270SN/A}}; 4113270SN/A 4123835Sgblack@eecs.umich.edu// Basic instruction class constructor template. 4133835Sgblack@eecs.umich.edudef template TwinMemConstructor {{ 4143835Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 4153835Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst) 4163835Sgblack@eecs.umich.edu { 4173835Sgblack@eecs.umich.edu %(constructor)s; 4183835Sgblack@eecs.umich.edu microOps[0] = new %(class_name)s_0(machInst); 4193835Sgblack@eecs.umich.edu microOps[1] = new %(class_name)s_1(machInst); 4203835Sgblack@eecs.umich.edu } 4213835Sgblack@eecs.umich.edu}}; 4223835Sgblack@eecs.umich.edu 4233280SN/Adef template BlockMemMicroConstructor {{ 4243280SN/A inline %(class_name)s:: 4253280SN/A %(class_name)s_%(micro_pc)s:: 4263280SN/A %(class_name)s_%(micro_pc)s(ExtMachInst machInst) : 4273280SN/A %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", 4283280SN/A machInst, %(op_class)s, %(micro_pc)s * 8) 4293280SN/A { 4303280SN/A %(constructor)s; 4313280SN/A %(set_flags)s; 4323280SN/A } 4333280SN/A}}; 4343280SN/A 4353270SN/Alet {{ 4363270SN/A 4373810Sgblack@eecs.umich.edu def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags): 4383270SN/A # XXX Need to take care of pstate.hpriv as well. The lower ASIs 4393270SN/A # are split into ones that are available in priv and hpriv, and 4403270SN/A # those that are only available in hpriv 4413379SN/A addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 4423379SN/A addrCalcImm = 'EA = Rs1 + imm + offset;' 4433274SN/A iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) 4443274SN/A iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) 4453270SN/A header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 4463270SN/A decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 4473270SN/A decode_block = ROrImmDecode.subst(iop) 4483274SN/A matcher = re.compile(r'Frd_N') 4493274SN/A exec_output = '' 4503391Sgblack@eecs.umich.edu for microPc in range(8): 4513280SN/A flag_code = '' 4523391Sgblack@eecs.umich.edu if (microPc == 7): 4533388Sgblack@eecs.umich.edu flag_code = "flags[IsLastMicroOp] = true;" 4543440Sgblack@eecs.umich.edu else: 4553440Sgblack@eecs.umich.edu flag_code = "flags[IsDelayedCommit] = true;" 4563391Sgblack@eecs.umich.edu pcedCode = matcher.sub("Frd_%d" % microPc, code) 4573274SN/A iop = InstObjParams(name, Name, 'BlockMem', pcedCode, 4583274SN/A opt_flags, {"ea_code": addrCalcReg, 4593391Sgblack@eecs.umich.edu "fault_check": faultCode, "micro_pc": microPc, 4603280SN/A "set_flags": flag_code}) 4613274SN/A iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode, 4623274SN/A opt_flags, {"ea_code": addrCalcImm, 4633391Sgblack@eecs.umich.edu "fault_check": faultCode, "micro_pc": microPc, 4643280SN/A "set_flags": flag_code}) 4653280SN/A decoder_output += BlockMemMicroConstructor.subst(iop) 4663280SN/A decoder_output += BlockMemMicroConstructor.subst(iop_imm) 4673439Sgblack@eecs.umich.edu exec_output += doDualSplitExecute( 4683391Sgblack@eecs.umich.edu pcedCode, addrCalcReg, addrCalcImm, execute, faultCode, 4693391Sgblack@eecs.umich.edu makeMicroName(name, microPc), 4703391Sgblack@eecs.umich.edu makeMicroName(name + "Imm", microPc), 4713391Sgblack@eecs.umich.edu makeMicroName(Name, microPc), 4723391Sgblack@eecs.umich.edu makeMicroName(Name + "Imm", microPc), 4733810Sgblack@eecs.umich.edu asi, opt_flags); 4743391Sgblack@eecs.umich.edu faultCode = '' 4753270SN/A return (header_output, decoder_output, exec_output, decode_block) 4763835Sgblack@eecs.umich.edu 4773835Sgblack@eecs.umich.edu 4783835Sgblack@eecs.umich.edu def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags): 4793835Sgblack@eecs.umich.edu addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 4803835Sgblack@eecs.umich.edu addrCalcImm = 'EA = Rs1 + imm + offset;' 4813835Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'TwinMem', code, opt_flags) 4823835Sgblack@eecs.umich.edu iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', code, opt_flags) 4833835Sgblack@eecs.umich.edu header_output = TwinMemDeclare.subst(iop) + TwinMemDeclare.subst(iop_imm) 4843835Sgblack@eecs.umich.edu decoder_output = TwinMemConstructor.subst(iop) + TwinMemConstructor.subst(iop_imm) 4853835Sgblack@eecs.umich.edu decode_block = ROrImmDecode.subst(iop) 4863835Sgblack@eecs.umich.edu matcher = re.compile(r'RdTwin') 4873835Sgblack@eecs.umich.edu exec_output = '' 4883835Sgblack@eecs.umich.edu for microPc in range(2): 4893835Sgblack@eecs.umich.edu flag_code = '' 4903835Sgblack@eecs.umich.edu pcedCode = '' 4913835Sgblack@eecs.umich.edu if (microPc == 1): 4923835Sgblack@eecs.umich.edu flag_code = "flags[IsLastMicroOp] = true;" 4933835Sgblack@eecs.umich.edu pcedCode = matcher.sub("RdHigh", code) 4943835Sgblack@eecs.umich.edu else: 4953835Sgblack@eecs.umich.edu flag_code = "flags[IsDelayedCommit] = true;" 4963835Sgblack@eecs.umich.edu pcedCode = matcher.sub("RdLow", code) 4973835Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'TwinMem', pcedCode, 4983835Sgblack@eecs.umich.edu opt_flags, {"ea_code": addrCalcReg, 4993835Sgblack@eecs.umich.edu "fault_check": faultCode, "micro_pc": microPc, 5003835Sgblack@eecs.umich.edu "set_flags": flag_code}) 5013835Sgblack@eecs.umich.edu iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', pcedCode, 5023835Sgblack@eecs.umich.edu opt_flags, {"ea_code": addrCalcImm, 5033835Sgblack@eecs.umich.edu "fault_check": faultCode, "micro_pc": microPc, 5043835Sgblack@eecs.umich.edu "set_flags": flag_code}) 5053835Sgblack@eecs.umich.edu decoder_output += BlockMemMicroConstructor.subst(iop) 5063835Sgblack@eecs.umich.edu decoder_output += BlockMemMicroConstructor.subst(iop_imm) 5073835Sgblack@eecs.umich.edu exec_output += doDualSplitExecute( 5083852Sgblack@eecs.umich.edu pcedCode, addrCalcReg, addrCalcImm, LoadExecute, faultCode, 5093835Sgblack@eecs.umich.edu makeMicroName(name, microPc), 5103835Sgblack@eecs.umich.edu makeMicroName(name + "Imm", microPc), 5113835Sgblack@eecs.umich.edu makeMicroName(Name, microPc), 5123835Sgblack@eecs.umich.edu makeMicroName(Name + "Imm", microPc), 5133835Sgblack@eecs.umich.edu asi, opt_flags); 5143835Sgblack@eecs.umich.edu faultCode = '' 5153835Sgblack@eecs.umich.edu return (header_output, decoder_output, exec_output, decode_block) 5163835Sgblack@eecs.umich.edu 5173270SN/A}}; 5183270SN/A 5193810Sgblack@eecs.umich.edudef format BlockLoad(code, asi, *opt_flags) {{ 5203391Sgblack@eecs.umich.edu # We need to make sure to check the highest priority fault last. 5213391Sgblack@eecs.umich.edu # That way, if other faults have been detected, they'll be overwritten 5223391Sgblack@eecs.umich.edu # rather than the other way around. 5233391Sgblack@eecs.umich.edu faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck 5243270SN/A (header_output, 5253270SN/A decoder_output, 5263270SN/A exec_output, 5273391Sgblack@eecs.umich.edu decode_block) = doBlockMemFormat(code, faultCode, 5283810Sgblack@eecs.umich.edu LoadExecute, name, Name, asi, opt_flags) 5293270SN/A}}; 5303270SN/A 5313810Sgblack@eecs.umich.edudef format BlockStore(code, asi, *opt_flags) {{ 5323391Sgblack@eecs.umich.edu # We need to make sure to check the highest priority fault last. 5333391Sgblack@eecs.umich.edu # That way, if other faults have been detected, they'll be overwritten 5343391Sgblack@eecs.umich.edu # rather than the other way around. 5353391Sgblack@eecs.umich.edu faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck 5363270SN/A (header_output, 5373270SN/A decoder_output, 5383270SN/A exec_output, 5393391Sgblack@eecs.umich.edu decode_block) = doBlockMemFormat(code, faultCode, 5403810Sgblack@eecs.umich.edu StoreExecute, name, Name, asi, opt_flags) 5413270SN/A}}; 5423835Sgblack@eecs.umich.edu 5433835Sgblack@eecs.umich.edudef format TwinLoad(code, asi, *opt_flags) {{ 5443835Sgblack@eecs.umich.edu faultCode = AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck 5453835Sgblack@eecs.umich.edu (header_output, 5463835Sgblack@eecs.umich.edu decoder_output, 5473835Sgblack@eecs.umich.edu exec_output, 5483835Sgblack@eecs.umich.edu decode_block) = doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags) 5493835Sgblack@eecs.umich.edu}}; 550