basicmem.isa revision 2591 
1////////////////////////////////////////////////////////////////////
2//
3// Mem instructions
4//
5
6output header {{
7        /**
8         * Base class for memory operations.
9         */
10        class Mem : public SparcStaticInst
11        {
12          protected:
13
14            // Constructor
15            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
16                SparcStaticInst(mnem, _machInst, __opClass)
17            {
18            }
19
20            std::string generateDisassembly(Addr pc,
21                    const SymbolTable *symtab) const;
22        };
23
24        /**
25         * Class for memory operations which use an immediate offset.
26         */
27        class MemImm : public Mem
28        {
29          protected:
30
31            // Constructor
32            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
33                Mem(mnem, _machInst, __opClass)
34            {
35                imm = sign_ext(SIMM13, 13);
36            }
37
38            std::string generateDisassembly(Addr pc,
39                    const SymbolTable *symtab) const;
40
41            int32_t imm;
42        };
43}};
44
45output decoder {{
46        std::string Mem::generateDisassembly(Addr pc,
47                const SymbolTable *symtab) const
48        {
49            std::stringstream response;
50            bool load = flags[IsLoad];
51            bool save = flags[IsStore];
52
53            printMnemonic(response, mnemonic);
54            if(save)
55            {
56                printReg(response, _srcRegIdx[0]);
57                ccprintf(response, ", ");
58            }
59            ccprintf(response, "[ ");
60            printReg(response, _srcRegIdx[!save ? 0 : 1]);
61            ccprintf(response, " + ");
62            printReg(response, _srcRegIdx[!save ? 1 : 2]);
63            ccprintf(response, " ]");
64            if(load)
65            {
66                ccprintf(response, ", ");
67                printReg(response, _destRegIdx[0]);
68            }
69
70            return response.str();
71        }
72
73        std::string MemImm::generateDisassembly(Addr pc,
74                const SymbolTable *symtab) const
75        {
76            std::stringstream response;
77            bool load = flags[IsLoad];
78            bool save = flags[IsStore];
79
80            printMnemonic(response, mnemonic);
81            if(save)
82            {
83                printReg(response, _srcRegIdx[0]);
84                ccprintf(response, ", ");
85            }
86            ccprintf(response, "[ ");
87            printReg(response, _srcRegIdx[!save ? 0 : 1]);
88            if(imm >= 0)
89                ccprintf(response, " + 0x%x ]", imm);
90            else
91                ccprintf(response, " + -0x%x ]", -imm);
92            if(load)
93            {
94                ccprintf(response, ", ");
95                printReg(response, _destRegIdx[0]);
96            }
97
98            return response.str();
99        }
100}};
101
102def template MemExecute {{
103        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
104                Trace::InstRecord *traceData) const
105        {
106            Fault fault = NoFault;
107            Addr EA;
108            %(op_decl)s;
109            %(op_rd)s;
110            %(ea_code)s;
111            DPRINTF(Sparc, "The address is 0x%x\n", EA);
112            %(load)s;
113            %(code)s;
114            %(store)s;
115
116            if(fault == NoFault)
117            {
118                //Write the resulting state to the execution context
119                %(op_wb)s;
120            }
121
122            return fault;
123        }
124}};
125
126let {{
127    # Leave memAccessFlags at 0 for now
128    loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
129    storeString = "uint64_t write_result = 0; \
130    xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
131
132    def doMemFormat(code, load, store, name, Name, opt_flags):
133        addrCalcReg = 'EA = Rs1 + Rs2;'
134        addrCalcImm = 'EA = Rs1 + imm;'
135        iop = InstObjParams(name, Name, 'Mem', code,
136                opt_flags, ("ea_code", addrCalcReg),
137                ("load", load), ("store", store))
138        iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
139                opt_flags, ("ea_code", addrCalcImm),
140                ("load", load), ("store", store))
141        header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
142        decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
143        decode_block = ROrImmDecode.subst(iop)
144        exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
145        return (header_output, decoder_output, exec_output, decode_block)
146}};
147
148def format Load(code, width, *opt_flags) {{
149        (header_output,
150         decoder_output,
151         exec_output,
152         decode_block) = doMemFormat(code,
153             loadString % {"width":width}, '', name, Name, opt_flags)
154}};
155
156def format Store(code, width, *opt_flags) {{
157        (header_output,
158         decoder_output,
159         exec_output,
160         decode_block) = doMemFormat(code, '',
161             storeString % {"width":width}, name, Name, opt_flags)
162}};
163
164def format LoadStore(code, width, *opt_flags) {{
165        (header_output,
166         decoder_output,
167         exec_output,
168         decode_block) = doMemFormat(code,
169             loadString % {"width":width}, storeString % {"width":width},
170             name, Name, opt_flags)
171}};
172