basicmem.isa revision 2561 
1////////////////////////////////////////////////////////////////////
2//
3// Mem instructions
4//
5
6output header {{
7        /**
8         * Base class for memory operations.
9         */
10        class Mem : public SparcStaticInst
11        {
12          protected:
13
14            // Constructor
15            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
16                SparcStaticInst(mnem, _machInst, __opClass)
17            {
18            }
19
20            std::string generateDisassembly(Addr pc,
21                    const SymbolTable *symtab) const;
22        };
23
24        /**
25         * Class for memory operations which use an immediate offset.
26         */
27        class MemImm : public Mem
28        {
29          protected:
30
31            // Constructor
32            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
33                Mem(mnem, _machInst, __opClass), imm(SIMM13)
34            {
35            }
36
37            std::string generateDisassembly(Addr pc,
38                    const SymbolTable *symtab) const;
39
40            int32_t imm;
41        };
42}};
43
44output decoder {{
45        std::string Mem::generateDisassembly(Addr pc,
46                const SymbolTable *symtab) const
47        {
48            std::stringstream response;
49            bool load = flags[IsLoad];
50            bool save = flags[IsStore];
51
52            printMnemonic(response, mnemonic);
53            if(save)
54            {
55                printReg(response, _srcRegIdx[0]);
56                ccprintf(response, ", ");
57            }
58            ccprintf(response, "[ ");
59            printReg(response, _srcRegIdx[!save ? 0 : 1]);
60            ccprintf(response, " + ");
61            printReg(response, _srcRegIdx[!save ? 1 : 2]);
62            ccprintf(response, " ]");
63            if(load)
64            {
65                ccprintf(response, ", ");
66                printReg(response, _destRegIdx[0]);
67            }
68
69            return response.str();
70        }
71
72        std::string MemImm::generateDisassembly(Addr pc,
73                const SymbolTable *symtab) const
74        {
75            std::stringstream response;
76            bool load = flags[IsLoad];
77            bool save = flags[IsStore];
78
79            printMnemonic(response, mnemonic);
80            if(save)
81            {
82                printReg(response, _srcRegIdx[0]);
83                ccprintf(response, ", ");
84            }
85            ccprintf(response, "[ ");
86            printReg(response, _srcRegIdx[!save ? 0 : 1]);
87            ccprintf(response, " + 0x%x ]", imm);
88            if(load)
89            {
90                ccprintf(response, ", ");
91                printReg(response, _destRegIdx[0]);
92            }
93
94            return response.str();
95        }
96}};
97
98def template MemExecute {{
99        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
100                Trace::InstRecord *traceData) const
101        {
102            Fault fault = NoFault;
103            Addr EA;
104            %(op_decl)s;
105            %(op_rd)s;
106            %(ea_code)s;
107            %(load)s;
108            %(code)s;
109            %(store)s;
110
111            if(fault == NoFault)
112            {
113                //Write the resulting state to the execution context
114                %(op_wb)s;
115            }
116
117            return fault;
118        }
119}};
120
121let {{
122    # Leave memAccessFlags at 0 for now
123    loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
124    storeString = "uint64_t write_result = 0; \
125    xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
126
127    def doMemFormat(code, load, store, name, Name, opt_flags):
128        addrCalcReg = 'EA = Rs1 + Rs2;'
129        addrCalcImm = 'EA = Rs1 + SIMM13;'
130        iop = InstObjParams(name, Name, 'Mem', code,
131                opt_flags, ("ea_code", addrCalcReg),
132                ("load", load), ("store", store))
133        iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
134                opt_flags, ("ea_code", addrCalcImm),
135                ("load", load), ("store", store))
136        header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
137        decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
138        decode_block = ROrImmDecode.subst(iop)
139        exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
140        return (header_output, decoder_output, exec_output, decode_block)
141}};
142
143def format Load(code, width, *opt_flags) {{
144        (header_output,
145         decoder_output,
146         exec_output,
147         decode_block) = doMemFormat(code,
148             loadString % {"width":width}, '', name, Name, opt_flags)
149}};
150
151def format Store(code, width, *opt_flags) {{
152        (header_output,
153         decoder_output,
154         exec_output,
155         decode_block) = doMemFormat(code, '',
156             storeString % {"width":width}, name, Name, opt_flags)
157}};
158
159def format LoadStore(code, width, *opt_flags) {{
160        (header_output,
161         decoder_output,
162         exec_output,
163         decode_block) = doMemFormat(code,
164             loadString % {"width":width}, storeString % {"width":width},
165             name, Name, opt_flags)
166}};
167