branch.isa revision 7741:340b6f01d69b 
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Gabe Black
28//          Steve Reinhardt
29
30////////////////////////////////////////////////////////////////////
31//
32// Branch instructions
33//
34
35output header {{
36        /**
37         * Base class for branch operations.
38         */
39        class Branch : public SparcStaticInst
40        {
41          protected:
42            // Constructor
43            Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
44                SparcStaticInst(mnem, _machInst, __opClass)
45            {
46            }
47
48            std::string generateDisassembly(Addr pc,
49                    const SymbolTable *symtab) const;
50        };
51
52        /**
53         * Base class for branch operations with an immediate displacement.
54         */
55        class BranchDisp : public Branch
56        {
57          protected:
58            // Constructor
59            BranchDisp(const char *mnem, ExtMachInst _machInst,
60                    OpClass __opClass) :
61                Branch(mnem, _machInst, __opClass)
62            {
63            }
64
65            std::string generateDisassembly(Addr pc,
66                    const SymbolTable *symtab) const;
67
68            int32_t disp;
69        };
70
71        /**
72         * Base class for branches with n bit displacements.
73         */
74        template<int bits>
75        class BranchNBits : public BranchDisp
76        {
77          protected:
78            // Constructor
79            BranchNBits(const char *mnem, ExtMachInst _machInst,
80                    OpClass __opClass) :
81                BranchDisp(mnem, _machInst, __opClass)
82            {
83                disp = sext<bits + 2>((_machInst & mask(bits)) << 2);
84            }
85        };
86
87        /**
88         * Base class for 16bit split displacements.
89         */
90        class BranchSplit : public BranchDisp
91        {
92          protected:
93            // Constructor
94            BranchSplit(const char *mnem, ExtMachInst _machInst,
95                    OpClass __opClass) :
96                BranchDisp(mnem, _machInst, __opClass)
97            {
98                disp = sext<18>((D16HI << 16) | (D16LO << 2));
99            }
100        };
101
102        /**
103         * Base class for branches that use an immediate and a register to
104         * compute their displacements.
105         */
106        class BranchImm13 : public Branch
107        {
108          protected:
109            // Constructor
110            BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
111                Branch(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
112            {
113            }
114
115            std::string generateDisassembly(Addr pc,
116                    const SymbolTable *symtab) const;
117
118            int32_t imm;
119        };
120}};
121
122output decoder {{
123
124        template class BranchNBits<19>;
125
126        template class BranchNBits<22>;
127
128        template class BranchNBits<30>;
129
130        std::string
131        Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
132        {
133            std::stringstream response;
134
135            printMnemonic(response, mnemonic);
136            printRegArray(response, _srcRegIdx, _numSrcRegs);
137            if (_numDestRegs && _numSrcRegs)
138                    response << ", ";
139            printDestReg(response, 0);
140
141            return response.str();
142        }
143
144        std::string
145        BranchImm13::generateDisassembly(Addr pc,
146                const SymbolTable *symtab) const
147        {
148            std::stringstream response;
149
150            printMnemonic(response, mnemonic);
151            printRegArray(response, _srcRegIdx, _numSrcRegs);
152            if (_numSrcRegs > 0)
153                response << ", ";
154            ccprintf(response, "0x%x", imm);
155            if (_numDestRegs > 0)
156                response << ", ";
157            printDestReg(response, 0);
158
159            return response.str();
160        }
161
162        std::string
163        BranchDisp::generateDisassembly(Addr pc,
164                const SymbolTable *symtab) const
165        {
166            std::stringstream response;
167            std::string symbol;
168            Addr symbolAddr;
169
170            Addr target = disp + pc;
171
172            printMnemonic(response, mnemonic);
173            ccprintf(response, "0x%x", target);
174
175            if (symtab &&
176                    symtab->findNearestSymbol(target, symbol, symbolAddr)) {
177                ccprintf(response, " <%s", symbol);
178                if (symbolAddr != target)
179                    ccprintf(response, "+%d>", target - symbolAddr);
180                else
181                    ccprintf(response, ">");
182            }
183
184            return response.str();
185        }
186}};
187
188def template JumpExecute {{
189        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
190                Trace::InstRecord *traceData) const
191        {
192            // Attempt to execute the instruction
193            Fault fault = NoFault;
194
195            %(op_decl)s;
196            %(op_rd)s;
197
198            PCS = PCS;
199            %(code)s;
200
201            if (fault == NoFault) {
202                // Write the resulting state to the execution context
203                %(op_wb)s;
204            }
205
206            return fault;
207        }
208}};
209
210def template BranchExecute {{
211        Fault
212        %(class_name)s::execute(%(CPU_exec_context)s *xc,
213                Trace::InstRecord *traceData) const
214        {
215            // Attempt to execute the instruction
216            Fault fault = NoFault;
217
218            %(op_decl)s;
219            %(op_rd)s;
220
221            if (%(cond)s) {
222                %(code)s;
223            } else {
224                %(fail)s;
225            }
226
227            if (fault == NoFault) {
228                // Write the resulting state to the execution context
229                %(op_wb)s;
230            }
231
232            return fault;
233        }
234}};
235
236def template BranchDecode {{
237    if (A)
238        return new %(class_name)sAnnul("%(mnemonic)s,a", machInst);
239    else
240        return new %(class_name)s("%(mnemonic)s", machInst);
241}};
242
243// Primary format for branch instructions:
244def format Branch(code, *opt_flags) {{
245    (usesImm, code, immCode,
246     rString, iString) = splitOutImm(code)
247    iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
248    header_output = BasicDeclare.subst(iop)
249    decoder_output = BasicConstructor.subst(iop)
250    exec_output = JumpExecute.subst(iop)
251    if usesImm:
252        imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
253                immCode, opt_flags)
254        header_output += BasicDeclare.subst(imm_iop)
255        decoder_output += BasicConstructor.subst(imm_iop)
256        exec_output += JumpExecute.subst(imm_iop)
257        decode_block = ROrImmDecode.subst(iop)
258    else:
259        decode_block = BasicDecode.subst(iop)
260}};
261
262let {{
263    def doBranch(name, Name, base, cond,
264            code, annul_code, fail, annul_fail, opt_flags):
265        iop = InstObjParams(name, Name, base,
266                {"code": code,
267                 "fail": fail,
268                 "cond": cond
269                },
270                opt_flags)
271        header_output = BasicDeclareWithMnemonic.subst(iop)
272        decoder_output = BasicConstructorWithMnemonic.subst(iop)
273        exec_output = BranchExecute.subst(iop)
274        if annul_code == "None":
275            decode_block = BasicDecodeWithMnemonic.subst(iop)
276        else:
277            decode_block = BranchDecode.subst(iop)
278
279        if annul_code != "None":
280            iop = InstObjParams(name + ',a', Name + 'Annul', base,
281                    {"code": annul_code,
282                     "fail": annul_fail,
283                     "cond": cond
284                    },
285                    opt_flags)
286            header_output += BasicDeclareWithMnemonic.subst(iop)
287            decoder_output += BasicConstructorWithMnemonic.subst(iop)
288            exec_output += BranchExecute.subst(iop)
289        return (header_output, decoder_output, exec_output, decode_block)
290
291    def doCondBranch(name, Name, base, cond, code, opt_flags):
292        return doBranch(name, Name, base, cond, code, code,
293                'PCS = PCS;',
294                '''
295                SparcISA::PCState pc = PCS;
296                pc.nnpc(pc.npc() + 8);
297                pc.npc(pc.npc() + 4);
298                PCS = pc;
299                ''',
300                opt_flags)
301
302    def doUncondBranch(name, Name, base, code, annul_code, opt_flags):
303        return doBranch(name, Name, base, "true", code, annul_code,
304                ";", ";", opt_flags)
305
306    default_branch_code = '''
307    SparcISA::PCState pc = PCS;
308    pc.nnpc(pc.pc() + disp);
309    PCS = pc;
310    '''
311}};
312
313// Format for branch instructions with n bit displacements:
314def format BranchN(bits, code=default_branch_code,
315        test=None, annul_code=None, *opt_flags) {{
316    if code == "default_branch_code":
317        code = default_branch_code
318    if test != "None":
319        (header_output,
320         decoder_output,
321         exec_output,
322         decode_block) = doCondBranch(name, Name,
323             "BranchNBits<%d>" % bits, test, code, opt_flags)
324    else:
325        (header_output,
326         decoder_output,
327         exec_output,
328         decode_block) = doUncondBranch(name, Name,
329             "BranchNBits<%d>" % bits, code, annul_code, opt_flags)
330}};
331
332// Format for branch instructions with split displacements:
333def format BranchSplit(code=default_branch_code,
334        test=None, annul_code=None, *opt_flags) {{
335    if code == "default_branch_code":
336        code = default_branch_code
337    if test != "None":
338        (header_output,
339         decoder_output,
340         exec_output,
341         decode_block) = doCondBranch(name, Name,
342             "BranchSplit", test, code, opt_flags)
343    else:
344        (header_output,
345         decoder_output,
346         exec_output,
347         decode_block) = doUncondBranch(name, Name,
348             "BranchSplit", code, annul_code, opt_flags)
349}};
350
351