decoder.isa revision 7085:e4c5fbbc8633
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: bpa(19, annul_code={{ 49 NPC = xc->readPC() + disp; 50 NNPC = NPC + 4; 51 }}); 52 //Branch Never 53 0x0: bpn(19, {{;}}, 54 annul_code={{ 55 NNPC = NPC + 8; 56 NPC = NPC + 4; 57 }}); 58 default: decode BPCC 59 { 60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 62 } 63 } 64 //bicc 65 0x2: decode COND2 66 { 67 //Branch Always 68 0x8: ba(22, annul_code={{ 69 NPC = xc->readPC() + disp; 70 NNPC = NPC + 4; 71 }}); 72 //Branch Never 73 0x0: bn(22, {{;}}, 74 annul_code={{ 75 NNPC = NPC + 8; 76 NPC = NPC + 4; 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { 85 0x1: bpreq(test={{Rs1.sdw == 0}}); 86 0x2: bprle(test={{Rs1.sdw <= 0}}); 87 0x3: bprl(test={{Rs1.sdw < 0}}); 88 0x5: bprne(test={{Rs1.sdw != 0}}); 89 0x6: bprg(test={{Rs1.sdw > 0}}); 90 0x7: bprge(test={{Rs1.sdw >= 0}}); 91 } 92 } 93 //SETHI (or NOP if rd == 0 and imm == 0) 94 0x4: SetHi::sethi({{Rd.udw = imm;}}); 95 //fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 //Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = xc->readPC() + disp; 101 NNPC = NPC + 4; 102 }}); 103 //Branch Never 104 0x0: fbpn(22, {{;}}, 105 annul_code={{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}); 109 default: decode BPCC { 110 0x0: fbpfcc0(19, test= 111 {{passesFpCondition(Fsr<11:10>, COND2)}}); 112 0x1: fbpfcc1(19, test= 113 {{passesFpCondition(Fsr<33:32>, COND2)}}); 114 0x2: fbpfcc2(19, test= 115 {{passesFpCondition(Fsr<35:34>, COND2)}}); 116 0x3: fbpfcc3(19, test= 117 {{passesFpCondition(Fsr<37:36>, COND2)}}); 118 } 119 } 120 } 121 //fbfcc 122 0x6: decode COND2 { 123 format BranchN { 124 //Branch Always 125 0x8: fba(22, annul_code={{ 126 NPC = xc->readPC() + disp; 127 NNPC = NPC + 4; 128 }}); 129 //Branch Never 130 0x0: fbn(22, {{;}}, 131 annul_code={{ 132 NNPC = NPC + 8; 133 NPC = NPC + 4; 134 }}); 135 default: fbfcc(22, test= 136 {{passesFpCondition(Fsr<11:10>, COND2)}}); 137 } 138 } 139 } 140 0x1: BranchN::call(30, {{ 141 if (Pstate<3:>) 142 R15 = (xc->readPC())<31:0>; 143 else 144 R15 = xc->readPC(); 145 NNPC = R15 + disp; 146 }}); 147 0x2: decode OP3 { 148 format IntOp { 149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 154 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 155 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 156 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 157 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 158 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 159 0x0A: umul({{ 160 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 161 Y = Rd<63:32>; 162 }}); 163 0x0B: smul({{ 164 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 165 Y = Rd.sdw<63:32>; 166 }}); 167 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 168 0x0D: udivx({{ 169 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 170 else Rd.udw = Rs1.udw / Rs2_or_imm13; 171 }}); 172 0x0E: udiv({{ 173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 174 else 175 { 176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 177 if(Rd.udw >> 32 != 0) 178 Rd.udw = 0xFFFFFFFF; 179 } 180 }}); 181 0x0F: sdiv({{ 182 if(Rs2_or_imm13.sdw == 0) 183 fault = new DivisionByZero; 184 else 185 { 186 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 187 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 188 Rd.udw = 0x7FFFFFFF; 189 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 190 Rd.udw = ULL(0xFFFFFFFF80000000); 191 } 192 }}); 193 } 194 format IntOpCc { 195 0x10: addcc({{ 196 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 197 Rd = res = op1 + op2; 198 }}); 199 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 200 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 201 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 202 0x14: subcc({{ 203 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 204 Rd = res = op1 - op2; 205 }}, sub=True); 206 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 207 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 208 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 209 0x18: addccc({{ 210 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 211 Rd = res = op1 + op2 + Ccr<0:>; 212 }}); 213 0x1A: IntOpCcRes::umulcc({{ 214 uint64_t resTemp; 215 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 216 Y = resTemp<63:32>;}}); 217 0x1B: IntOpCcRes::smulcc({{ 218 int64_t resTemp; 219 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 220 Y = resTemp<63:32>;}}); 221 0x1C: subccc({{ 222 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 223 Rd = res = op1 - op2 - Ccr<0:>; 224 }}, sub=True); 225 0x1D: IntOpCcRes::udivxcc({{ 226 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 227 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 228 0x1E: IntOpCcRes::udivcc({{ 229 uint64_t resTemp; 230 uint32_t val2 = Rs2_or_imm13.udw; 231 int32_t overflow = 0; 232 if(val2 == 0) fault = new DivisionByZero; 233 else 234 { 235 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 236 overflow = (resTemp<63:32> != 0); 237 if(overflow) Rd = resTemp = 0xFFFFFFFF; 238 else Rd = resTemp; 239 } 240 }}, iv={{overflow}}); 241 0x1F: IntOpCcRes::sdivcc({{ 242 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 243 bool overflow = false, underflow = false; 244 if(val2 == 0) fault = new DivisionByZero; 245 else 246 { 247 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 248 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 249 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 250 if(overflow) Rd = 0x7FFFFFFF; 251 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 252 } 253 }}, iv={{overflow || underflow}}); 254 0x20: taddcc({{ 255 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 256 Rd = res = Rs1 + op2; 257 }}, iv={{ 258 (op1 & mask(2)) || (op2 & mask(2)) || 259 findOverflow(32, res, op1, op2) 260 }}); 261 0x21: tsubcc({{ 262 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 263 Rd = res = Rs1 - op2; 264 }}, iv={{ 265 (op1 & mask(2)) || (op2 & mask(2)) || 266 findOverflow(32, res, op1, ~op2) 267 }}, sub=True); 268 0x22: taddcctv({{ 269 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 270 Rd = res = op1 + op2; 271 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 272 findOverflow(32, res, op1, op2); 273 if(overflow) fault = new TagOverflow; 274 }}, iv={{overflow}}); 275 0x23: tsubcctv({{ 276 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 277 Rd = res = op1 - op2; 278 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 279 findOverflow(32, res, op1, ~op2); 280 if(overflow) fault = new TagOverflow; 281 }}, iv={{overflow}}, sub=True); 282 0x24: mulscc({{ 283 int32_t savedLSB = Rs1<0:>; 284 285 //Step 1 286 int64_t multiplicand = Rs2_or_imm13; 287 //Step 2 288 int32_t partialP = Rs1<31:1> | 289 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 290 //Step 3 291 int32_t added = Y<0:> ? multiplicand : 0; 292 int64_t res, op1 = partialP, op2 = added; 293 Rd = res = partialP + added; 294 //Steps 4 & 5 295 Y = Y<31:1> | (savedLSB << 31); 296 }}); 297 } 298 format IntOp 299 { 300 0x25: decode X { 301 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 302 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 303 } 304 0x26: decode X { 305 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 306 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 307 } 308 0x27: decode X { 309 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 310 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 311 } 312 0x28: decode RS1 { 313 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 314 //1 should cause an illegal instruction exception 315 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 316 0x03: NoPriv::rdasi({{Rd = Asi;}}); 317 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 318 0x05: NoPriv::rdpc({{ 319 if(Pstate<3:>) 320 Rd = (xc->readPC())<31:0>; 321 else 322 Rd = xc->readPC();}}); 323 0x06: NoPriv::rdfprs({{ 324 //Wait for all fpops to finish. 325 Rd = Fprs; 326 }}); 327 //7-14 should cause an illegal instruction exception 328 0x0F: decode I { 329 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 330 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 331 } 332 0x10: Priv::rdpcr({{Rd = Pcr;}}); 333 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 334 //0x12 should cause an illegal instruction exception 335 0x13: NoPriv::rdgsr({{ 336 fault = checkFpEnableFault(xc); 337 if (fault) 338 return fault; 339 Rd = Gsr; 340 }}); 341 //0x14-0x15 should cause an illegal instruction exception 342 0x16: Priv::rdsoftint({{Rd = Softint;}}); 343 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 344 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 345 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 346 0x1A: Priv::rdstrand_sts_reg({{ 347 if(Pstate<2:> && !Hpstate<2:>) 348 Rd = StrandStsReg<0:>; 349 else 350 Rd = StrandStsReg; 351 }}); 352 //0x1A is supposed to be reserved, but it reads the strand 353 //status register. 354 //0x1B-0x1F should cause an illegal instruction exception 355 } 356 0x29: decode RS1 { 357 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 358 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 359 //0x02 should cause an illegal instruction exception 360 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 361 //0x04 should cause an illegal instruction exception 362 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 363 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 364 //0x07-0x1E should cause an illegal instruction exception 365 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 366 } 367 0x2A: decode RS1 { 368 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 369 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 370 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 371 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 372 0x04: Priv::rdprtick({{Rd = Tick;}}); 373 0x05: Priv::rdprtba({{Rd = Tba;}}); 374 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 375 0x07: Priv::rdprtl({{Rd = Tl;}}); 376 0x08: Priv::rdprpil({{Rd = Pil;}}); 377 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 378 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 379 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 380 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 381 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 382 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 383 //0x0F should cause an illegal instruction exception 384 0x10: Priv::rdprgl({{Rd = Gl;}}); 385 //0x11-0x1F should cause an illegal instruction exception 386 } 387 0x2B: BasicOperate::flushw({{ 388 if(NWindows - 2 - Cansave != 0) 389 { 390 if(Otherwin) 391 fault = new SpillNOther(4*Wstate<5:3>); 392 else 393 fault = new SpillNNormal(4*Wstate<2:0>); 394 } 395 }}); 396 0x2C: decode MOVCC3 397 { 398 0x0: decode CC 399 { 400 0x0: movccfcc0({{ 401 if(passesCondition(Fsr<11:10>, COND4)) 402 Rd = Rs2_or_imm11; 403 else 404 Rd = Rd; 405 }}); 406 0x1: movccfcc1({{ 407 if(passesCondition(Fsr<33:32>, COND4)) 408 Rd = Rs2_or_imm11; 409 else 410 Rd = Rd; 411 }}); 412 0x2: movccfcc2({{ 413 if(passesCondition(Fsr<35:34>, COND4)) 414 Rd = Rs2_or_imm11; 415 else 416 Rd = Rd; 417 }}); 418 0x3: movccfcc3({{ 419 if(passesCondition(Fsr<37:36>, COND4)) 420 Rd = Rs2_or_imm11; 421 else 422 Rd = Rd; 423 }}); 424 } 425 0x1: decode CC 426 { 427 0x0: movcci({{ 428 if(passesCondition(Ccr<3:0>, COND4)) 429 Rd = Rs2_or_imm11; 430 else 431 Rd = Rd; 432 }}); 433 0x2: movccx({{ 434 if(passesCondition(Ccr<7:4>, COND4)) 435 Rd = Rs2_or_imm11; 436 else 437 Rd = Rd; 438 }}); 439 } 440 } 441 0x2D: sdivx({{ 442 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 443 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 444 }}); 445 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 446 0x2F: decode RCOND3 447 { 448 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 449 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 450 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 451 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 452 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 453 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 454 } 455 0x30: decode RD { 456 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 457 //0x01 should cause an illegal instruction exception 458 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 459 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 460 //0x04-0x05 should cause an illegal instruction exception 461 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 462 //0x07-0x0E should cause an illegal instruction exception 463 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 464 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 465 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 466 //0x12 should cause an illegal instruction exception 467 0x13: NoPriv::wrgsr({{ 468 if(Fprs<2:> == 0 || Pstate<4:> == 0) 469 return new FpDisabled; 470 Gsr = Rs1 ^ Rs2_or_imm13; 471 }}); 472 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 473 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 474 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 475 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 476 0x18: NoPriv::wrstick({{ 477 if(!Hpstate<2:>) 478 return new IllegalInstruction; 479 Stick = Rs1 ^ Rs2_or_imm13; 480 }}); 481 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 482 0x1A: Priv::wrstrand_sts_reg({{ 483 StrandStsReg = Rs1 ^ Rs2_or_imm13; 484 }}); 485 //0x1A is supposed to be reserved, but it writes the strand 486 //status register. 487 //0x1B-0x1F should cause an illegal instruction exception 488 } 489 0x31: decode FCN { 490 0x0: Priv::saved({{ 491 assert(Cansave < NWindows - 2); 492 assert(Otherwin || Canrestore); 493 Cansave = Cansave + 1; 494 if(Otherwin == 0) 495 Canrestore = Canrestore - 1; 496 else 497 Otherwin = Otherwin - 1; 498 }}); 499 0x1: Priv::restored({{ 500 assert(Cansave || Otherwin); 501 assert(Canrestore < NWindows - 2); 502 Canrestore = Canrestore + 1; 503 if(Otherwin == 0) 504 Cansave = Cansave - 1; 505 else 506 Otherwin = Otherwin - 1; 507 508 if(Cleanwin < NWindows - 1) 509 Cleanwin = Cleanwin + 1; 510 }}); 511 } 512 0x32: decode RD { 513 0x00: Priv::wrprtpc( 514 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 515 0x01: Priv::wrprtnpc( 516 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 517 0x02: Priv::wrprtstate( 518 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 519 0x03: Priv::wrprtt( 520 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 521 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 522 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 523 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 524 0x07: Priv::wrprtl({{ 525 if(Pstate<2:> && !Hpstate<2:>) 526 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 527 else 528 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 529 }}); 530 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 531 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 532 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 533 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 534 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 535 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 536 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 537 //0x0F should cause an illegal instruction exception 538 0x10: Priv::wrprgl({{ 539 if(Pstate<2:> && !Hpstate<2:>) 540 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 541 else 542 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 543 }}); 544 //0x11-0x1F should cause an illegal instruction exception 545 } 546 0x33: decode RD { 547 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 548 0x01: HPriv::wrhprhtstate( 549 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 550 //0x02 should cause an illegal instruction exception 551 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 552 //0x04 should cause an illegal instruction exception 553 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 554 //0x06-0x01D should cause an illegal instruction exception 555 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 556 } 557 0x34: decode OPF{ 558 format FpBasic{ 559 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 560 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 561 0x03: FpUnimpl::fmovq(); 562 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 563 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 564 0x07: FpUnimpl::fnegq(); 565 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 566 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 567 0x0B: FpUnimpl::fabsq(); 568 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 569 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 570 0x2B: FpUnimpl::fsqrtq(); 571 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 572 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 573 0x43: FpUnimpl::faddq(); 574 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 575 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 576 0x47: FpUnimpl::fsubq(); 577 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 578 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 579 0x4B: FpUnimpl::fmulq(); 580 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 581 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 582 0x4F: FpUnimpl::fdivq(); 583 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 584 0x6E: FpUnimpl::fdmulq(); 585 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 586 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 587 0x83: FpUnimpl::fqtox(); 588 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 589 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 590 0x8C: FpUnimpl::fxtoq(); 591 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 592 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 593 0xC7: FpUnimpl::fqtos(); 594 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 595 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 596 0xCB: FpUnimpl::fqtod(); 597 0xCC: FpUnimpl::fitoq(); 598 0xCD: FpUnimpl::fstoq(); 599 0xCE: FpUnimpl::fdtoq(); 600 0xD1: fstoi({{ 601 Frds.sw = static_cast<int32_t>(Frs2s.sf); 602 float t = Frds.sw; 603 if (t != Frs2s.sf) 604 Fsr = insertBits(Fsr, 4,0, 0x01); 605 }}); 606 0xD2: fdtoi({{ 607 Frds.sw = static_cast<int32_t>(Frs2.df); 608 double t = Frds.sw; 609 if (t != Frs2.df) 610 Fsr = insertBits(Fsr, 4,0, 0x01); 611 }}); 612 0xD3: FpUnimpl::fqtoi(); 613 default: FailUnimpl::fpop1(); 614 } 615 } 616 0x35: decode OPF{ 617 format FpBasic{ 618 0x01: fmovs_fcc0({{ 619 if(passesFpCondition(Fsr<11:10>, COND4)) 620 Frds = Frs2s; 621 else 622 Frds = Frds; 623 }}); 624 0x02: fmovd_fcc0({{ 625 if(passesFpCondition(Fsr<11:10>, COND4)) 626 Frd = Frs2; 627 else 628 Frd = Frd; 629 }}); 630 0x03: FpUnimpl::fmovq_fcc0(); 631 0x25: fmovrsz({{ 632 if(Rs1 == 0) 633 Frds = Frs2s; 634 else 635 Frds = Frds; 636 }}); 637 0x26: fmovrdz({{ 638 if(Rs1 == 0) 639 Frd = Frs2; 640 else 641 Frd = Frd; 642 }}); 643 0x27: FpUnimpl::fmovrqz(); 644 0x41: fmovs_fcc1({{ 645 if(passesFpCondition(Fsr<33:32>, COND4)) 646 Frds = Frs2s; 647 else 648 Frds = Frds; 649 }}); 650 0x42: fmovd_fcc1({{ 651 if(passesFpCondition(Fsr<33:32>, COND4)) 652 Frd = Frs2; 653 else 654 Frd = Frd; 655 }}); 656 0x43: FpUnimpl::fmovq_fcc1(); 657 0x45: fmovrslez({{ 658 if(Rs1 <= 0) 659 Frds = Frs2s; 660 else 661 Frds = Frds; 662 }}); 663 0x46: fmovrdlez({{ 664 if(Rs1 <= 0) 665 Frd = Frs2; 666 else 667 Frd = Frd; 668 }}); 669 0x47: FpUnimpl::fmovrqlez(); 670 0x51: fcmps({{ 671 uint8_t fcc; 672 if(isnan(Frs1s) || isnan(Frs2s)) 673 fcc = 3; 674 else if(Frs1s < Frs2s) 675 fcc = 1; 676 else if(Frs1s > Frs2s) 677 fcc = 2; 678 else 679 fcc = 0; 680 uint8_t firstbit = 10; 681 if(FCMPCC) 682 firstbit = FCMPCC * 2 + 30; 683 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 684 }}); 685 0x52: fcmpd({{ 686 uint8_t fcc; 687 if(isnan(Frs1) || isnan(Frs2)) 688 fcc = 3; 689 else if(Frs1 < Frs2) 690 fcc = 1; 691 else if(Frs1 > Frs2) 692 fcc = 2; 693 else 694 fcc = 0; 695 uint8_t firstbit = 10; 696 if(FCMPCC) 697 firstbit = FCMPCC * 2 + 30; 698 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 699 }}); 700 0x53: FpUnimpl::fcmpq(); 701 0x55: fcmpes({{ 702 uint8_t fcc = 0; 703 if(isnan(Frs1s) || isnan(Frs2s)) 704 fault = new FpExceptionIEEE754; 705 if(Frs1s < Frs2s) 706 fcc = 1; 707 else if(Frs1s > Frs2s) 708 fcc = 2; 709 uint8_t firstbit = 10; 710 if(FCMPCC) 711 firstbit = FCMPCC * 2 + 30; 712 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 713 }}); 714 0x56: fcmped({{ 715 uint8_t fcc = 0; 716 if(isnan(Frs1) || isnan(Frs2)) 717 fault = new FpExceptionIEEE754; 718 if(Frs1 < Frs2) 719 fcc = 1; 720 else if(Frs1 > Frs2) 721 fcc = 2; 722 uint8_t firstbit = 10; 723 if(FCMPCC) 724 firstbit = FCMPCC * 2 + 30; 725 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 726 }}); 727 0x57: FpUnimpl::fcmpeq(); 728 0x65: fmovrslz({{ 729 if(Rs1 < 0) 730 Frds = Frs2s; 731 else 732 Frds = Frds; 733 }}); 734 0x66: fmovrdlz({{ 735 if(Rs1 < 0) 736 Frd = Frs2; 737 else 738 Frd = Frd; 739 }}); 740 0x67: FpUnimpl::fmovrqlz(); 741 0x81: fmovs_fcc2({{ 742 if(passesFpCondition(Fsr<35:34>, COND4)) 743 Frds = Frs2s; 744 else 745 Frds = Frds; 746 }}); 747 0x82: fmovd_fcc2({{ 748 if(passesFpCondition(Fsr<35:34>, COND4)) 749 Frd = Frs2; 750 else 751 Frd = Frd; 752 }}); 753 0x83: FpUnimpl::fmovq_fcc2(); 754 0xA5: fmovrsnz({{ 755 if(Rs1 != 0) 756 Frds = Frs2s; 757 else 758 Frds = Frds; 759 }}); 760 0xA6: fmovrdnz({{ 761 if(Rs1 != 0) 762 Frd = Frs2; 763 else 764 Frd = Frd; 765 }}); 766 0xA7: FpUnimpl::fmovrqnz(); 767 0xC1: fmovs_fcc3({{ 768 if(passesFpCondition(Fsr<37:36>, COND4)) 769 Frds = Frs2s; 770 else 771 Frds = Frds; 772 }}); 773 0xC2: fmovd_fcc3({{ 774 if(passesFpCondition(Fsr<37:36>, COND4)) 775 Frd = Frs2; 776 else 777 Frd = Frd; 778 }}); 779 0xC3: FpUnimpl::fmovq_fcc3(); 780 0xC5: fmovrsgz({{ 781 if(Rs1 > 0) 782 Frds = Frs2s; 783 else 784 Frds = Frds; 785 }}); 786 0xC6: fmovrdgz({{ 787 if(Rs1 > 0) 788 Frd = Frs2; 789 else 790 Frd = Frd; 791 }}); 792 0xC7: FpUnimpl::fmovrqgz(); 793 0xE5: fmovrsgez({{ 794 if(Rs1 >= 0) 795 Frds = Frs2s; 796 else 797 Frds = Frds; 798 }}); 799 0xE6: fmovrdgez({{ 800 if(Rs1 >= 0) 801 Frd = Frs2; 802 else 803 Frd = Frd; 804 }}); 805 0xE7: FpUnimpl::fmovrqgez(); 806 0x101: fmovs_icc({{ 807 if(passesCondition(Ccr<3:0>, COND4)) 808 Frds = Frs2s; 809 else 810 Frds = Frds; 811 }}); 812 0x102: fmovd_icc({{ 813 if(passesCondition(Ccr<3:0>, COND4)) 814 Frd = Frs2; 815 else 816 Frd = Frd; 817 }}); 818 0x103: FpUnimpl::fmovq_icc(); 819 0x181: fmovs_xcc({{ 820 if(passesCondition(Ccr<7:4>, COND4)) 821 Frds = Frs2s; 822 else 823 Frds = Frds; 824 }}); 825 0x182: fmovd_xcc({{ 826 if(passesCondition(Ccr<7:4>, COND4)) 827 Frd = Frs2; 828 else 829 Frd = Frd; 830 }}); 831 0x183: FpUnimpl::fmovq_xcc(); 832 default: FailUnimpl::fpop2(); 833 } 834 } 835 //This used to be just impdep1, but now it's a whole bunch 836 //of instructions 837 0x36: decode OPF{ 838 0x00: FailUnimpl::edge8(); 839 0x01: FailUnimpl::edge8n(); 840 0x02: FailUnimpl::edge8l(); 841 0x03: FailUnimpl::edge8ln(); 842 0x04: FailUnimpl::edge16(); 843 0x05: FailUnimpl::edge16n(); 844 0x06: FailUnimpl::edge16l(); 845 0x07: FailUnimpl::edge16ln(); 846 0x08: FailUnimpl::edge32(); 847 0x09: FailUnimpl::edge32n(); 848 0x0A: FailUnimpl::edge32l(); 849 0x0B: FailUnimpl::edge32ln(); 850 0x10: FailUnimpl::array8(); 851 0x12: FailUnimpl::array16(); 852 0x14: FailUnimpl::array32(); 853 0x18: BasicOperate::alignaddr({{ 854 uint64_t sum = Rs1 + Rs2; 855 Rd = sum & ~7; 856 Gsr = (Gsr & ~7) | (sum & 7); 857 }}); 858 0x19: FailUnimpl::bmask(); 859 0x1A: BasicOperate::alignaddresslittle({{ 860 uint64_t sum = Rs1 + Rs2; 861 Rd = sum & ~7; 862 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 863 }}); 864 0x20: FailUnimpl::fcmple16(); 865 0x22: FailUnimpl::fcmpne16(); 866 0x24: FailUnimpl::fcmple32(); 867 0x26: FailUnimpl::fcmpne32(); 868 0x28: FailUnimpl::fcmpgt16(); 869 0x2A: FailUnimpl::fcmpeq16(); 870 0x2C: FailUnimpl::fcmpgt32(); 871 0x2E: FailUnimpl::fcmpeq32(); 872 0x31: FailUnimpl::fmul8x16(); 873 0x33: FailUnimpl::fmul8x16au(); 874 0x35: FailUnimpl::fmul8x16al(); 875 0x36: FailUnimpl::fmul8sux16(); 876 0x37: FailUnimpl::fmul8ulx16(); 877 0x38: FailUnimpl::fmuld8sux16(); 878 0x39: FailUnimpl::fmuld8ulx16(); 879 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 880 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 881 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 882 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 883 0x48: BasicOperate::faligndata({{ 884 uint64_t msbX = Frs1.udw; 885 uint64_t lsbX = Frs2.udw; 886 //Some special cases need to be split out, first 887 //because they're the most likely to be used, and 888 //second because otherwise, we end up shifting by 889 //greater than the width of the type being shifted, 890 //namely 64, which produces undefined results according 891 //to the C standard. 892 switch(Gsr<2:0>) 893 { 894 case 0: 895 Frd.udw = msbX; 896 break; 897 case 8: 898 Frd.udw = lsbX; 899 break; 900 default: 901 uint64_t msbShift = Gsr<2:0> * 8; 902 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 903 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 904 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 905 Frd.udw = ((msbX & msbMask) << msbShift) | 906 ((lsbX & lsbMask) >> lsbShift); 907 } 908 }}); 909 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 910 0x4C: FailUnimpl::bshuffle(); 911 0x4D: FailUnimpl::fexpand(); 912 0x50: FailUnimpl::fpadd16(); 913 0x51: FailUnimpl::fpadd16s(); 914 0x52: FailUnimpl::fpadd32(); 915 0x53: FailUnimpl::fpadd32s(); 916 0x54: FailUnimpl::fpsub16(); 917 0x55: FailUnimpl::fpsub16s(); 918 0x56: FailUnimpl::fpsub32(); 919 0x57: FailUnimpl::fpsub32s(); 920 0x60: FpBasic::fzero({{Frd.df = 0;}}); 921 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 922 0x62: FailUnimpl::fnor(); 923 0x63: FailUnimpl::fnors(); 924 0x64: FailUnimpl::fandnot2(); 925 0x65: FailUnimpl::fandnot2s(); 926 0x66: FpBasic::fnot2({{ 927 Frd.df = (double)(~((uint64_t)Frs2.df)); 928 }}); 929 0x67: FpBasic::fnot2s({{ 930 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 931 }}); 932 0x68: FailUnimpl::fandnot1(); 933 0x69: FailUnimpl::fandnot1s(); 934 0x6A: FpBasic::fnot1({{ 935 Frd.df = (double)(~((uint64_t)Frs1.df)); 936 }}); 937 0x6B: FpBasic::fnot1s({{ 938 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 939 }}); 940 0x6C: FailUnimpl::fxor(); 941 0x6D: FailUnimpl::fxors(); 942 0x6E: FailUnimpl::fnand(); 943 0x6F: FailUnimpl::fnands(); 944 0x70: FailUnimpl::fand(); 945 0x71: FailUnimpl::fands(); 946 0x72: FailUnimpl::fxnor(); 947 0x73: FailUnimpl::fxnors(); 948 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 949 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 950 0x76: FailUnimpl::fornot2(); 951 0x77: FailUnimpl::fornot2s(); 952 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 953 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 954 0x7A: FailUnimpl::fornot1(); 955 0x7B: FailUnimpl::fornot1s(); 956 0x7C: FailUnimpl::for(); 957 0x7D: FailUnimpl::fors(); 958 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 959 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 960 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 961 0x81: FailUnimpl::siam(); 962 } 963 // M5 special opcodes use the reserved IMPDEP2A opcode space 964 0x37: decode M5FUNC { 965#if FULL_SYSTEM 966 format BasicOperate { 967 // we have 7 bits of space here to play with... 968 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 969 }}, No_OpClass, IsNonSpeculative); 970 0x50: m5readfile({{ 971 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 972 }}, IsNonSpeculative); 973 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 974 }}, IsNonSpeculative); 975 0x54: m5panic({{ 976 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 977 }}, No_OpClass, IsNonSpeculative); 978 } 979#endif 980 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 981 } 982 0x38: Branch::jmpl({{ 983 Addr target = Rs1 + Rs2_or_imm13; 984 if(target & 0x3) 985 fault = new MemAddressNotAligned; 986 else 987 { 988 if (Pstate<3:>) 989 Rd = (xc->readPC())<31:0>; 990 else 991 Rd = xc->readPC(); 992 NNPC = target; 993 } 994 }}); 995 0x39: Branch::return({{ 996 Addr target = Rs1 + Rs2_or_imm13; 997 if(fault == NoFault) 998 { 999 //Check for fills which are higher priority than alignment 1000 //faults. 1001 if(Canrestore == 0) 1002 { 1003 if(Otherwin) 1004 fault = new FillNOther(4*Wstate<5:3>); 1005 else 1006 fault = new FillNNormal(4*Wstate<2:0>); 1007 } 1008 //Check for alignment faults 1009 else if(target & 0x3) 1010 fault = new MemAddressNotAligned; 1011 else 1012 { 1013 NNPC = target; 1014 Cwp = (Cwp - 1 + NWindows) % NWindows; 1015 Cansave = Cansave + 1; 1016 Canrestore = Canrestore - 1; 1017 } 1018 } 1019 }}); 1020 0x3A: decode CC 1021 { 1022 0x0: Trap::tcci({{ 1023 if(passesCondition(Ccr<3:0>, COND2)) 1024 { 1025 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1026 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1027 fault = new TrapInstruction(lTrapNum); 1028 } 1029 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1030 0x2: Trap::tccx({{ 1031 if(passesCondition(Ccr<7:4>, COND2)) 1032 { 1033 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1034 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1035 fault = new TrapInstruction(lTrapNum); 1036 } 1037 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1038 } 1039 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1040 MemWriteOp); 1041 0x3C: save({{ 1042 if(Cansave == 0) 1043 { 1044 if(Otherwin) 1045 fault = new SpillNOther(4*Wstate<5:3>); 1046 else 1047 fault = new SpillNNormal(4*Wstate<2:0>); 1048 } 1049 else if(Cleanwin - Canrestore == 0) 1050 { 1051 fault = new CleanWindow; 1052 } 1053 else 1054 { 1055 Cwp = (Cwp + 1) % NWindows; 1056 Rd_next = Rs1 + Rs2_or_imm13; 1057 Cansave = Cansave - 1; 1058 Canrestore = Canrestore + 1; 1059 } 1060 }}); 1061 0x3D: restore({{ 1062 if(Canrestore == 0) 1063 { 1064 if(Otherwin) 1065 fault = new FillNOther(4*Wstate<5:3>); 1066 else 1067 fault = new FillNNormal(4*Wstate<2:0>); 1068 } 1069 else 1070 { 1071 Cwp = (Cwp - 1 + NWindows) % NWindows; 1072 Rd_prev = Rs1 + Rs2_or_imm13; 1073 Cansave = Cansave + 1; 1074 Canrestore = Canrestore - 1; 1075 } 1076 }}); 1077 0x3E: decode FCN { 1078 0x0: Priv::done({{ 1079 Cwp = Tstate<4:0>; 1080 Pstate = Tstate<20:8>; 1081 Asi = Tstate<31:24>; 1082 Ccr = Tstate<39:32>; 1083 Gl = Tstate<42:40>; 1084 Hpstate = Htstate; 1085 NPC = Tnpc; 1086 NNPC = Tnpc + 4; 1087 Tl = Tl - 1; 1088 }}, checkTl=true); 1089 0x1: Priv::retry({{ 1090 Cwp = Tstate<4:0>; 1091 Pstate = Tstate<20:8>; 1092 Asi = Tstate<31:24>; 1093 Ccr = Tstate<39:32>; 1094 Gl = Tstate<42:40>; 1095 Hpstate = Htstate; 1096 NPC = Tpc; 1097 NNPC = Tnpc; 1098 Tl = Tl - 1; 1099 }}, checkTl=true); 1100 } 1101 } 1102 } 1103 0x3: decode OP3 { 1104 format Load { 1105 0x00: lduw({{Rd = Mem.uw;}}); 1106 0x01: ldub({{Rd = Mem.ub;}}); 1107 0x02: lduh({{Rd = Mem.uhw;}}); 1108 0x03: ldtw({{ 1109 RdLow = (Mem.tuw).a; 1110 RdHigh = (Mem.tuw).b; 1111 }}); 1112 } 1113 format Store { 1114 0x04: stw({{Mem.uw = Rd.sw;}}); 1115 0x05: stb({{Mem.ub = Rd.sb;}}); 1116 0x06: sth({{Mem.uhw = Rd.shw;}}); 1117 0x07: sttw({{ 1118 //This temporary needs to be here so that the parser 1119 //will correctly identify this instruction as a store. 1120 //It's probably either the parenthesis or referencing 1121 //the member variable that throws confuses it. 1122 Twin32_t temp; 1123 temp.a = RdLow<31:0>; 1124 temp.b = RdHigh<31:0>; 1125 Mem.tuw = temp; 1126 }}); 1127 } 1128 format Load { 1129 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1130 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1131 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1132 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1133 } 1134 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1135 {{ 1136 uint8_t tmp = mem_data; 1137 Rd.ub = tmp; 1138 }}, MEM_SWAP); 1139 0x0E: Store::stx({{Mem.udw = Rd}}); 1140 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1141 {{ 1142 uint32_t tmp = mem_data; 1143 Rd.uw = tmp; 1144 }}, MEM_SWAP); 1145 format LoadAlt { 1146 0x10: lduwa({{Rd = Mem.uw;}}); 1147 0x11: lduba({{Rd = Mem.ub;}}); 1148 0x12: lduha({{Rd = Mem.uhw;}}); 1149 0x13: decode EXT_ASI { 1150 //ASI_LDTD_AIUP 1151 0x22: TwinLoad::ldtx_aiup( 1152 {{RdLow.udw = (Mem.tudw).a; 1153 RdHigh.udw = (Mem.tudw).b;}}); 1154 //ASI_LDTD_AIUS 1155 0x23: TwinLoad::ldtx_aius( 1156 {{RdLow.udw = (Mem.tudw).a; 1157 RdHigh.udw = (Mem.tudw).b;}}); 1158 //ASI_QUAD_LDD 1159 0x24: TwinLoad::ldtx_quad_ldd( 1160 {{RdLow.udw = (Mem.tudw).a; 1161 RdHigh.udw = (Mem.tudw).b;}}); 1162 //ASI_LDTX_REAL 1163 0x26: TwinLoad::ldtx_real( 1164 {{RdLow.udw = (Mem.tudw).a; 1165 RdHigh.udw = (Mem.tudw).b;}}); 1166 //ASI_LDTX_N 1167 0x27: TwinLoad::ldtx_n( 1168 {{RdLow.udw = (Mem.tudw).a; 1169 RdHigh.udw = (Mem.tudw).b;}}); 1170 //ASI_LDTX_AIUP_L 1171 0x2A: TwinLoad::ldtx_aiup_l( 1172 {{RdLow.udw = (Mem.tudw).a; 1173 RdHigh.udw = (Mem.tudw).b;}}); 1174 //ASI_LDTX_AIUS_L 1175 0x2B: TwinLoad::ldtx_aius_l( 1176 {{RdLow.udw = (Mem.tudw).a; 1177 RdHigh.udw = (Mem.tudw).b;}}); 1178 //ASI_LDTX_L 1179 0x2C: TwinLoad::ldtx_l( 1180 {{RdLow.udw = (Mem.tudw).a; 1181 RdHigh.udw = (Mem.tudw).b;}}); 1182 //ASI_LDTX_REAL_L 1183 0x2E: TwinLoad::ldtx_real_l( 1184 {{RdLow.udw = (Mem.tudw).a; 1185 RdHigh.udw = (Mem.tudw).b;}}); 1186 //ASI_LDTX_N_L 1187 0x2F: TwinLoad::ldtx_n_l( 1188 {{RdLow.udw = (Mem.tudw).a; 1189 RdHigh.udw = (Mem.tudw).b;}}); 1190 //ASI_LDTX_P 1191 0xE2: TwinLoad::ldtx_p( 1192 {{RdLow.udw = (Mem.tudw).a; 1193 RdHigh.udw = (Mem.tudw).b;}}); 1194 //ASI_LDTX_S 1195 0xE3: TwinLoad::ldtx_s( 1196 {{RdLow.udw = (Mem.tudw).a; 1197 RdHigh.udw = (Mem.tudw).b;}}); 1198 //ASI_LDTX_PL 1199 0xEA: TwinLoad::ldtx_pl( 1200 {{RdLow.udw = (Mem.tudw).a; 1201 RdHigh.udw = (Mem.tudw).b;}}); 1202 //ASI_LDTX_SL 1203 0xEB: TwinLoad::ldtx_sl( 1204 {{RdLow.udw = (Mem.tudw).a; 1205 RdHigh.udw = (Mem.tudw).b;}}); 1206 default: ldtwa({{ 1207 RdLow = (Mem.tuw).a; 1208 RdHigh = (Mem.tuw).b;}}); 1209 } 1210 } 1211 format StoreAlt { 1212 0x14: stwa({{Mem.uw = Rd;}}); 1213 0x15: stba({{Mem.ub = Rd;}}); 1214 0x16: stha({{Mem.uhw = Rd;}}); 1215 0x17: sttwa({{ 1216 //This temporary needs to be here so that the parser 1217 //will correctly identify this instruction as a store. 1218 //It's probably either the parenthesis or referencing 1219 //the member variable that throws confuses it. 1220 Twin32_t temp; 1221 temp.a = RdLow<31:0>; 1222 temp.b = RdHigh<31:0>; 1223 Mem.tuw = temp; 1224 }}); 1225 } 1226 format LoadAlt { 1227 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1228 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1229 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1230 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 1231 } 1232 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1233 {{ 1234 uint8_t tmp = mem_data; 1235 Rd.ub = tmp; 1236 }}, MEM_SWAP); 1237 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 1238 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1239 {{ 1240 uint32_t tmp = mem_data; 1241 Rd.uw = tmp; 1242 }}, MEM_SWAP); 1243 1244 format Trap { 1245 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1246 0x21: decode RD { 1247 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1248 if (fault) 1249 return fault; 1250 Fsr = Mem.uw | Fsr<63:32>;}}); 1251 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1252 if (fault) 1253 return fault; 1254 Fsr = Mem.udw;}}); 1255 default: FailUnimpl::ldfsrOther(); 1256 } 1257 0x22: ldqf({{fault = new FpDisabled;}}); 1258 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1259 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1260 0x25: decode RD { 1261 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 1262 if (fault) 1263 return fault; 1264 Mem.uw = Fsr<31:0>;}}); 1265 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 1266 if (fault) 1267 return fault; 1268 Mem.udw = Fsr;}}); 1269 default: FailUnimpl::stfsrOther(); 1270 } 1271 0x26: stqf({{fault = new FpDisabled;}}); 1272 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1273 0x2D: Nop::prefetch({{ }}); 1274 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 1275 0x32: ldqfa({{fault = new FpDisabled;}}); 1276 format LoadAlt { 1277 0x33: decode EXT_ASI { 1278 //ASI_NUCLEUS 1279 0x04: FailUnimpl::lddfa_n(); 1280 //ASI_NUCLEUS_LITTLE 1281 0x0C: FailUnimpl::lddfa_nl(); 1282 //ASI_AS_IF_USER_PRIMARY 1283 0x10: FailUnimpl::lddfa_aiup(); 1284 //ASI_AS_IF_USER_PRIMARY_LITTLE 1285 0x18: FailUnimpl::lddfa_aiupl(); 1286 //ASI_AS_IF_USER_SECONDARY 1287 0x11: FailUnimpl::lddfa_aius(); 1288 //ASI_AS_IF_USER_SECONDARY_LITTLE 1289 0x19: FailUnimpl::lddfa_aiusl(); 1290 //ASI_REAL 1291 0x14: FailUnimpl::lddfa_real(); 1292 //ASI_REAL_LITTLE 1293 0x1C: FailUnimpl::lddfa_real_l(); 1294 //ASI_REAL_IO 1295 0x15: FailUnimpl::lddfa_real_io(); 1296 //ASI_REAL_IO_LITTLE 1297 0x1D: FailUnimpl::lddfa_real_io_l(); 1298 //ASI_PRIMARY 1299 0x80: FailUnimpl::lddfa_p(); 1300 //ASI_PRIMARY_LITTLE 1301 0x88: FailUnimpl::lddfa_pl(); 1302 //ASI_SECONDARY 1303 0x81: FailUnimpl::lddfa_s(); 1304 //ASI_SECONDARY_LITTLE 1305 0x89: FailUnimpl::lddfa_sl(); 1306 //ASI_PRIMARY_NO_FAULT 1307 0x82: FailUnimpl::lddfa_pnf(); 1308 //ASI_PRIMARY_NO_FAULT_LITTLE 1309 0x8A: FailUnimpl::lddfa_pnfl(); 1310 //ASI_SECONDARY_NO_FAULT 1311 0x83: FailUnimpl::lddfa_snf(); 1312 //ASI_SECONDARY_NO_FAULT_LITTLE 1313 0x8B: FailUnimpl::lddfa_snfl(); 1314 1315 format BlockLoad { 1316 // LDBLOCKF 1317 //ASI_BLOCK_AS_IF_USER_PRIMARY 1318 0x16: FailUnimpl::ldblockf_aiup(); 1319 //ASI_BLOCK_AS_IF_USER_SECONDARY 1320 0x17: FailUnimpl::ldblockf_aius(); 1321 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1322 0x1E: FailUnimpl::ldblockf_aiupl(); 1323 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1324 0x1F: FailUnimpl::ldblockf_aiusl(); 1325 //ASI_BLOCK_PRIMARY 1326 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 1327 //ASI_BLOCK_SECONDARY 1328 0xF1: FailUnimpl::ldblockf_s(); 1329 //ASI_BLOCK_PRIMARY_LITTLE 1330 0xF8: FailUnimpl::ldblockf_pl(); 1331 //ASI_BLOCK_SECONDARY_LITTLE 1332 0xF9: FailUnimpl::ldblockf_sl(); 1333 } 1334 1335 //LDSHORTF 1336 //ASI_FL8_PRIMARY 1337 0xD0: FailUnimpl::ldshortf_8p(); 1338 //ASI_FL8_SECONDARY 1339 0xD1: FailUnimpl::ldshortf_8s(); 1340 //ASI_FL8_PRIMARY_LITTLE 1341 0xD8: FailUnimpl::ldshortf_8pl(); 1342 //ASI_FL8_SECONDARY_LITTLE 1343 0xD9: FailUnimpl::ldshortf_8sl(); 1344 //ASI_FL16_PRIMARY 1345 0xD2: FailUnimpl::ldshortf_16p(); 1346 //ASI_FL16_SECONDARY 1347 0xD3: FailUnimpl::ldshortf_16s(); 1348 //ASI_FL16_PRIMARY_LITTLE 1349 0xDA: FailUnimpl::ldshortf_16pl(); 1350 //ASI_FL16_SECONDARY_LITTLE 1351 0xDB: FailUnimpl::ldshortf_16sl(); 1352 //Not an ASI which is legal with lddfa 1353 default: Trap::lddfa_bad_asi( 1354 {{fault = new DataAccessException;}}); 1355 } 1356 } 1357 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1358 0x36: stqfa({{fault = new FpDisabled;}}); 1359 format StoreAlt { 1360 0x37: decode EXT_ASI { 1361 //ASI_NUCLEUS 1362 0x04: FailUnimpl::stdfa_n(); 1363 //ASI_NUCLEUS_LITTLE 1364 0x0C: FailUnimpl::stdfa_nl(); 1365 //ASI_AS_IF_USER_PRIMARY 1366 0x10: FailUnimpl::stdfa_aiup(); 1367 //ASI_AS_IF_USER_PRIMARY_LITTLE 1368 0x18: FailUnimpl::stdfa_aiupl(); 1369 //ASI_AS_IF_USER_SECONDARY 1370 0x11: FailUnimpl::stdfa_aius(); 1371 //ASI_AS_IF_USER_SECONDARY_LITTLE 1372 0x19: FailUnimpl::stdfa_aiusl(); 1373 //ASI_REAL 1374 0x14: FailUnimpl::stdfa_real(); 1375 //ASI_REAL_LITTLE 1376 0x1C: FailUnimpl::stdfa_real_l(); 1377 //ASI_REAL_IO 1378 0x15: FailUnimpl::stdfa_real_io(); 1379 //ASI_REAL_IO_LITTLE 1380 0x1D: FailUnimpl::stdfa_real_io_l(); 1381 //ASI_PRIMARY 1382 0x80: FailUnimpl::stdfa_p(); 1383 //ASI_PRIMARY_LITTLE 1384 0x88: FailUnimpl::stdfa_pl(); 1385 //ASI_SECONDARY 1386 0x81: FailUnimpl::stdfa_s(); 1387 //ASI_SECONDARY_LITTLE 1388 0x89: FailUnimpl::stdfa_sl(); 1389 //ASI_PRIMARY_NO_FAULT 1390 0x82: FailUnimpl::stdfa_pnf(); 1391 //ASI_PRIMARY_NO_FAULT_LITTLE 1392 0x8A: FailUnimpl::stdfa_pnfl(); 1393 //ASI_SECONDARY_NO_FAULT 1394 0x83: FailUnimpl::stdfa_snf(); 1395 //ASI_SECONDARY_NO_FAULT_LITTLE 1396 0x8B: FailUnimpl::stdfa_snfl(); 1397 1398 format BlockStore { 1399 // STBLOCKF 1400 //ASI_BLOCK_AS_IF_USER_PRIMARY 1401 0x16: FailUnimpl::stblockf_aiup(); 1402 //ASI_BLOCK_AS_IF_USER_SECONDARY 1403 0x17: FailUnimpl::stblockf_aius(); 1404 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1405 0x1E: FailUnimpl::stblockf_aiupl(); 1406 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1407 0x1F: FailUnimpl::stblockf_aiusl(); 1408 //ASI_BLOCK_PRIMARY 1409 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1410 //ASI_BLOCK_SECONDARY 1411 0xF1: FailUnimpl::stblockf_s(); 1412 //ASI_BLOCK_PRIMARY_LITTLE 1413 0xF8: FailUnimpl::stblockf_pl(); 1414 //ASI_BLOCK_SECONDARY_LITTLE 1415 0xF9: FailUnimpl::stblockf_sl(); 1416 } 1417 1418 //STSHORTF 1419 //ASI_FL8_PRIMARY 1420 0xD0: FailUnimpl::stshortf_8p(); 1421 //ASI_FL8_SECONDARY 1422 0xD1: FailUnimpl::stshortf_8s(); 1423 //ASI_FL8_PRIMARY_LITTLE 1424 0xD8: FailUnimpl::stshortf_8pl(); 1425 //ASI_FL8_SECONDARY_LITTLE 1426 0xD9: FailUnimpl::stshortf_8sl(); 1427 //ASI_FL16_PRIMARY 1428 0xD2: FailUnimpl::stshortf_16p(); 1429 //ASI_FL16_SECONDARY 1430 0xD3: FailUnimpl::stshortf_16s(); 1431 //ASI_FL16_PRIMARY_LITTLE 1432 0xDA: FailUnimpl::stshortf_16pl(); 1433 //ASI_FL16_SECONDARY_LITTLE 1434 0xDB: FailUnimpl::stshortf_16sl(); 1435 //Not an ASI which is legal with lddfa 1436 default: Trap::stdfa_bad_asi( 1437 {{fault = new DataAccessException;}}); 1438 } 1439 } 1440 0x3C: CasAlt::casa({{ 1441 mem_data = htog(Rs2.uw); 1442 Mem.uw = Rd.uw;}}, 1443 {{ 1444 uint32_t tmp = mem_data; 1445 Rd.uw = tmp; 1446 }}, MEM_SWAP_COND); 1447 0x3D: Nop::prefetcha({{ }}); 1448 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1449 Mem.udw = Rd.udw; }}, 1450 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 1451 } 1452 } 1453} 1454