decoder.isa revision 6639
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: bpa(19, annul_code={{ 49 NPC = xc->readPC() + disp; 50 NNPC = NPC + 4; 51 }}); 52 //Branch Never 53 0x0: bpn(19, {{;}}, 54 annul_code={{ 55 NNPC = NPC + 8; 56 NPC = NPC + 4; 57 }}); 58 default: decode BPCC 59 { 60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 62 } 63 } 64 //bicc 65 0x2: decode COND2 66 { 67 //Branch Always 68 0x8: ba(22, annul_code={{ 69 NPC = xc->readPC() + disp; 70 NNPC = NPC + 4; 71 }}); 72 //Branch Never 73 0x0: bn(22, {{;}}, 74 annul_code={{ 75 NNPC = NPC + 8; 76 NPC = NPC + 4; 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { 85 0x1: bpreq(test={{Rs1.sdw == 0}}); 86 0x2: bprle(test={{Rs1.sdw <= 0}}); 87 0x3: bprl(test={{Rs1.sdw < 0}}); 88 0x5: bprne(test={{Rs1.sdw != 0}}); 89 0x6: bprg(test={{Rs1.sdw > 0}}); 90 0x7: bprge(test={{Rs1.sdw >= 0}}); 91 } 92 } 93 //SETHI (or NOP if rd == 0 and imm == 0) 94 0x4: SetHi::sethi({{Rd.udw = imm;}}); 95 //fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 //Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = xc->readPC() + disp; 101 NNPC = NPC + 4; 102 }}); 103 //Branch Never 104 0x0: fbpn(22, {{;}}, 105 annul_code={{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}); 109 default: decode BPCC { 110 0x0: fbpfcc0(19, test= 111 {{passesFpCondition(Fsr<11:10>, COND2)}}); 112 0x1: fbpfcc1(19, test= 113 {{passesFpCondition(Fsr<33:32>, COND2)}}); 114 0x2: fbpfcc2(19, test= 115 {{passesFpCondition(Fsr<35:34>, COND2)}}); 116 0x3: fbpfcc3(19, test= 117 {{passesFpCondition(Fsr<37:36>, COND2)}}); 118 } 119 } 120 } 121 //fbfcc 122 0x6: decode COND2 { 123 format BranchN { 124 //Branch Always 125 0x8: fba(22, annul_code={{ 126 NPC = xc->readPC() + disp; 127 NNPC = NPC + 4; 128 }}); 129 //Branch Never 130 0x0: fbn(22, {{;}}, 131 annul_code={{ 132 NNPC = NPC + 8; 133 NPC = NPC + 4; 134 }}); 135 default: fbfcc(22, test= 136 {{passesFpCondition(Fsr<11:10>, COND2)}}); 137 } 138 } 139 } 140 0x1: BranchN::call(30, {{ 141 if (Pstate<3:>) 142 R15 = (xc->readPC())<31:0>; 143 else 144 R15 = xc->readPC(); 145 NNPC = R15 + disp; 146 }}); 147 0x2: decode OP3 { 148 format IntOp { 149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 154 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 155 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 156 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 157 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 158 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 159 0x0A: umul({{ 160 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 161 Y = Rd<63:32>; 162 }}); 163 0x0B: smul({{ 164 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 165 Y = Rd.sdw<63:32>; 166 }}); 167 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 168 0x0D: udivx({{ 169 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 170 else Rd.udw = Rs1.udw / Rs2_or_imm13; 171 }}); 172 0x0E: udiv({{ 173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 174 else 175 { 176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 177 if(Rd.udw >> 32 != 0) 178 Rd.udw = 0xFFFFFFFF; 179 } 180 }}); 181 0x0F: sdiv({{ 182 if(Rs2_or_imm13.sdw == 0) 183 fault = new DivisionByZero; 184 else 185 { 186 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 187 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 188 Rd.udw = 0x7FFFFFFF; 189 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 190 Rd.udw = ULL(0xFFFFFFFF80000000); 191 } 192 }}); 193 } 194 format IntOpCc { 195 0x10: addcc({{ 196 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 197 Rd = res = op1 + op2; 198 }}); 199 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 200 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 201 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 202 0x14: subcc({{ 203 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 204 Rd = res = op1 - op2; 205 }}, sub=True); 206 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 207 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 208 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 209 0x18: addccc({{ 210 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 211 Rd = res = op1 + op2 + Ccr<0:>; 212 }}); 213 0x1A: IntOpCcRes::umulcc({{ 214 uint64_t resTemp; 215 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 216 Y = resTemp<63:32>;}}); 217 0x1B: IntOpCcRes::smulcc({{ 218 int64_t resTemp; 219 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 220 Y = resTemp<63:32>;}}); 221 0x1C: subccc({{ 222 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 223 Rd = res = op1 - op2 - Ccr<0:>; 224 }}, sub=True); 225 0x1D: IntOpCcRes::udivxcc({{ 226 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 227 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 228 0x1E: IntOpCcRes::udivcc({{ 229 uint64_t resTemp; 230 uint32_t val2 = Rs2_or_imm13.udw; 231 int32_t overflow = 0; 232 if(val2 == 0) fault = new DivisionByZero; 233 else 234 { 235 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 236 overflow = (resTemp<63:32> != 0); 237 if(overflow) Rd = resTemp = 0xFFFFFFFF; 238 else Rd = resTemp; 239 } 240 }}, iv={{overflow}}); 241 0x1F: IntOpCcRes::sdivcc({{ 242 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 243 bool overflow = false, underflow = false; 244 if(val2 == 0) fault = new DivisionByZero; 245 else 246 { 247 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 248 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 249 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 250 if(overflow) Rd = 0x7FFFFFFF; 251 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 252 } 253 }}, iv={{overflow || underflow}}); 254 0x20: taddcc({{ 255 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 256 Rd = res = Rs1 + op2; 257 }}, iv={{ 258 (op1 & mask(2)) || (op2 & mask(2)) || 259 findOverflow(32, res, op1, op2) 260 }}); 261 0x21: tsubcc({{ 262 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 263 Rd = res = Rs1 - op2; 264 }}, iv={{ 265 (op1 & mask(2)) || (op2 & mask(2)) || 266 findOverflow(32, res, op1, ~op2) 267 }}, sub=True); 268 0x22: taddcctv({{ 269 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 270 Rd = res = op1 + op2; 271 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 272 findOverflow(32, res, op1, op2); 273 if(overflow) fault = new TagOverflow; 274 }}, iv={{overflow}}); 275 0x23: tsubcctv({{ 276 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 277 Rd = res = op1 - op2; 278 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 279 findOverflow(32, res, op1, ~op2); 280 if(overflow) fault = new TagOverflow; 281 }}, iv={{overflow}}, sub=True); 282 0x24: mulscc({{ 283 int32_t savedLSB = Rs1<0:>; 284 285 //Step 1 286 int64_t multiplicand = Rs2_or_imm13; 287 //Step 2 288 int32_t partialP = Rs1<31:1> | 289 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 290 //Step 3 291 int32_t added = Y<0:> ? multiplicand : 0; 292 int64_t res, op1 = partialP, op2 = added; 293 Rd = res = partialP + added; 294 //Steps 4 & 5 295 Y = Y<31:1> | (savedLSB << 31); 296 }}); 297 } 298 format IntOp 299 { 300 0x25: decode X { 301 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 302 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 303 } 304 0x26: decode X { 305 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 306 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 307 } 308 0x27: decode X { 309 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 310 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 311 } 312 0x28: decode RS1 { 313 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 314 //1 should cause an illegal instruction exception 315 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 316 0x03: NoPriv::rdasi({{Rd = Asi;}}); 317 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 318 0x05: NoPriv::rdpc({{ 319 if(Pstate<3:>) 320 Rd = (xc->readPC())<31:0>; 321 else 322 Rd = xc->readPC();}}); 323 0x06: NoPriv::rdfprs({{ 324 //Wait for all fpops to finish. 325 Rd = Fprs; 326 }}); 327 //7-14 should cause an illegal instruction exception 328 0x0F: decode I { 329 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 330 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 331 } 332 0x10: Priv::rdpcr({{Rd = Pcr;}}); 333 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 334 //0x12 should cause an illegal instruction exception 335 0x13: NoPriv::rdgsr({{ 336 fault = checkFpEnableFault(xc); 337 if (fault) 338 return fault; 339 Rd = Gsr; 340 }}); 341 //0x14-0x15 should cause an illegal instruction exception 342 0x16: Priv::rdsoftint({{Rd = Softint;}}); 343 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 344 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 345 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 346 0x1A: Priv::rdstrand_sts_reg({{ 347 if(Pstate<2:> && !Hpstate<2:>) 348 Rd = StrandStsReg<0:>; 349 else 350 Rd = StrandStsReg; 351 }}); 352 //0x1A is supposed to be reserved, but it reads the strand 353 //status register. 354 //0x1B-0x1F should cause an illegal instruction exception 355 } 356 0x29: decode RS1 { 357 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 358 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 359 //0x02 should cause an illegal instruction exception 360 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 361 //0x04 should cause an illegal instruction exception 362 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 363 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 364 //0x07-0x1E should cause an illegal instruction exception 365 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 366 } 367 0x2A: decode RS1 { 368 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 369 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 370 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 371 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 372 0x04: Priv::rdprtick({{Rd = Tick;}}); 373 0x05: Priv::rdprtba({{Rd = Tba;}}); 374 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 375 0x07: Priv::rdprtl({{Rd = Tl;}}); 376 0x08: Priv::rdprpil({{Rd = Pil;}}); 377 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 378 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 379 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 380 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 381 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 382 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 383 //0x0F should cause an illegal instruction exception 384 0x10: Priv::rdprgl({{Rd = Gl;}}); 385 //0x11-0x1F should cause an illegal instruction exception 386 } 387 0x2B: BasicOperate::flushw({{ 388 if(NWindows - 2 - Cansave != 0) 389 { 390 if(Otherwin) 391 fault = new SpillNOther(4*Wstate<5:3>); 392 else 393 fault = new SpillNNormal(4*Wstate<2:0>); 394 } 395 }}); 396 0x2C: decode MOVCC3 397 { 398 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 399 0x1: decode CC 400 { 401 0x0: movcci({{ 402 if(passesCondition(Ccr<3:0>, COND4)) 403 Rd = Rs2_or_imm11; 404 else 405 Rd = Rd; 406 }}); 407 0x2: movccx({{ 408 if(passesCondition(Ccr<7:4>, COND4)) 409 Rd = Rs2_or_imm11; 410 else 411 Rd = Rd; 412 }}); 413 } 414 } 415 0x2D: sdivx({{ 416 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 417 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 418 }}); 419 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 420 0x2F: decode RCOND3 421 { 422 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 423 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 424 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 425 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 426 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 427 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 428 } 429 0x30: decode RD { 430 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 431 //0x01 should cause an illegal instruction exception 432 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 433 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 434 //0x04-0x05 should cause an illegal instruction exception 435 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 436 //0x07-0x0E should cause an illegal instruction exception 437 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 438 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 439 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 440 //0x12 should cause an illegal instruction exception 441 0x13: NoPriv::wrgsr({{ 442 if(Fprs<2:> == 0 || Pstate<4:> == 0) 443 return new FpDisabled; 444 Gsr = Rs1 ^ Rs2_or_imm13; 445 }}); 446 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 447 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 448 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 449 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 450 0x18: NoPriv::wrstick({{ 451 if(!Hpstate<2:>) 452 return new IllegalInstruction; 453 Stick = Rs1 ^ Rs2_or_imm13; 454 }}); 455 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 456 0x1A: Priv::wrstrand_sts_reg({{ 457 StrandStsReg = Rs1 ^ Rs2_or_imm13; 458 }}); 459 //0x1A is supposed to be reserved, but it writes the strand 460 //status register. 461 //0x1B-0x1F should cause an illegal instruction exception 462 } 463 0x31: decode FCN { 464 0x0: Priv::saved({{ 465 assert(Cansave < NWindows - 2); 466 assert(Otherwin || Canrestore); 467 Cansave = Cansave + 1; 468 if(Otherwin == 0) 469 Canrestore = Canrestore - 1; 470 else 471 Otherwin = Otherwin - 1; 472 }}); 473 0x1: Priv::restored({{ 474 assert(Cansave || Otherwin); 475 assert(Canrestore < NWindows - 2); 476 Canrestore = Canrestore + 1; 477 if(Otherwin == 0) 478 Cansave = Cansave - 1; 479 else 480 Otherwin = Otherwin - 1; 481 482 if(Cleanwin < NWindows - 1) 483 Cleanwin = Cleanwin + 1; 484 }}); 485 } 486 0x32: decode RD { 487 0x00: Priv::wrprtpc( 488 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 489 0x01: Priv::wrprtnpc( 490 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 491 0x02: Priv::wrprtstate( 492 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 493 0x03: Priv::wrprtt( 494 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 495 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 496 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 497 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 498 0x07: Priv::wrprtl({{ 499 if(Pstate<2:> && !Hpstate<2:>) 500 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 501 else 502 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 503 }}); 504 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 505 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 506 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 507 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 508 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 509 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 510 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 511 //0x0F should cause an illegal instruction exception 512 0x10: Priv::wrprgl({{ 513 if(Pstate<2:> && !Hpstate<2:>) 514 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 515 else 516 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 517 }}); 518 //0x11-0x1F should cause an illegal instruction exception 519 } 520 0x33: decode RD { 521 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 522 0x01: HPriv::wrhprhtstate( 523 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 524 //0x02 should cause an illegal instruction exception 525 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 526 //0x04 should cause an illegal instruction exception 527 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 528 //0x06-0x01D should cause an illegal instruction exception 529 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 530 } 531 0x34: decode OPF{ 532 format FpBasic{ 533 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 534 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 535 0x03: FpUnimpl::fmovq(); 536 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 537 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 538 0x07: FpUnimpl::fnegq(); 539 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 540 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 541 0x0B: FpUnimpl::fabsq(); 542 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 543 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 544 0x2B: FpUnimpl::fsqrtq(); 545 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 546 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 547 0x43: FpUnimpl::faddq(); 548 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 549 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 550 0x47: FpUnimpl::fsubq(); 551 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 552 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 553 0x4B: FpUnimpl::fmulq(); 554 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 555 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 556 0x4F: FpUnimpl::fdivq(); 557 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 558 0x6E: FpUnimpl::fdmulq(); 559 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 560 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 561 0x83: FpUnimpl::fqtox(); 562 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 563 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 564 0x8C: FpUnimpl::fxtoq(); 565 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 566 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 567 0xC7: FpUnimpl::fqtos(); 568 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 569 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 570 0xCB: FpUnimpl::fqtod(); 571 0xCC: FpUnimpl::fitoq(); 572 0xCD: FpUnimpl::fstoq(); 573 0xCE: FpUnimpl::fdtoq(); 574 0xD1: fstoi({{ 575 Frds.sw = static_cast<int32_t>(Frs2s.sf); 576 float t = Frds.sw; 577 if (t != Frs2s.sf) 578 Fsr = insertBits(Fsr, 4,0, 0x01); 579 }}); 580 0xD2: fdtoi({{ 581 Frds.sw = static_cast<int32_t>(Frs2.df); 582 double t = Frds.sw; 583 if (t != Frs2.df) 584 Fsr = insertBits(Fsr, 4,0, 0x01); 585 }}); 586 0xD3: FpUnimpl::fqtoi(); 587 default: FailUnimpl::fpop1(); 588 } 589 } 590 0x35: decode OPF{ 591 format FpBasic{ 592 0x01: fmovs_fcc0({{ 593 if(passesFpCondition(Fsr<11:10>, COND4)) 594 Frds = Frs2s; 595 else 596 Frds = Frds; 597 }}); 598 0x02: fmovd_fcc0({{ 599 if(passesFpCondition(Fsr<11:10>, COND4)) 600 Frd = Frs2; 601 else 602 Frd = Frd; 603 }}); 604 0x03: FpUnimpl::fmovq_fcc0(); 605 0x25: fmovrsz({{ 606 if(Rs1 == 0) 607 Frds = Frs2s; 608 else 609 Frds = Frds; 610 }}); 611 0x26: fmovrdz({{ 612 if(Rs1 == 0) 613 Frd = Frs2; 614 else 615 Frd = Frd; 616 }}); 617 0x27: FpUnimpl::fmovrqz(); 618 0x41: fmovs_fcc1({{ 619 if(passesFpCondition(Fsr<33:32>, COND4)) 620 Frds = Frs2s; 621 else 622 Frds = Frds; 623 }}); 624 0x42: fmovd_fcc1({{ 625 if(passesFpCondition(Fsr<33:32>, COND4)) 626 Frd = Frs2; 627 else 628 Frd = Frd; 629 }}); 630 0x43: FpUnimpl::fmovq_fcc1(); 631 0x45: fmovrslez({{ 632 if(Rs1 <= 0) 633 Frds = Frs2s; 634 else 635 Frds = Frds; 636 }}); 637 0x46: fmovrdlez({{ 638 if(Rs1 <= 0) 639 Frd = Frs2; 640 else 641 Frd = Frd; 642 }}); 643 0x47: FpUnimpl::fmovrqlez(); 644 0x51: fcmps({{ 645 uint8_t fcc; 646 if(isnan(Frs1s) || isnan(Frs2s)) 647 fcc = 3; 648 else if(Frs1s < Frs2s) 649 fcc = 1; 650 else if(Frs1s > Frs2s) 651 fcc = 2; 652 else 653 fcc = 0; 654 uint8_t firstbit = 10; 655 if(FCMPCC) 656 firstbit = FCMPCC * 2 + 30; 657 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 658 }}); 659 0x52: fcmpd({{ 660 uint8_t fcc; 661 if(isnan(Frs1) || isnan(Frs2)) 662 fcc = 3; 663 else if(Frs1 < Frs2) 664 fcc = 1; 665 else if(Frs1 > Frs2) 666 fcc = 2; 667 else 668 fcc = 0; 669 uint8_t firstbit = 10; 670 if(FCMPCC) 671 firstbit = FCMPCC * 2 + 30; 672 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 673 }}); 674 0x53: FpUnimpl::fcmpq(); 675 0x55: fcmpes({{ 676 uint8_t fcc = 0; 677 if(isnan(Frs1s) || isnan(Frs2s)) 678 fault = new FpExceptionIEEE754; 679 if(Frs1s < Frs2s) 680 fcc = 1; 681 else if(Frs1s > Frs2s) 682 fcc = 2; 683 uint8_t firstbit = 10; 684 if(FCMPCC) 685 firstbit = FCMPCC * 2 + 30; 686 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 687 }}); 688 0x56: fcmped({{ 689 uint8_t fcc = 0; 690 if(isnan(Frs1) || isnan(Frs2)) 691 fault = new FpExceptionIEEE754; 692 if(Frs1 < Frs2) 693 fcc = 1; 694 else if(Frs1 > Frs2) 695 fcc = 2; 696 uint8_t firstbit = 10; 697 if(FCMPCC) 698 firstbit = FCMPCC * 2 + 30; 699 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 700 }}); 701 0x57: FpUnimpl::fcmpeq(); 702 0x65: fmovrslz({{ 703 if(Rs1 < 0) 704 Frds = Frs2s; 705 else 706 Frds = Frds; 707 }}); 708 0x66: fmovrdlz({{ 709 if(Rs1 < 0) 710 Frd = Frs2; 711 else 712 Frd = Frd; 713 }}); 714 0x67: FpUnimpl::fmovrqlz(); 715 0x81: fmovs_fcc2({{ 716 if(passesFpCondition(Fsr<35:34>, COND4)) 717 Frds = Frs2s; 718 else 719 Frds = Frds; 720 }}); 721 0x82: fmovd_fcc2({{ 722 if(passesFpCondition(Fsr<35:34>, COND4)) 723 Frd = Frs2; 724 else 725 Frd = Frd; 726 }}); 727 0x83: FpUnimpl::fmovq_fcc2(); 728 0xA5: fmovrsnz({{ 729 if(Rs1 != 0) 730 Frds = Frs2s; 731 else 732 Frds = Frds; 733 }}); 734 0xA6: fmovrdnz({{ 735 if(Rs1 != 0) 736 Frd = Frs2; 737 else 738 Frd = Frd; 739 }}); 740 0xA7: FpUnimpl::fmovrqnz(); 741 0xC1: fmovs_fcc3({{ 742 if(passesFpCondition(Fsr<37:36>, COND4)) 743 Frds = Frs2s; 744 else 745 Frds = Frds; 746 }}); 747 0xC2: fmovd_fcc3({{ 748 if(passesFpCondition(Fsr<37:36>, COND4)) 749 Frd = Frs2; 750 else 751 Frd = Frd; 752 }}); 753 0xC3: FpUnimpl::fmovq_fcc3(); 754 0xC5: fmovrsgz({{ 755 if(Rs1 > 0) 756 Frds = Frs2s; 757 else 758 Frds = Frds; 759 }}); 760 0xC6: fmovrdgz({{ 761 if(Rs1 > 0) 762 Frd = Frs2; 763 else 764 Frd = Frd; 765 }}); 766 0xC7: FpUnimpl::fmovrqgz(); 767 0xE5: fmovrsgez({{ 768 if(Rs1 >= 0) 769 Frds = Frs2s; 770 else 771 Frds = Frds; 772 }}); 773 0xE6: fmovrdgez({{ 774 if(Rs1 >= 0) 775 Frd = Frs2; 776 else 777 Frd = Frd; 778 }}); 779 0xE7: FpUnimpl::fmovrqgez(); 780 0x101: fmovs_icc({{ 781 if(passesCondition(Ccr<3:0>, COND4)) 782 Frds = Frs2s; 783 else 784 Frds = Frds; 785 }}); 786 0x102: fmovd_icc({{ 787 if(passesCondition(Ccr<3:0>, COND4)) 788 Frd = Frs2; 789 else 790 Frd = Frd; 791 }}); 792 0x103: FpUnimpl::fmovq_icc(); 793 0x181: fmovs_xcc({{ 794 if(passesCondition(Ccr<7:4>, COND4)) 795 Frds = Frs2s; 796 else 797 Frds = Frds; 798 }}); 799 0x182: fmovd_xcc({{ 800 if(passesCondition(Ccr<7:4>, COND4)) 801 Frd = Frs2; 802 else 803 Frd = Frd; 804 }}); 805 0x183: FpUnimpl::fmovq_xcc(); 806 default: FailUnimpl::fpop2(); 807 } 808 } 809 //This used to be just impdep1, but now it's a whole bunch 810 //of instructions 811 0x36: decode OPF{ 812 0x00: FailUnimpl::edge8(); 813 0x01: FailUnimpl::edge8n(); 814 0x02: FailUnimpl::edge8l(); 815 0x03: FailUnimpl::edge8ln(); 816 0x04: FailUnimpl::edge16(); 817 0x05: FailUnimpl::edge16n(); 818 0x06: FailUnimpl::edge16l(); 819 0x07: FailUnimpl::edge16ln(); 820 0x08: FailUnimpl::edge32(); 821 0x09: FailUnimpl::edge32n(); 822 0x0A: FailUnimpl::edge32l(); 823 0x0B: FailUnimpl::edge32ln(); 824 0x10: FailUnimpl::array8(); 825 0x12: FailUnimpl::array16(); 826 0x14: FailUnimpl::array32(); 827 0x18: BasicOperate::alignaddr({{ 828 uint64_t sum = Rs1 + Rs2; 829 Rd = sum & ~7; 830 Gsr = (Gsr & ~7) | (sum & 7); 831 }}); 832 0x19: FailUnimpl::bmask(); 833 0x1A: BasicOperate::alignaddresslittle({{ 834 uint64_t sum = Rs1 + Rs2; 835 Rd = sum & ~7; 836 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 837 }}); 838 0x20: FailUnimpl::fcmple16(); 839 0x22: FailUnimpl::fcmpne16(); 840 0x24: FailUnimpl::fcmple32(); 841 0x26: FailUnimpl::fcmpne32(); 842 0x28: FailUnimpl::fcmpgt16(); 843 0x2A: FailUnimpl::fcmpeq16(); 844 0x2C: FailUnimpl::fcmpgt32(); 845 0x2E: FailUnimpl::fcmpeq32(); 846 0x31: FailUnimpl::fmul8x16(); 847 0x33: FailUnimpl::fmul8x16au(); 848 0x35: FailUnimpl::fmul8x16al(); 849 0x36: FailUnimpl::fmul8sux16(); 850 0x37: FailUnimpl::fmul8ulx16(); 851 0x38: FailUnimpl::fmuld8sux16(); 852 0x39: FailUnimpl::fmuld8ulx16(); 853 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 854 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 855 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 856 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 857 0x48: BasicOperate::faligndata({{ 858 uint64_t msbX = Frs1.udw; 859 uint64_t lsbX = Frs2.udw; 860 //Some special cases need to be split out, first 861 //because they're the most likely to be used, and 862 //second because otherwise, we end up shifting by 863 //greater than the width of the type being shifted, 864 //namely 64, which produces undefined results according 865 //to the C standard. 866 switch(Gsr<2:0>) 867 { 868 case 0: 869 Frd.udw = msbX; 870 break; 871 case 8: 872 Frd.udw = lsbX; 873 break; 874 default: 875 uint64_t msbShift = Gsr<2:0> * 8; 876 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 877 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 878 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 879 Frd.udw = ((msbX & msbMask) << msbShift) | 880 ((lsbX & lsbMask) >> lsbShift); 881 } 882 }}); 883 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 884 0x4C: FailUnimpl::bshuffle(); 885 0x4D: FailUnimpl::fexpand(); 886 0x50: FailUnimpl::fpadd16(); 887 0x51: FailUnimpl::fpadd16s(); 888 0x52: FailUnimpl::fpadd32(); 889 0x53: FailUnimpl::fpadd32s(); 890 0x54: FailUnimpl::fpsub16(); 891 0x55: FailUnimpl::fpsub16s(); 892 0x56: FailUnimpl::fpsub32(); 893 0x57: FailUnimpl::fpsub32s(); 894 0x60: FpBasic::fzero({{Frd.df = 0;}}); 895 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 896 0x62: FailUnimpl::fnor(); 897 0x63: FailUnimpl::fnors(); 898 0x64: FailUnimpl::fandnot2(); 899 0x65: FailUnimpl::fandnot2s(); 900 0x66: FpBasic::fnot2({{ 901 Frd.df = (double)(~((uint64_t)Frs2.df)); 902 }}); 903 0x67: FpBasic::fnot2s({{ 904 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 905 }}); 906 0x68: FailUnimpl::fandnot1(); 907 0x69: FailUnimpl::fandnot1s(); 908 0x6A: FpBasic::fnot1({{ 909 Frd.df = (double)(~((uint64_t)Frs1.df)); 910 }}); 911 0x6B: FpBasic::fnot1s({{ 912 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 913 }}); 914 0x6C: FailUnimpl::fxor(); 915 0x6D: FailUnimpl::fxors(); 916 0x6E: FailUnimpl::fnand(); 917 0x6F: FailUnimpl::fnands(); 918 0x70: FailUnimpl::fand(); 919 0x71: FailUnimpl::fands(); 920 0x72: FailUnimpl::fxnor(); 921 0x73: FailUnimpl::fxnors(); 922 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 923 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 924 0x76: FailUnimpl::fornot2(); 925 0x77: FailUnimpl::fornot2s(); 926 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 927 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 928 0x7A: FailUnimpl::fornot1(); 929 0x7B: FailUnimpl::fornot1s(); 930 0x7C: FailUnimpl::for(); 931 0x7D: FailUnimpl::fors(); 932 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 933 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 934 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 935 0x81: FailUnimpl::siam(); 936 } 937 // M5 special opcodes use the reserved IMPDEP2A opcode space 938 0x37: decode M5FUNC { 939#if FULL_SYSTEM 940 format BasicOperate { 941 // we have 7 bits of space here to play with... 942 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 943 }}, No_OpClass, IsNonSpeculative); 944 0x50: m5readfile({{ 945 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 946 }}, IsNonSpeculative); 947 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 948 }}, IsNonSpeculative); 949 0x54: m5panic({{ 950 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 951 }}, No_OpClass, IsNonSpeculative); 952 } 953#endif 954 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 955 } 956 0x38: Branch::jmpl({{ 957 Addr target = Rs1 + Rs2_or_imm13; 958 if(target & 0x3) 959 fault = new MemAddressNotAligned; 960 else 961 { 962 if (Pstate<3:>) 963 Rd = (xc->readPC())<31:0>; 964 else 965 Rd = xc->readPC(); 966 NNPC = target; 967 } 968 }}); 969 0x39: Branch::return({{ 970 Addr target = Rs1 + Rs2_or_imm13; 971 if(fault == NoFault) 972 { 973 //Check for fills which are higher priority than alignment 974 //faults. 975 if(Canrestore == 0) 976 { 977 if(Otherwin) 978 fault = new FillNOther(4*Wstate<5:3>); 979 else 980 fault = new FillNNormal(4*Wstate<2:0>); 981 } 982 //Check for alignment faults 983 else if(target & 0x3) 984 fault = new MemAddressNotAligned; 985 else 986 { 987 NNPC = target; 988 Cwp = (Cwp - 1 + NWindows) % NWindows; 989 Cansave = Cansave + 1; 990 Canrestore = Canrestore - 1; 991 } 992 } 993 }}); 994 0x3A: decode CC 995 { 996 0x0: Trap::tcci({{ 997 if(passesCondition(Ccr<3:0>, COND2)) 998 { 999 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1000 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1001 fault = new TrapInstruction(lTrapNum); 1002 } 1003 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1004 0x2: Trap::tccx({{ 1005 if(passesCondition(Ccr<7:4>, COND2)) 1006 { 1007 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1008 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1009 fault = new TrapInstruction(lTrapNum); 1010 } 1011 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1012 } 1013 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1014 MemWriteOp); 1015 0x3C: save({{ 1016 if(Cansave == 0) 1017 { 1018 if(Otherwin) 1019 fault = new SpillNOther(4*Wstate<5:3>); 1020 else 1021 fault = new SpillNNormal(4*Wstate<2:0>); 1022 } 1023 else if(Cleanwin - Canrestore == 0) 1024 { 1025 fault = new CleanWindow; 1026 } 1027 else 1028 { 1029 Cwp = (Cwp + 1) % NWindows; 1030 Rd_next = Rs1 + Rs2_or_imm13; 1031 Cansave = Cansave - 1; 1032 Canrestore = Canrestore + 1; 1033 } 1034 }}); 1035 0x3D: restore({{ 1036 if(Canrestore == 0) 1037 { 1038 if(Otherwin) 1039 fault = new FillNOther(4*Wstate<5:3>); 1040 else 1041 fault = new FillNNormal(4*Wstate<2:0>); 1042 } 1043 else 1044 { 1045 Cwp = (Cwp - 1 + NWindows) % NWindows; 1046 Rd_prev = Rs1 + Rs2_or_imm13; 1047 Cansave = Cansave + 1; 1048 Canrestore = Canrestore - 1; 1049 } 1050 }}); 1051 0x3E: decode FCN { 1052 0x0: Priv::done({{ 1053 Cwp = Tstate<4:0>; 1054 Pstate = Tstate<20:8>; 1055 Asi = Tstate<31:24>; 1056 Ccr = Tstate<39:32>; 1057 Gl = Tstate<42:40>; 1058 Hpstate = Htstate; 1059 NPC = Tnpc; 1060 NNPC = Tnpc + 4; 1061 Tl = Tl - 1; 1062 }}, checkTl=true); 1063 0x1: Priv::retry({{ 1064 Cwp = Tstate<4:0>; 1065 Pstate = Tstate<20:8>; 1066 Asi = Tstate<31:24>; 1067 Ccr = Tstate<39:32>; 1068 Gl = Tstate<42:40>; 1069 Hpstate = Htstate; 1070 NPC = Tpc; 1071 NNPC = Tnpc; 1072 Tl = Tl - 1; 1073 }}, checkTl=true); 1074 } 1075 } 1076 } 1077 0x3: decode OP3 { 1078 format Load { 1079 0x00: lduw({{Rd = Mem.uw;}}); 1080 0x01: ldub({{Rd = Mem.ub;}}); 1081 0x02: lduh({{Rd = Mem.uhw;}}); 1082 0x03: ldtw({{ 1083 RdLow = (Mem.tuw).a; 1084 RdHigh = (Mem.tuw).b; 1085 }}); 1086 } 1087 format Store { 1088 0x04: stw({{Mem.uw = Rd.sw;}}); 1089 0x05: stb({{Mem.ub = Rd.sb;}}); 1090 0x06: sth({{Mem.uhw = Rd.shw;}}); 1091 0x07: sttw({{ 1092 //This temporary needs to be here so that the parser 1093 //will correctly identify this instruction as a store. 1094 //It's probably either the parenthesis or referencing 1095 //the member variable that throws confuses it. 1096 Twin32_t temp; 1097 temp.a = RdLow<31:0>; 1098 temp.b = RdHigh<31:0>; 1099 Mem.tuw = temp; 1100 }}); 1101 } 1102 format Load { 1103 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1104 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1105 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1106 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1107 } 1108 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1109 {{ 1110 uint8_t tmp = mem_data; 1111 Rd.ub = tmp; 1112 }}, MEM_SWAP); 1113 0x0E: Store::stx({{Mem.udw = Rd}}); 1114 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1115 {{ 1116 uint32_t tmp = mem_data; 1117 Rd.uw = tmp; 1118 }}, MEM_SWAP); 1119 format LoadAlt { 1120 0x10: lduwa({{Rd = Mem.uw;}}); 1121 0x11: lduba({{Rd = Mem.ub;}}); 1122 0x12: lduha({{Rd = Mem.uhw;}}); 1123 0x13: decode EXT_ASI { 1124 //ASI_LDTD_AIUP 1125 0x22: TwinLoad::ldtx_aiup( 1126 {{RdLow.udw = (Mem.tudw).a; 1127 RdHigh.udw = (Mem.tudw).b;}}); 1128 //ASI_LDTD_AIUS 1129 0x23: TwinLoad::ldtx_aius( 1130 {{RdLow.udw = (Mem.tudw).a; 1131 RdHigh.udw = (Mem.tudw).b;}}); 1132 //ASI_QUAD_LDD 1133 0x24: TwinLoad::ldtx_quad_ldd( 1134 {{RdLow.udw = (Mem.tudw).a; 1135 RdHigh.udw = (Mem.tudw).b;}}); 1136 //ASI_LDTX_REAL 1137 0x26: TwinLoad::ldtx_real( 1138 {{RdLow.udw = (Mem.tudw).a; 1139 RdHigh.udw = (Mem.tudw).b;}}); 1140 //ASI_LDTX_N 1141 0x27: TwinLoad::ldtx_n( 1142 {{RdLow.udw = (Mem.tudw).a; 1143 RdHigh.udw = (Mem.tudw).b;}}); 1144 //ASI_LDTX_AIUP_L 1145 0x2A: TwinLoad::ldtx_aiup_l( 1146 {{RdLow.udw = (Mem.tudw).a; 1147 RdHigh.udw = (Mem.tudw).b;}}); 1148 //ASI_LDTX_AIUS_L 1149 0x2B: TwinLoad::ldtx_aius_l( 1150 {{RdLow.udw = (Mem.tudw).a; 1151 RdHigh.udw = (Mem.tudw).b;}}); 1152 //ASI_LDTX_L 1153 0x2C: TwinLoad::ldtx_l( 1154 {{RdLow.udw = (Mem.tudw).a; 1155 RdHigh.udw = (Mem.tudw).b;}}); 1156 //ASI_LDTX_REAL_L 1157 0x2E: TwinLoad::ldtx_real_l( 1158 {{RdLow.udw = (Mem.tudw).a; 1159 RdHigh.udw = (Mem.tudw).b;}}); 1160 //ASI_LDTX_N_L 1161 0x2F: TwinLoad::ldtx_n_l( 1162 {{RdLow.udw = (Mem.tudw).a; 1163 RdHigh.udw = (Mem.tudw).b;}}); 1164 //ASI_LDTX_P 1165 0xE2: TwinLoad::ldtx_p( 1166 {{RdLow.udw = (Mem.tudw).a; 1167 RdHigh.udw = (Mem.tudw).b;}}); 1168 //ASI_LDTX_S 1169 0xE3: TwinLoad::ldtx_s( 1170 {{RdLow.udw = (Mem.tudw).a; 1171 RdHigh.udw = (Mem.tudw).b;}}); 1172 //ASI_LDTX_PL 1173 0xEA: TwinLoad::ldtx_pl( 1174 {{RdLow.udw = (Mem.tudw).a; 1175 RdHigh.udw = (Mem.tudw).b;}}); 1176 //ASI_LDTX_SL 1177 0xEB: TwinLoad::ldtx_sl( 1178 {{RdLow.udw = (Mem.tudw).a; 1179 RdHigh.udw = (Mem.tudw).b;}}); 1180 default: ldtwa({{ 1181 RdLow = (Mem.tuw).a; 1182 RdHigh = (Mem.tuw).b;}}); 1183 } 1184 } 1185 format StoreAlt { 1186 0x14: stwa({{Mem.uw = Rd;}}); 1187 0x15: stba({{Mem.ub = Rd;}}); 1188 0x16: stha({{Mem.uhw = Rd;}}); 1189 0x17: sttwa({{ 1190 //This temporary needs to be here so that the parser 1191 //will correctly identify this instruction as a store. 1192 //It's probably either the parenthesis or referencing 1193 //the member variable that throws confuses it. 1194 Twin32_t temp; 1195 temp.a = RdLow<31:0>; 1196 temp.b = RdHigh<31:0>; 1197 Mem.tuw = temp; 1198 }}); 1199 } 1200 format LoadAlt { 1201 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1202 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1203 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1204 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 1205 } 1206 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1207 {{ 1208 uint8_t tmp = mem_data; 1209 Rd.ub = tmp; 1210 }}, MEM_SWAP); 1211 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 1212 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1213 {{ 1214 uint32_t tmp = mem_data; 1215 Rd.uw = tmp; 1216 }}, MEM_SWAP); 1217 1218 format Trap { 1219 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1220 0x21: decode RD { 1221 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1222 if (fault) 1223 return fault; 1224 Fsr = Mem.uw | Fsr<63:32>;}}); 1225 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1226 if (fault) 1227 return fault; 1228 Fsr = Mem.udw;}}); 1229 default: FailUnimpl::ldfsrOther(); 1230 } 1231 0x22: ldqf({{fault = new FpDisabled;}}); 1232 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1233 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1234 0x25: decode RD { 1235 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 1236 if (fault) 1237 return fault; 1238 Mem.uw = Fsr<31:0>;}}); 1239 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 1240 if (fault) 1241 return fault; 1242 Mem.udw = Fsr;}}); 1243 default: FailUnimpl::stfsrOther(); 1244 } 1245 0x26: stqf({{fault = new FpDisabled;}}); 1246 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1247 0x2D: Nop::prefetch({{ }}); 1248 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 1249 0x32: ldqfa({{fault = new FpDisabled;}}); 1250 format LoadAlt { 1251 0x33: decode EXT_ASI { 1252 //ASI_NUCLEUS 1253 0x04: FailUnimpl::lddfa_n(); 1254 //ASI_NUCLEUS_LITTLE 1255 0x0C: FailUnimpl::lddfa_nl(); 1256 //ASI_AS_IF_USER_PRIMARY 1257 0x10: FailUnimpl::lddfa_aiup(); 1258 //ASI_AS_IF_USER_PRIMARY_LITTLE 1259 0x18: FailUnimpl::lddfa_aiupl(); 1260 //ASI_AS_IF_USER_SECONDARY 1261 0x11: FailUnimpl::lddfa_aius(); 1262 //ASI_AS_IF_USER_SECONDARY_LITTLE 1263 0x19: FailUnimpl::lddfa_aiusl(); 1264 //ASI_REAL 1265 0x14: FailUnimpl::lddfa_real(); 1266 //ASI_REAL_LITTLE 1267 0x1C: FailUnimpl::lddfa_real_l(); 1268 //ASI_REAL_IO 1269 0x15: FailUnimpl::lddfa_real_io(); 1270 //ASI_REAL_IO_LITTLE 1271 0x1D: FailUnimpl::lddfa_real_io_l(); 1272 //ASI_PRIMARY 1273 0x80: FailUnimpl::lddfa_p(); 1274 //ASI_PRIMARY_LITTLE 1275 0x88: FailUnimpl::lddfa_pl(); 1276 //ASI_SECONDARY 1277 0x81: FailUnimpl::lddfa_s(); 1278 //ASI_SECONDARY_LITTLE 1279 0x89: FailUnimpl::lddfa_sl(); 1280 //ASI_PRIMARY_NO_FAULT 1281 0x82: FailUnimpl::lddfa_pnf(); 1282 //ASI_PRIMARY_NO_FAULT_LITTLE 1283 0x8A: FailUnimpl::lddfa_pnfl(); 1284 //ASI_SECONDARY_NO_FAULT 1285 0x83: FailUnimpl::lddfa_snf(); 1286 //ASI_SECONDARY_NO_FAULT_LITTLE 1287 0x8B: FailUnimpl::lddfa_snfl(); 1288 1289 format BlockLoad { 1290 // LDBLOCKF 1291 //ASI_BLOCK_AS_IF_USER_PRIMARY 1292 0x16: FailUnimpl::ldblockf_aiup(); 1293 //ASI_BLOCK_AS_IF_USER_SECONDARY 1294 0x17: FailUnimpl::ldblockf_aius(); 1295 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1296 0x1E: FailUnimpl::ldblockf_aiupl(); 1297 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1298 0x1F: FailUnimpl::ldblockf_aiusl(); 1299 //ASI_BLOCK_PRIMARY 1300 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 1301 //ASI_BLOCK_SECONDARY 1302 0xF1: FailUnimpl::ldblockf_s(); 1303 //ASI_BLOCK_PRIMARY_LITTLE 1304 0xF8: FailUnimpl::ldblockf_pl(); 1305 //ASI_BLOCK_SECONDARY_LITTLE 1306 0xF9: FailUnimpl::ldblockf_sl(); 1307 } 1308 1309 //LDSHORTF 1310 //ASI_FL8_PRIMARY 1311 0xD0: FailUnimpl::ldshortf_8p(); 1312 //ASI_FL8_SECONDARY 1313 0xD1: FailUnimpl::ldshortf_8s(); 1314 //ASI_FL8_PRIMARY_LITTLE 1315 0xD8: FailUnimpl::ldshortf_8pl(); 1316 //ASI_FL8_SECONDARY_LITTLE 1317 0xD9: FailUnimpl::ldshortf_8sl(); 1318 //ASI_FL16_PRIMARY 1319 0xD2: FailUnimpl::ldshortf_16p(); 1320 //ASI_FL16_SECONDARY 1321 0xD3: FailUnimpl::ldshortf_16s(); 1322 //ASI_FL16_PRIMARY_LITTLE 1323 0xDA: FailUnimpl::ldshortf_16pl(); 1324 //ASI_FL16_SECONDARY_LITTLE 1325 0xDB: FailUnimpl::ldshortf_16sl(); 1326 //Not an ASI which is legal with lddfa 1327 default: Trap::lddfa_bad_asi( 1328 {{fault = new DataAccessException;}}); 1329 } 1330 } 1331 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1332 0x36: stqfa({{fault = new FpDisabled;}}); 1333 format StoreAlt { 1334 0x37: decode EXT_ASI { 1335 //ASI_NUCLEUS 1336 0x04: FailUnimpl::stdfa_n(); 1337 //ASI_NUCLEUS_LITTLE 1338 0x0C: FailUnimpl::stdfa_nl(); 1339 //ASI_AS_IF_USER_PRIMARY 1340 0x10: FailUnimpl::stdfa_aiup(); 1341 //ASI_AS_IF_USER_PRIMARY_LITTLE 1342 0x18: FailUnimpl::stdfa_aiupl(); 1343 //ASI_AS_IF_USER_SECONDARY 1344 0x11: FailUnimpl::stdfa_aius(); 1345 //ASI_AS_IF_USER_SECONDARY_LITTLE 1346 0x19: FailUnimpl::stdfa_aiusl(); 1347 //ASI_REAL 1348 0x14: FailUnimpl::stdfa_real(); 1349 //ASI_REAL_LITTLE 1350 0x1C: FailUnimpl::stdfa_real_l(); 1351 //ASI_REAL_IO 1352 0x15: FailUnimpl::stdfa_real_io(); 1353 //ASI_REAL_IO_LITTLE 1354 0x1D: FailUnimpl::stdfa_real_io_l(); 1355 //ASI_PRIMARY 1356 0x80: FailUnimpl::stdfa_p(); 1357 //ASI_PRIMARY_LITTLE 1358 0x88: FailUnimpl::stdfa_pl(); 1359 //ASI_SECONDARY 1360 0x81: FailUnimpl::stdfa_s(); 1361 //ASI_SECONDARY_LITTLE 1362 0x89: FailUnimpl::stdfa_sl(); 1363 //ASI_PRIMARY_NO_FAULT 1364 0x82: FailUnimpl::stdfa_pnf(); 1365 //ASI_PRIMARY_NO_FAULT_LITTLE 1366 0x8A: FailUnimpl::stdfa_pnfl(); 1367 //ASI_SECONDARY_NO_FAULT 1368 0x83: FailUnimpl::stdfa_snf(); 1369 //ASI_SECONDARY_NO_FAULT_LITTLE 1370 0x8B: FailUnimpl::stdfa_snfl(); 1371 1372 format BlockStore { 1373 // STBLOCKF 1374 //ASI_BLOCK_AS_IF_USER_PRIMARY 1375 0x16: FailUnimpl::stblockf_aiup(); 1376 //ASI_BLOCK_AS_IF_USER_SECONDARY 1377 0x17: FailUnimpl::stblockf_aius(); 1378 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1379 0x1E: FailUnimpl::stblockf_aiupl(); 1380 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1381 0x1F: FailUnimpl::stblockf_aiusl(); 1382 //ASI_BLOCK_PRIMARY 1383 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1384 //ASI_BLOCK_SECONDARY 1385 0xF1: FailUnimpl::stblockf_s(); 1386 //ASI_BLOCK_PRIMARY_LITTLE 1387 0xF8: FailUnimpl::stblockf_pl(); 1388 //ASI_BLOCK_SECONDARY_LITTLE 1389 0xF9: FailUnimpl::stblockf_sl(); 1390 } 1391 1392 //STSHORTF 1393 //ASI_FL8_PRIMARY 1394 0xD0: FailUnimpl::stshortf_8p(); 1395 //ASI_FL8_SECONDARY 1396 0xD1: FailUnimpl::stshortf_8s(); 1397 //ASI_FL8_PRIMARY_LITTLE 1398 0xD8: FailUnimpl::stshortf_8pl(); 1399 //ASI_FL8_SECONDARY_LITTLE 1400 0xD9: FailUnimpl::stshortf_8sl(); 1401 //ASI_FL16_PRIMARY 1402 0xD2: FailUnimpl::stshortf_16p(); 1403 //ASI_FL16_SECONDARY 1404 0xD3: FailUnimpl::stshortf_16s(); 1405 //ASI_FL16_PRIMARY_LITTLE 1406 0xDA: FailUnimpl::stshortf_16pl(); 1407 //ASI_FL16_SECONDARY_LITTLE 1408 0xDB: FailUnimpl::stshortf_16sl(); 1409 //Not an ASI which is legal with lddfa 1410 default: Trap::stdfa_bad_asi( 1411 {{fault = new DataAccessException;}}); 1412 } 1413 } 1414 0x3C: CasAlt::casa({{ 1415 mem_data = htog(Rs2.uw); 1416 Mem.uw = Rd.uw;}}, 1417 {{ 1418 uint32_t tmp = mem_data; 1419 Rd.uw = tmp; 1420 }}, MEM_SWAP_COND); 1421 0x3D: Nop::prefetcha({{ }}); 1422 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1423 Mem.udw = Rd.udw; }}, 1424 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 1425 } 1426 } 1427} 1428