decoder.isa revision 5091:662c1d7b4795
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: bpa(19, annul_code={{ 49 NPC = xc->readPC() + disp; 50 NNPC = NPC + 4; 51 }}); 52 //Branch Never 53 0x0: bpn(19, {{;}}, 54 annul_code={{ 55 NNPC = NPC + 8; 56 NPC = NPC + 4; 57 }}); 58 default: decode BPCC 59 { 60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 62 } 63 } 64 //bicc 65 0x2: decode COND2 66 { 67 //Branch Always 68 0x8: ba(22, annul_code={{ 69 NPC = xc->readPC() + disp; 70 NNPC = NPC + 4; 71 }}); 72 //Branch Never 73 0x0: bn(22, {{;}}, 74 annul_code={{ 75 NNPC = NPC + 8; 76 NPC = NPC + 4; 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { 85 0x1: bpreq(test={{Rs1.sdw == 0}}); 86 0x2: bprle(test={{Rs1.sdw <= 0}}); 87 0x3: bprl(test={{Rs1.sdw < 0}}); 88 0x5: bprne(test={{Rs1.sdw != 0}}); 89 0x6: bprg(test={{Rs1.sdw > 0}}); 90 0x7: bprge(test={{Rs1.sdw >= 0}}); 91 } 92 } 93 //SETHI (or NOP if rd == 0 and imm == 0) 94 0x4: SetHi::sethi({{Rd.udw = imm;}}); 95 //fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 //Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = xc->readPC() + disp; 101 NNPC = NPC + 4; 102 }}); 103 //Branch Never 104 0x0: fbpn(22, {{;}}, 105 annul_code={{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}); 109 default: decode BPCC { 110 0x0: fbpfcc0(19, test= 111 {{passesFpCondition(Fsr<11:10>, COND2)}}); 112 0x1: fbpfcc1(19, test= 113 {{passesFpCondition(Fsr<33:32>, COND2)}}); 114 0x2: fbpfcc2(19, test= 115 {{passesFpCondition(Fsr<35:34>, COND2)}}); 116 0x3: fbpfcc3(19, test= 117 {{passesFpCondition(Fsr<37:36>, COND2)}}); 118 } 119 } 120 } 121 //fbfcc 122 0x6: decode COND2 { 123 format BranchN { 124 //Branch Always 125 0x8: fba(22, annul_code={{ 126 NPC = xc->readPC() + disp; 127 NNPC = NPC + 4; 128 }}); 129 //Branch Never 130 0x0: fbn(22, {{;}}, 131 annul_code={{ 132 NNPC = NPC + 8; 133 NPC = NPC + 4; 134 }}); 135 default: fbfcc(22, test= 136 {{passesFpCondition(Fsr<11:10>, COND2)}}); 137 } 138 } 139 } 140 0x1: BranchN::call(30, {{ 141 if (Pstate<3:>) 142 R15 = (xc->readPC())<31:0>; 143 else 144 R15 = xc->readPC(); 145 NNPC = R15 + disp; 146 }}); 147 0x2: decode OP3 { 148 format IntOp { 149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 154 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 155 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 156 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 157 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 158 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 159 0x0A: umul({{ 160 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 161 Y = Rd<63:32>; 162 }}); 163 0x0B: smul({{ 164 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 165 Y = Rd.sdw<63:32>; 166 }}); 167 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 168 0x0D: udivx({{ 169 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 170 else Rd.udw = Rs1.udw / Rs2_or_imm13; 171 }}); 172 0x0E: udiv({{ 173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 174 else 175 { 176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 177 if(Rd.udw >> 32 != 0) 178 Rd.udw = 0xFFFFFFFF; 179 } 180 }}); 181 0x0F: sdiv({{ 182 if(Rs2_or_imm13.sdw == 0) 183 fault = new DivisionByZero; 184 else 185 { 186 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 187 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 188 Rd.udw = 0x7FFFFFFF; 189 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 190 Rd.udw = ULL(0xFFFFFFFF80000000); 191 } 192 }}); 193 } 194 format IntOpCc { 195 0x10: addcc({{ 196 int64_t resTemp, val2 = Rs2_or_imm13; 197 Rd = resTemp = Rs1 + val2;}}, 198 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 199 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 200 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 201 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 202 ); 203 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 204 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 205 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 206 0x14: subcc({{ 207 int64_t val2 = Rs2_or_imm13; 208 Rd = Rs1 - val2;}}, 209 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 210 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 211 {{(~(Rs1<63:1> + (~val2)<63:1> + 212 (Rs1 | ~val2)<0:>))<63:>}}, 213 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 214 ); 215 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 216 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 217 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 218 0x18: addccc({{ 219 int64_t resTemp, val2 = Rs2_or_imm13; 220 int64_t carryin = Ccr<0:0>; 221 Rd = resTemp = Rs1 + val2 + carryin;}}, 222 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 223 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 224 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 225 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 226 ); 227 0x1A: IntOpCcRes::umulcc({{ 228 uint64_t resTemp; 229 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 230 Y = resTemp<63:32>;}}); 231 0x1B: IntOpCcRes::smulcc({{ 232 int64_t resTemp; 233 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 234 Y = resTemp<63:32>;}}); 235 0x1C: subccc({{ 236 int64_t resTemp, val2 = Rs2_or_imm13; 237 int64_t carryin = Ccr<0:0>; 238 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 239 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 240 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 241 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 242 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 243 ); 244 0x1D: IntOpCcRes::udivxcc({{ 245 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 246 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 247 0x1E: udivcc({{ 248 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 249 int32_t overflow = 0; 250 if(val2 == 0) fault = new DivisionByZero; 251 else 252 { 253 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 254 overflow = (resTemp<63:32> != 0); 255 if(overflow) Rd = resTemp = 0xFFFFFFFF; 256 else Rd = resTemp; 257 } }}, 258 {{0}}, 259 {{overflow}}, 260 {{0}}, 261 {{0}} 262 ); 263 0x1F: sdivcc({{ 264 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 265 bool overflow = false, underflow = false; 266 if(val2 == 0) fault = new DivisionByZero; 267 else 268 { 269 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 270 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 271 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 272 if(overflow) Rd = 0x7FFFFFFF; 273 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 274 } }}, 275 {{0}}, 276 {{overflow || underflow}}, 277 {{0}}, 278 {{0}} 279 ); 280 0x20: taddcc({{ 281 int64_t resTemp, val2 = Rs2_or_imm13; 282 Rd = resTemp = Rs1 + val2; 283 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 284 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 285 {{overflow}}, 286 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 287 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 288 ); 289 0x21: tsubcc({{ 290 int64_t resTemp, val2 = Rs2_or_imm13; 291 Rd = resTemp = Rs1 + val2; 292 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 293 {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 294 {{overflow}}, 295 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 296 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 297 ); 298 0x22: taddcctv({{ 299 int64_t val2 = Rs2_or_imm13; 300 Rd = Rs1 + val2; 301 int32_t overflow = Rs1<1:0> || val2<1:0> || 302 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 303 if(overflow) fault = new TagOverflow;}}, 304 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 305 {{overflow}}, 306 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 307 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 308 ); 309 0x23: tsubcctv({{ 310 int64_t resTemp, val2 = Rs2_or_imm13; 311 Rd = resTemp = Rs1 + val2; 312 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 313 if(overflow) fault = new TagOverflow;}}, 314 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 315 {{overflow}}, 316 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 317 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 318 ); 319 0x24: mulscc({{ 320 int32_t savedLSB = Rs1<0:>; 321 322 //Step 1 323 int64_t multiplicand = Rs2_or_imm13; 324 //Step 2 325 int32_t partialP = Rs1<31:1> | 326 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 327 //Step 3 328 int32_t added = Y<0:> ? multiplicand : 0; 329 Rd = partialP + added; 330 //Steps 4 & 5 331 Y = Y<31:1> | (savedLSB << 31);}}, 332 {{((partialP<31:0> + added<31:0>)<32:0>)}}, 333 {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}}, 334 {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}}, 335 {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}} 336 ); 337 } 338 format IntOp 339 { 340 0x25: decode X { 341 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 342 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 343 } 344 0x26: decode X { 345 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 346 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 347 } 348 0x27: decode X { 349 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 350 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 351 } 352 0x28: decode RS1 { 353 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 354 //1 should cause an illegal instruction exception 355 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 356 0x03: NoPriv::rdasi({{Rd = Asi;}}); 357 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 358 0x05: NoPriv::rdpc({{ 359 if(Pstate<3:>) 360 Rd = (xc->readPC())<31:0>; 361 else 362 Rd = xc->readPC();}}); 363 0x06: NoPriv::rdfprs({{ 364 //Wait for all fpops to finish. 365 Rd = Fprs; 366 }}); 367 //7-14 should cause an illegal instruction exception 368 0x0F: decode I { 369 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 370 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 371 } 372 0x10: Priv::rdpcr({{Rd = Pcr;}}); 373 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 374 //0x12 should cause an illegal instruction exception 375 0x13: NoPriv::rdgsr({{ 376 fault = checkFpEnableFault(xc); 377 if (fault) 378 return fault; 379 Rd = Gsr; 380 }}); 381 //0x14-0x15 should cause an illegal instruction exception 382 0x16: Priv::rdsoftint({{Rd = Softint;}}); 383 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 384 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 385 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 386 0x1A: Priv::rdstrand_sts_reg({{ 387 if(Pstate<2:> && !Hpstate<2:>) 388 Rd = StrandStsReg<0:>; 389 else 390 Rd = StrandStsReg; 391 }}); 392 //0x1A is supposed to be reserved, but it reads the strand 393 //status register. 394 //0x1B-0x1F should cause an illegal instruction exception 395 } 396 0x29: decode RS1 { 397 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 398 0x01: HPriv::rdhprhtstate({{ 399 if(Tl == 0) 400 return new IllegalInstruction; 401 Rd = Htstate; 402 }}); 403 //0x02 should cause an illegal instruction exception 404 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 405 //0x04 should cause an illegal instruction exception 406 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 407 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 408 //0x07-0x1E should cause an illegal instruction exception 409 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 410 } 411 0x2A: decode RS1 { 412 0x00: Priv::rdprtpc({{ 413 if(Tl == 0) 414 return new IllegalInstruction; 415 Rd = Tpc; 416 }}); 417 0x01: Priv::rdprtnpc({{ 418 if(Tl == 0) 419 return new IllegalInstruction; 420 Rd = Tnpc; 421 }}); 422 0x02: Priv::rdprtstate({{ 423 if(Tl == 0) 424 return new IllegalInstruction; 425 Rd = Tstate; 426 }}); 427 0x03: Priv::rdprtt({{ 428 if(Tl == 0) 429 return new IllegalInstruction; 430 Rd = Tt; 431 }}); 432 0x04: Priv::rdprtick({{Rd = Tick;}}); 433 0x05: Priv::rdprtba({{Rd = Tba;}}); 434 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 435 0x07: Priv::rdprtl({{Rd = Tl;}}); 436 0x08: Priv::rdprpil({{Rd = Pil;}}); 437 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 438 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 439 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 440 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 441 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 442 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 443 //0x0F should cause an illegal instruction exception 444 0x10: Priv::rdprgl({{Rd = Gl;}}); 445 //0x11-0x1F should cause an illegal instruction exception 446 } 447 0x2B: BasicOperate::flushw({{ 448 if(NWindows - 2 - Cansave != 0) 449 { 450 if(Otherwin) 451 fault = new SpillNOther(4*Wstate<5:3>); 452 else 453 fault = new SpillNNormal(4*Wstate<2:0>); 454 } 455 }}); 456 0x2C: decode MOVCC3 457 { 458 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 459 0x1: decode CC 460 { 461 0x0: movcci({{ 462 if(passesCondition(Ccr<3:0>, COND4)) 463 Rd = Rs2_or_imm11; 464 else 465 Rd = Rd; 466 }}); 467 0x2: movccx({{ 468 if(passesCondition(Ccr<7:4>, COND4)) 469 Rd = Rs2_or_imm11; 470 else 471 Rd = Rd; 472 }}); 473 } 474 } 475 0x2D: sdivx({{ 476 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 477 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 478 }}); 479 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 480 0x2F: decode RCOND3 481 { 482 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 483 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 484 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 485 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 486 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 487 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 488 } 489 0x30: decode RD { 490 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 491 //0x01 should cause an illegal instruction exception 492 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 493 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 494 //0x04-0x05 should cause an illegal instruction exception 495 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 496 //0x07-0x0E should cause an illegal instruction exception 497 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 498 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 499 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 500 //0x12 should cause an illegal instruction exception 501 0x13: NoPriv::wrgsr({{ 502 if(Fprs<2:> == 0 || Pstate<4:> == 0) 503 return new FpDisabled; 504 Gsr = Rs1 ^ Rs2_or_imm13; 505 }}); 506 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 507 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 508 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 509 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 510 0x18: NoPriv::wrstick({{ 511 if(!Hpstate<2:>) 512 return new IllegalInstruction; 513 Stick = Rs1 ^ Rs2_or_imm13; 514 }}); 515 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 516 0x1A: Priv::wrstrand_sts_reg({{ 517 StrandStsReg = Rs1 ^ Rs2_or_imm13; 518 }}); 519 //0x1A is supposed to be reserved, but it writes the strand 520 //status register. 521 //0x1B-0x1F should cause an illegal instruction exception 522 } 523 0x31: decode FCN { 524 0x0: Priv::saved({{ 525 assert(Cansave < NWindows - 2); 526 assert(Otherwin || Canrestore); 527 Cansave = Cansave + 1; 528 if(Otherwin == 0) 529 Canrestore = Canrestore - 1; 530 else 531 Otherwin = Otherwin - 1; 532 }}); 533 0x1: Priv::restored({{ 534 assert(Cansave || Otherwin); 535 assert(Canrestore < NWindows - 2); 536 Canrestore = Canrestore + 1; 537 if(Otherwin == 0) 538 Cansave = Cansave - 1; 539 else 540 Otherwin = Otherwin - 1; 541 542 if(Cleanwin < NWindows - 1) 543 Cleanwin = Cleanwin + 1; 544 }}); 545 } 546 0x32: decode RD { 547 0x00: Priv::wrprtpc({{ 548 if(Tl == 0) 549 return new IllegalInstruction; 550 else 551 Tpc = Rs1 ^ Rs2_or_imm13; 552 }}); 553 0x01: Priv::wrprtnpc({{ 554 if(Tl == 0) 555 return new IllegalInstruction; 556 else 557 Tnpc = Rs1 ^ Rs2_or_imm13; 558 }}); 559 0x02: Priv::wrprtstate({{ 560 if(Tl == 0) 561 return new IllegalInstruction; 562 else 563 Tstate = Rs1 ^ Rs2_or_imm13; 564 }}); 565 0x03: Priv::wrprtt({{ 566 if(Tl == 0) 567 return new IllegalInstruction; 568 else 569 Tt = Rs1 ^ Rs2_or_imm13; 570 }}); 571 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 572 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 573 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 574 0x07: Priv::wrprtl({{ 575 if(Pstate<2:> && !Hpstate<2:>) 576 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 577 else 578 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 579 }}); 580 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 581 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 582 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 583 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 584 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 585 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 586 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 587 //0x0F should cause an illegal instruction exception 588 0x10: Priv::wrprgl({{ 589 if(Pstate<2:> && !Hpstate<2:>) 590 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 591 else 592 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 593 }}); 594 //0x11-0x1F should cause an illegal instruction exception 595 } 596 0x33: decode RD { 597 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 598 0x01: HPriv::wrhprhtstate({{ 599 if(Tl == 0) 600 return new IllegalInstruction; 601 Htstate = Rs1 ^ Rs2_or_imm13; 602 }}); 603 //0x02 should cause an illegal instruction exception 604 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 605 //0x04 should cause an illegal instruction exception 606 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 607 //0x06-0x01D should cause an illegal instruction exception 608 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 609 } 610 0x34: decode OPF{ 611 format FpBasic{ 612 0x01: fmovs({{ 613 Frds.uw = Frs2s.uw; 614 //fsr.ftt = fsr.cexc = 0 615 Fsr &= ~(7 << 14); 616 Fsr &= ~(0x1F); 617 }}); 618 0x02: fmovd({{ 619 Frd.udw = Frs2.udw; 620 //fsr.ftt = fsr.cexc = 0 621 Fsr &= ~(7 << 14); 622 Fsr &= ~(0x1F); 623 }}); 624 0x03: FpUnimpl::fmovq(); 625 0x05: fnegs({{ 626 Frds.uw = Frs2s.uw ^ (1UL << 31); 627 //fsr.ftt = fsr.cexc = 0 628 Fsr &= ~(7 << 14); 629 Fsr &= ~(0x1F); 630 }}); 631 0x06: fnegd({{ 632 Frd.udw = Frs2.udw ^ (1ULL << 63); 633 //fsr.ftt = fsr.cexc = 0 634 Fsr &= ~(7 << 14); 635 Fsr &= ~(0x1F); 636 }}); 637 0x07: FpUnimpl::fnegq(); 638 0x09: fabss({{ 639 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 640 //fsr.ftt = fsr.cexc = 0 641 Fsr &= ~(7 << 14); 642 Fsr &= ~(0x1F); 643 }}); 644 0x0A: fabsd({{ 645 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 646 //fsr.ftt = fsr.cexc = 0 647 Fsr &= ~(7 << 14); 648 Fsr &= ~(0x1F); 649 }}); 650 0x0B: FpUnimpl::fabsq(); 651 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 652 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 653 0x2B: FpUnimpl::fsqrtq(); 654 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 655 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 656 0x43: FpUnimpl::faddq(); 657 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 658 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 659 0x47: FpUnimpl::fsubq(); 660 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 661 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 662 0x4B: FpUnimpl::fmulq(); 663 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 664 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 665 0x4F: FpUnimpl::fdivq(); 666 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 667 0x6E: FpUnimpl::fdmulq(); 668 0x81: fstox({{ 669 Frd.sdw = static_cast<int64_t>(Frs2s.sf); 670 }}); 671 0x82: fdtox({{ 672 Frd.sdw = static_cast<int64_t>(Frs2.df); 673 }}); 674 0x83: FpUnimpl::fqtox(); 675 0x84: fxtos({{ 676 Frds.sf = static_cast<float>(Frs2.sdw); 677 }}); 678 0x88: fxtod({{ 679 Frd.df = static_cast<double>(Frs2.sdw); 680 }}); 681 0x8C: FpUnimpl::fxtoq(); 682 0xC4: fitos({{ 683 Frds.sf = static_cast<float>(Frs2s.sw); 684 }}); 685 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 686 0xC7: FpUnimpl::fqtos(); 687 0xC8: fitod({{ 688 Frd.df = static_cast<double>(Frs2s.sw); 689 }}); 690 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 691 0xCB: FpUnimpl::fqtod(); 692 0xCC: FpUnimpl::fitoq(); 693 0xCD: FpUnimpl::fstoq(); 694 0xCE: FpUnimpl::fdtoq(); 695 0xD1: fstoi({{ 696 Frds.sw = static_cast<int32_t>(Frs2s.sf); 697 float t = Frds.sw; 698 if (t != Frs2s.sf) 699 Fsr = insertBits(Fsr, 4,0, 0x01); 700 }}); 701 0xD2: fdtoi({{ 702 Frds.sw = static_cast<int32_t>(Frs2.df); 703 double t = Frds.sw; 704 if (t != Frs2.df) 705 Fsr = insertBits(Fsr, 4,0, 0x01); 706 }}); 707 0xD3: FpUnimpl::fqtoi(); 708 default: FailUnimpl::fpop1(); 709 } 710 } 711 0x35: decode OPF{ 712 format FpBasic{ 713 0x01: fmovs_fcc0({{ 714 if(passesFpCondition(Fsr<11:10>, COND4)) 715 Frds = Frs2s; 716 else 717 Frds = Frds; 718 }}); 719 0x02: fmovd_fcc0({{ 720 if(passesFpCondition(Fsr<11:10>, COND4)) 721 Frd = Frs2; 722 else 723 Frd = Frd; 724 }}); 725 0x03: FpUnimpl::fmovq_fcc0(); 726 0x25: fmovrsz({{ 727 if(Rs1 == 0) 728 Frds = Frs2s; 729 else 730 Frds = Frds; 731 }}); 732 0x26: fmovrdz({{ 733 if(Rs1 == 0) 734 Frd = Frs2; 735 else 736 Frd = Frd; 737 }}); 738 0x27: FpUnimpl::fmovrqz(); 739 0x41: fmovs_fcc1({{ 740 if(passesFpCondition(Fsr<33:32>, COND4)) 741 Frds = Frs2s; 742 else 743 Frds = Frds; 744 }}); 745 0x42: fmovd_fcc1({{ 746 if(passesFpCondition(Fsr<33:32>, COND4)) 747 Frd = Frs2; 748 else 749 Frd = Frd; 750 }}); 751 0x43: FpUnimpl::fmovq_fcc1(); 752 0x45: fmovrslez({{ 753 if(Rs1 <= 0) 754 Frds = Frs2s; 755 else 756 Frds = Frds; 757 }}); 758 0x46: fmovrdlez({{ 759 if(Rs1 <= 0) 760 Frd = Frs2; 761 else 762 Frd = Frd; 763 }}); 764 0x47: FpUnimpl::fmovrqlez(); 765 0x51: fcmps({{ 766 uint8_t fcc; 767 if(isnan(Frs1s) || isnan(Frs2s)) 768 fcc = 3; 769 else if(Frs1s < Frs2s) 770 fcc = 1; 771 else if(Frs1s > Frs2s) 772 fcc = 2; 773 else 774 fcc = 0; 775 uint8_t firstbit = 10; 776 if(FCMPCC) 777 firstbit = FCMPCC * 2 + 30; 778 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 779 }}); 780 0x52: fcmpd({{ 781 uint8_t fcc; 782 if(isnan(Frs1) || isnan(Frs2)) 783 fcc = 3; 784 else if(Frs1 < Frs2) 785 fcc = 1; 786 else if(Frs1 > Frs2) 787 fcc = 2; 788 else 789 fcc = 0; 790 uint8_t firstbit = 10; 791 if(FCMPCC) 792 firstbit = FCMPCC * 2 + 30; 793 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 794 }}); 795 0x53: FpUnimpl::fcmpq(); 796 0x55: fcmpes({{ 797 uint8_t fcc = 0; 798 if(isnan(Frs1s) || isnan(Frs2s)) 799 fault = new FpExceptionIEEE754; 800 if(Frs1s < Frs2s) 801 fcc = 1; 802 else if(Frs1s > Frs2s) 803 fcc = 2; 804 uint8_t firstbit = 10; 805 if(FCMPCC) 806 firstbit = FCMPCC * 2 + 30; 807 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 808 }}); 809 0x56: fcmped({{ 810 uint8_t fcc = 0; 811 if(isnan(Frs1) || isnan(Frs2)) 812 fault = new FpExceptionIEEE754; 813 if(Frs1 < Frs2) 814 fcc = 1; 815 else if(Frs1 > Frs2) 816 fcc = 2; 817 uint8_t firstbit = 10; 818 if(FCMPCC) 819 firstbit = FCMPCC * 2 + 30; 820 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 821 }}); 822 0x57: FpUnimpl::fcmpeq(); 823 0x65: fmovrslz({{ 824 if(Rs1 < 0) 825 Frds = Frs2s; 826 else 827 Frds = Frds; 828 }}); 829 0x66: fmovrdlz({{ 830 if(Rs1 < 0) 831 Frd = Frs2; 832 else 833 Frd = Frd; 834 }}); 835 0x67: FpUnimpl::fmovrqlz(); 836 0x81: fmovs_fcc2({{ 837 if(passesFpCondition(Fsr<35:34>, COND4)) 838 Frds = Frs2s; 839 else 840 Frds = Frds; 841 }}); 842 0x82: fmovd_fcc2({{ 843 if(passesFpCondition(Fsr<35:34>, COND4)) 844 Frd = Frs2; 845 else 846 Frd = Frd; 847 }}); 848 0x83: FpUnimpl::fmovq_fcc2(); 849 0xA5: fmovrsnz({{ 850 if(Rs1 != 0) 851 Frds = Frs2s; 852 else 853 Frds = Frds; 854 }}); 855 0xA6: fmovrdnz({{ 856 if(Rs1 != 0) 857 Frd = Frs2; 858 else 859 Frd = Frd; 860 }}); 861 0xA7: FpUnimpl::fmovrqnz(); 862 0xC1: fmovs_fcc3({{ 863 if(passesFpCondition(Fsr<37:36>, COND4)) 864 Frds = Frs2s; 865 else 866 Frds = Frds; 867 }}); 868 0xC2: fmovd_fcc3({{ 869 if(passesFpCondition(Fsr<37:36>, COND4)) 870 Frd = Frs2; 871 else 872 Frd = Frd; 873 }}); 874 0xC3: FpUnimpl::fmovq_fcc3(); 875 0xC5: fmovrsgz({{ 876 if(Rs1 > 0) 877 Frds = Frs2s; 878 else 879 Frds = Frds; 880 }}); 881 0xC6: fmovrdgz({{ 882 if(Rs1 > 0) 883 Frd = Frs2; 884 else 885 Frd = Frd; 886 }}); 887 0xC7: FpUnimpl::fmovrqgz(); 888 0xE5: fmovrsgez({{ 889 if(Rs1 >= 0) 890 Frds = Frs2s; 891 else 892 Frds = Frds; 893 }}); 894 0xE6: fmovrdgez({{ 895 if(Rs1 >= 0) 896 Frd = Frs2; 897 else 898 Frd = Frd; 899 }}); 900 0xE7: FpUnimpl::fmovrqgez(); 901 0x101: fmovs_icc({{ 902 if(passesCondition(Ccr<3:0>, COND4)) 903 Frds = Frs2s; 904 else 905 Frds = Frds; 906 }}); 907 0x102: fmovd_icc({{ 908 if(passesCondition(Ccr<3:0>, COND4)) 909 Frd = Frs2; 910 else 911 Frd = Frd; 912 }}); 913 0x103: FpUnimpl::fmovq_icc(); 914 0x181: fmovs_xcc({{ 915 if(passesCondition(Ccr<7:4>, COND4)) 916 Frds = Frs2s; 917 else 918 Frds = Frds; 919 }}); 920 0x182: fmovd_xcc({{ 921 if(passesCondition(Ccr<7:4>, COND4)) 922 Frd = Frs2; 923 else 924 Frd = Frd; 925 }}); 926 0x183: FpUnimpl::fmovq_xcc(); 927 default: FailUnimpl::fpop2(); 928 } 929 } 930 //This used to be just impdep1, but now it's a whole bunch 931 //of instructions 932 0x36: decode OPF{ 933 0x00: FailUnimpl::edge8(); 934 0x01: FailUnimpl::edge8n(); 935 0x02: FailUnimpl::edge8l(); 936 0x03: FailUnimpl::edge8ln(); 937 0x04: FailUnimpl::edge16(); 938 0x05: FailUnimpl::edge16n(); 939 0x06: FailUnimpl::edge16l(); 940 0x07: FailUnimpl::edge16ln(); 941 0x08: FailUnimpl::edge32(); 942 0x09: FailUnimpl::edge32n(); 943 0x0A: FailUnimpl::edge32l(); 944 0x0B: FailUnimpl::edge32ln(); 945 0x10: FailUnimpl::array8(); 946 0x12: FailUnimpl::array16(); 947 0x14: FailUnimpl::array32(); 948 0x18: BasicOperate::alignaddr({{ 949 uint64_t sum = Rs1 + Rs2; 950 Rd = sum & ~7; 951 Gsr = (Gsr & ~7) | (sum & 7); 952 }}); 953 0x19: FailUnimpl::bmask(); 954 0x1A: BasicOperate::alignaddresslittle({{ 955 uint64_t sum = Rs1 + Rs2; 956 Rd = sum & ~7; 957 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 958 }}); 959 0x20: FailUnimpl::fcmple16(); 960 0x22: FailUnimpl::fcmpne16(); 961 0x24: FailUnimpl::fcmple32(); 962 0x26: FailUnimpl::fcmpne32(); 963 0x28: FailUnimpl::fcmpgt16(); 964 0x2A: FailUnimpl::fcmpeq16(); 965 0x2C: FailUnimpl::fcmpgt32(); 966 0x2E: FailUnimpl::fcmpeq32(); 967 0x31: FailUnimpl::fmul8x16(); 968 0x33: FailUnimpl::fmul8x16au(); 969 0x35: FailUnimpl::fmul8x16al(); 970 0x36: FailUnimpl::fmul8sux16(); 971 0x37: FailUnimpl::fmul8ulx16(); 972 0x38: FailUnimpl::fmuld8sux16(); 973 0x39: FailUnimpl::fmuld8ulx16(); 974 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 975 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 976 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 977 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 978 0x48: BasicOperate::faligndata({{ 979 uint64_t msbX = Frs1.udw; 980 uint64_t lsbX = Frs2.udw; 981 //Some special cases need to be split out, first 982 //because they're the most likely to be used, and 983 //second because otherwise, we end up shifting by 984 //greater than the width of the type being shifted, 985 //namely 64, which produces undefined results according 986 //to the C standard. 987 switch(Gsr<2:0>) 988 { 989 case 0: 990 Frd.udw = msbX; 991 break; 992 case 8: 993 Frd.udw = lsbX; 994 break; 995 default: 996 uint64_t msbShift = Gsr<2:0> * 8; 997 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 998 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 999 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 1000 Frd.udw = ((msbX & msbMask) << msbShift) | 1001 ((lsbX & lsbMask) >> lsbShift); 1002 } 1003 }}); 1004 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 1005 0x4C: FailUnimpl::bshuffle(); 1006 0x4D: FailUnimpl::fexpand(); 1007 0x50: FailUnimpl::fpadd16(); 1008 0x51: FailUnimpl::fpadd16s(); 1009 0x52: FailUnimpl::fpadd32(); 1010 0x53: FailUnimpl::fpadd32s(); 1011 0x54: FailUnimpl::fpsub16(); 1012 0x55: FailUnimpl::fpsub16s(); 1013 0x56: FailUnimpl::fpsub32(); 1014 0x57: FailUnimpl::fpsub32s(); 1015 0x60: FpBasic::fzero({{Frd.df = 0;}}); 1016 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 1017 0x62: FailUnimpl::fnor(); 1018 0x63: FailUnimpl::fnors(); 1019 0x64: FailUnimpl::fandnot2(); 1020 0x65: FailUnimpl::fandnot2s(); 1021 0x66: FpBasic::fnot2({{ 1022 Frd.df = (double)(~((uint64_t)Frs2.df)); 1023 }}); 1024 0x67: FpBasic::fnot2s({{ 1025 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 1026 }}); 1027 0x68: FailUnimpl::fandnot1(); 1028 0x69: FailUnimpl::fandnot1s(); 1029 0x6A: FpBasic::fnot1({{ 1030 Frd.df = (double)(~((uint64_t)Frs1.df)); 1031 }}); 1032 0x6B: FpBasic::fnot1s({{ 1033 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 1034 }}); 1035 0x6C: FailUnimpl::fxor(); 1036 0x6D: FailUnimpl::fxors(); 1037 0x6E: FailUnimpl::fnand(); 1038 0x6F: FailUnimpl::fnands(); 1039 0x70: FailUnimpl::fand(); 1040 0x71: FailUnimpl::fands(); 1041 0x72: FailUnimpl::fxnor(); 1042 0x73: FailUnimpl::fxnors(); 1043 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 1044 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 1045 0x76: FailUnimpl::fornot2(); 1046 0x77: FailUnimpl::fornot2s(); 1047 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 1048 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 1049 0x7A: FailUnimpl::fornot1(); 1050 0x7B: FailUnimpl::fornot1s(); 1051 0x7C: FailUnimpl::for(); 1052 0x7D: FailUnimpl::fors(); 1053 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 1054 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 1055 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 1056 0x81: FailUnimpl::siam(); 1057 } 1058 // M5 special opcodes use the reserved IMPDEP2A opcode space 1059 0x37: decode M5FUNC { 1060#if FULL_SYSTEM 1061 format BasicOperate { 1062 // we have 7 bits of space here to play with... 1063 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 1064 }}, No_OpClass, IsNonSpeculative); 1065 0x50: m5readfile({{ 1066 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 1067 }}, IsNonSpeculative); 1068 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 1069 }}, IsNonSpeculative); 1070 0x54: m5panic({{ 1071 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 1072 }}, No_OpClass, IsNonSpeculative); 1073 } 1074#endif 1075 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 1076 } 1077 0x38: Branch::jmpl({{ 1078 Addr target = Rs1 + Rs2_or_imm13; 1079 if(target & 0x3) 1080 fault = new MemAddressNotAligned; 1081 else 1082 { 1083 if (Pstate<3:>) 1084 Rd = (xc->readPC())<31:0>; 1085 else 1086 Rd = xc->readPC(); 1087 NNPC = target; 1088 } 1089 }}); 1090 0x39: Branch::return({{ 1091 Addr target = Rs1 + Rs2_or_imm13; 1092 if(fault == NoFault) 1093 { 1094 //Check for fills which are higher priority than alignment 1095 //faults. 1096 if(Canrestore == 0) 1097 { 1098 if(Otherwin) 1099 fault = new FillNOther(4*Wstate<5:3>); 1100 else 1101 fault = new FillNNormal(4*Wstate<2:0>); 1102 } 1103 //Check for alignment faults 1104 else if(target & 0x3) 1105 fault = new MemAddressNotAligned; 1106 else 1107 { 1108 NNPC = target; 1109 Cwp = (Cwp - 1 + NWindows) % NWindows; 1110 Cansave = Cansave + 1; 1111 Canrestore = Canrestore - 1; 1112 } 1113 } 1114 }}); 1115 0x3A: decode CC 1116 { 1117 0x0: Trap::tcci({{ 1118 if(passesCondition(Ccr<3:0>, COND2)) 1119 { 1120 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1121 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1122 fault = new TrapInstruction(lTrapNum); 1123 } 1124 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1125 0x2: Trap::tccx({{ 1126 if(passesCondition(Ccr<7:4>, COND2)) 1127 { 1128 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1129 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1130 fault = new TrapInstruction(lTrapNum); 1131 } 1132 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1133 } 1134 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1135 MemWriteOp); 1136 0x3C: save({{ 1137 if(Cansave == 0) 1138 { 1139 if(Otherwin) 1140 fault = new SpillNOther(4*Wstate<5:3>); 1141 else 1142 fault = new SpillNNormal(4*Wstate<2:0>); 1143 } 1144 else if(Cleanwin - Canrestore == 0) 1145 { 1146 fault = new CleanWindow; 1147 } 1148 else 1149 { 1150 Cwp = (Cwp + 1) % NWindows; 1151 Rd_next = Rs1 + Rs2_or_imm13; 1152 Cansave = Cansave - 1; 1153 Canrestore = Canrestore + 1; 1154 } 1155 }}); 1156 0x3D: restore({{ 1157 if(Canrestore == 0) 1158 { 1159 if(Otherwin) 1160 fault = new FillNOther(4*Wstate<5:3>); 1161 else 1162 fault = new FillNNormal(4*Wstate<2:0>); 1163 } 1164 else 1165 { 1166 Cwp = (Cwp - 1 + NWindows) % NWindows; 1167 Rd_prev = Rs1 + Rs2_or_imm13; 1168 Cansave = Cansave + 1; 1169 Canrestore = Canrestore - 1; 1170 } 1171 }}); 1172 0x3E: decode FCN { 1173 0x0: Priv::done({{ 1174 if(Tl == 0) 1175 return new IllegalInstruction; 1176 1177 Cwp = Tstate<4:0>; 1178 Pstate = Tstate<20:8>; 1179 Asi = Tstate<31:24>; 1180 Ccr = Tstate<39:32>; 1181 Gl = Tstate<42:40>; 1182 Hpstate = Htstate; 1183 NPC = Tnpc; 1184 NNPC = Tnpc + 4; 1185 Tl = Tl - 1; 1186 }}); 1187 0x1: Priv::retry({{ 1188 if(Tl == 0) 1189 return new IllegalInstruction; 1190 Cwp = Tstate<4:0>; 1191 Pstate = Tstate<20:8>; 1192 Asi = Tstate<31:24>; 1193 Ccr = Tstate<39:32>; 1194 Gl = Tstate<42:40>; 1195 Hpstate = Htstate; 1196 NPC = Tpc; 1197 NNPC = Tnpc; 1198 Tl = Tl - 1; 1199 }}); 1200 } 1201 } 1202 } 1203 0x3: decode OP3 { 1204 format Load { 1205 0x00: lduw({{Rd = Mem.uw;}}); 1206 0x01: ldub({{Rd = Mem.ub;}}); 1207 0x02: lduh({{Rd = Mem.uhw;}}); 1208 0x03: ldtw({{ 1209 RdLow = (Mem.tuw).a; 1210 RdHigh = (Mem.tuw).b; 1211 }}); 1212 } 1213 format Store { 1214 0x04: stw({{Mem.uw = Rd.sw;}}); 1215 0x05: stb({{Mem.ub = Rd.sb;}}); 1216 0x06: sth({{Mem.uhw = Rd.shw;}}); 1217 0x07: sttw({{ 1218 //This temporary needs to be here so that the parser 1219 //will correctly identify this instruction as a store. 1220 //It's probably either the parenthesis or referencing 1221 //the member variable that throws confuses it. 1222 Twin32_t temp; 1223 temp.a = RdLow<31:0>; 1224 temp.b = RdHigh<31:0>; 1225 Mem.tuw = temp; 1226 }}); 1227 } 1228 format Load { 1229 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1230 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1231 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1232 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1233 } 1234 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1235 {{ 1236 uint8_t tmp = mem_data; 1237 Rd.ub = tmp; 1238 }}, MEM_SWAP); 1239 0x0E: Store::stx({{Mem.udw = Rd}}); 1240 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1241 {{ 1242 uint32_t tmp = mem_data; 1243 Rd.uw = tmp; 1244 }}, MEM_SWAP); 1245 format LoadAlt { 1246 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1247 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1248 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1249 0x13: decode EXT_ASI { 1250 //ASI_LDTD_AIUP 1251 0x22: TwinLoad::ldtx_aiup( 1252 {{RdLow.udw = (Mem.tudw).a; 1253 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1254 //ASI_LDTD_AIUS 1255 0x23: TwinLoad::ldtx_aius( 1256 {{RdLow.udw = (Mem.tudw).a; 1257 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1258 //ASI_QUAD_LDD 1259 0x24: TwinLoad::ldtx_quad_ldd( 1260 {{RdLow.udw = (Mem.tudw).a; 1261 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1262 //ASI_LDTX_REAL 1263 0x26: TwinLoad::ldtx_real( 1264 {{RdLow.udw = (Mem.tudw).a; 1265 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1266 //ASI_LDTX_N 1267 0x27: TwinLoad::ldtx_n( 1268 {{RdLow.udw = (Mem.tudw).a; 1269 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1270 //ASI_LDTX_AIUP_L 1271 0x2A: TwinLoad::ldtx_aiup_l( 1272 {{RdLow.udw = (Mem.tudw).a; 1273 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1274 //ASI_LDTX_AIUS_L 1275 0x2B: TwinLoad::ldtx_aius_l( 1276 {{RdLow.udw = (Mem.tudw).a; 1277 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1278 //ASI_LDTX_L 1279 0x2C: TwinLoad::ldtx_l( 1280 {{RdLow.udw = (Mem.tudw).a; 1281 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1282 //ASI_LDTX_REAL_L 1283 0x2E: TwinLoad::ldtx_real_l( 1284 {{RdLow.udw = (Mem.tudw).a; 1285 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1286 //ASI_LDTX_N_L 1287 0x2F: TwinLoad::ldtx_n_l( 1288 {{RdLow.udw = (Mem.tudw).a; 1289 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1290 //ASI_LDTX_P 1291 0xE2: TwinLoad::ldtx_p( 1292 {{RdLow.udw = (Mem.tudw).a; 1293 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1294 //ASI_LDTX_S 1295 0xE3: TwinLoad::ldtx_s( 1296 {{RdLow.udw = (Mem.tudw).a; 1297 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1298 //ASI_LDTX_PL 1299 0xEA: TwinLoad::ldtx_pl( 1300 {{RdLow.udw = (Mem.tudw).a; 1301 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1302 //ASI_LDTX_SL 1303 0xEB: TwinLoad::ldtx_sl( 1304 {{RdLow.udw = (Mem.tudw).a; 1305 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1306 default: ldtwa({{ 1307 RdLow = (Mem.tuw).a; 1308 RdHigh = (Mem.tuw).b; 1309 }}, {{EXT_ASI}}); 1310 } 1311 } 1312 format StoreAlt { 1313 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1314 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1315 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1316 0x17: sttwa({{ 1317 //This temporary needs to be here so that the parser 1318 //will correctly identify this instruction as a store. 1319 //It's probably either the parenthesis or referencing 1320 //the member variable that throws confuses it. 1321 Twin32_t temp; 1322 temp.a = RdLow<31:0>; 1323 temp.b = RdHigh<31:0>; 1324 Mem.tuw = temp; 1325 }}, {{EXT_ASI}}); 1326 } 1327 format LoadAlt { 1328 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1329 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1330 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1331 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1332 } 1333 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1334 {{ 1335 uint8_t tmp = mem_data; 1336 Rd.ub = tmp; 1337 }}, {{EXT_ASI}}, MEM_SWAP); 1338 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1339 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1340 {{ 1341 uint32_t tmp = mem_data; 1342 Rd.uw = tmp; 1343 }}, {{EXT_ASI}}, MEM_SWAP); 1344 1345 format Trap { 1346 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1347 0x21: decode RD { 1348 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1349 if (fault) 1350 return fault; 1351 Fsr = Mem.uw | Fsr<63:32>;}}); 1352 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1353 if (fault) 1354 return fault; 1355 Fsr = Mem.udw;}}); 1356 default: FailUnimpl::ldfsrOther(); 1357 } 1358 0x22: ldqf({{fault = new FpDisabled;}}); 1359 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1360 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1361 0x25: decode RD { 1362 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 1363 if (fault) 1364 return fault; 1365 Mem.uw = Fsr<31:0>; 1366 Fsr = insertBits(Fsr,16,14,0);}}); 1367 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 1368 if (fault) 1369 return fault; 1370 Mem.udw = Fsr; 1371 Fsr = insertBits(Fsr,16,14,0);}}); 1372 default: FailUnimpl::stfsrOther(); 1373 } 1374 0x26: stqf({{fault = new FpDisabled;}}); 1375 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1376 0x2D: Nop::prefetch({{ }}); 1377 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 1378 0x32: ldqfa({{fault = new FpDisabled;}}); 1379 format LoadAlt { 1380 0x33: decode EXT_ASI { 1381 //ASI_NUCLEUS 1382 0x04: FailUnimpl::lddfa_n(); 1383 //ASI_NUCLEUS_LITTLE 1384 0x0C: FailUnimpl::lddfa_nl(); 1385 //ASI_AS_IF_USER_PRIMARY 1386 0x10: FailUnimpl::lddfa_aiup(); 1387 //ASI_AS_IF_USER_PRIMARY_LITTLE 1388 0x18: FailUnimpl::lddfa_aiupl(); 1389 //ASI_AS_IF_USER_SECONDARY 1390 0x11: FailUnimpl::lddfa_aius(); 1391 //ASI_AS_IF_USER_SECONDARY_LITTLE 1392 0x19: FailUnimpl::lddfa_aiusl(); 1393 //ASI_REAL 1394 0x14: FailUnimpl::lddfa_real(); 1395 //ASI_REAL_LITTLE 1396 0x1C: FailUnimpl::lddfa_real_l(); 1397 //ASI_REAL_IO 1398 0x15: FailUnimpl::lddfa_real_io(); 1399 //ASI_REAL_IO_LITTLE 1400 0x1D: FailUnimpl::lddfa_real_io_l(); 1401 //ASI_PRIMARY 1402 0x80: FailUnimpl::lddfa_p(); 1403 //ASI_PRIMARY_LITTLE 1404 0x88: FailUnimpl::lddfa_pl(); 1405 //ASI_SECONDARY 1406 0x81: FailUnimpl::lddfa_s(); 1407 //ASI_SECONDARY_LITTLE 1408 0x89: FailUnimpl::lddfa_sl(); 1409 //ASI_PRIMARY_NO_FAULT 1410 0x82: FailUnimpl::lddfa_pnf(); 1411 //ASI_PRIMARY_NO_FAULT_LITTLE 1412 0x8A: FailUnimpl::lddfa_pnfl(); 1413 //ASI_SECONDARY_NO_FAULT 1414 0x83: FailUnimpl::lddfa_snf(); 1415 //ASI_SECONDARY_NO_FAULT_LITTLE 1416 0x8B: FailUnimpl::lddfa_snfl(); 1417 1418 format BlockLoad { 1419 // LDBLOCKF 1420 //ASI_BLOCK_AS_IF_USER_PRIMARY 1421 0x16: FailUnimpl::ldblockf_aiup(); 1422 //ASI_BLOCK_AS_IF_USER_SECONDARY 1423 0x17: FailUnimpl::ldblockf_aius(); 1424 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1425 0x1E: FailUnimpl::ldblockf_aiupl(); 1426 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1427 0x1F: FailUnimpl::ldblockf_aiusl(); 1428 //ASI_BLOCK_PRIMARY 1429 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 1430 //ASI_BLOCK_SECONDARY 1431 0xF1: FailUnimpl::ldblockf_s(); 1432 //ASI_BLOCK_PRIMARY_LITTLE 1433 0xF8: FailUnimpl::ldblockf_pl(); 1434 //ASI_BLOCK_SECONDARY_LITTLE 1435 0xF9: FailUnimpl::ldblockf_sl(); 1436 } 1437 1438 //LDSHORTF 1439 //ASI_FL8_PRIMARY 1440 0xD0: FailUnimpl::ldshortf_8p(); 1441 //ASI_FL8_SECONDARY 1442 0xD1: FailUnimpl::ldshortf_8s(); 1443 //ASI_FL8_PRIMARY_LITTLE 1444 0xD8: FailUnimpl::ldshortf_8pl(); 1445 //ASI_FL8_SECONDARY_LITTLE 1446 0xD9: FailUnimpl::ldshortf_8sl(); 1447 //ASI_FL16_PRIMARY 1448 0xD2: FailUnimpl::ldshortf_16p(); 1449 //ASI_FL16_SECONDARY 1450 0xD3: FailUnimpl::ldshortf_16s(); 1451 //ASI_FL16_PRIMARY_LITTLE 1452 0xDA: FailUnimpl::ldshortf_16pl(); 1453 //ASI_FL16_SECONDARY_LITTLE 1454 0xDB: FailUnimpl::ldshortf_16sl(); 1455 //Not an ASI which is legal with lddfa 1456 default: Trap::lddfa_bad_asi( 1457 {{fault = new DataAccessException;}}); 1458 } 1459 } 1460 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1461 0x36: stqfa({{fault = new FpDisabled;}}); 1462 format StoreAlt { 1463 0x37: decode EXT_ASI { 1464 //ASI_NUCLEUS 1465 0x04: FailUnimpl::stdfa_n(); 1466 //ASI_NUCLEUS_LITTLE 1467 0x0C: FailUnimpl::stdfa_nl(); 1468 //ASI_AS_IF_USER_PRIMARY 1469 0x10: FailUnimpl::stdfa_aiup(); 1470 //ASI_AS_IF_USER_PRIMARY_LITTLE 1471 0x18: FailUnimpl::stdfa_aiupl(); 1472 //ASI_AS_IF_USER_SECONDARY 1473 0x11: FailUnimpl::stdfa_aius(); 1474 //ASI_AS_IF_USER_SECONDARY_LITTLE 1475 0x19: FailUnimpl::stdfa_aiusl(); 1476 //ASI_REAL 1477 0x14: FailUnimpl::stdfa_real(); 1478 //ASI_REAL_LITTLE 1479 0x1C: FailUnimpl::stdfa_real_l(); 1480 //ASI_REAL_IO 1481 0x15: FailUnimpl::stdfa_real_io(); 1482 //ASI_REAL_IO_LITTLE 1483 0x1D: FailUnimpl::stdfa_real_io_l(); 1484 //ASI_PRIMARY 1485 0x80: FailUnimpl::stdfa_p(); 1486 //ASI_PRIMARY_LITTLE 1487 0x88: FailUnimpl::stdfa_pl(); 1488 //ASI_SECONDARY 1489 0x81: FailUnimpl::stdfa_s(); 1490 //ASI_SECONDARY_LITTLE 1491 0x89: FailUnimpl::stdfa_sl(); 1492 //ASI_PRIMARY_NO_FAULT 1493 0x82: FailUnimpl::stdfa_pnf(); 1494 //ASI_PRIMARY_NO_FAULT_LITTLE 1495 0x8A: FailUnimpl::stdfa_pnfl(); 1496 //ASI_SECONDARY_NO_FAULT 1497 0x83: FailUnimpl::stdfa_snf(); 1498 //ASI_SECONDARY_NO_FAULT_LITTLE 1499 0x8B: FailUnimpl::stdfa_snfl(); 1500 1501 format BlockStore { 1502 // STBLOCKF 1503 //ASI_BLOCK_AS_IF_USER_PRIMARY 1504 0x16: FailUnimpl::stblockf_aiup(); 1505 //ASI_BLOCK_AS_IF_USER_SECONDARY 1506 0x17: FailUnimpl::stblockf_aius(); 1507 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1508 0x1E: FailUnimpl::stblockf_aiupl(); 1509 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1510 0x1F: FailUnimpl::stblockf_aiusl(); 1511 //ASI_BLOCK_PRIMARY 1512 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 1513 //ASI_BLOCK_SECONDARY 1514 0xF1: FailUnimpl::stblockf_s(); 1515 //ASI_BLOCK_PRIMARY_LITTLE 1516 0xF8: FailUnimpl::stblockf_pl(); 1517 //ASI_BLOCK_SECONDARY_LITTLE 1518 0xF9: FailUnimpl::stblockf_sl(); 1519 } 1520 1521 //STSHORTF 1522 //ASI_FL8_PRIMARY 1523 0xD0: FailUnimpl::stshortf_8p(); 1524 //ASI_FL8_SECONDARY 1525 0xD1: FailUnimpl::stshortf_8s(); 1526 //ASI_FL8_PRIMARY_LITTLE 1527 0xD8: FailUnimpl::stshortf_8pl(); 1528 //ASI_FL8_SECONDARY_LITTLE 1529 0xD9: FailUnimpl::stshortf_8sl(); 1530 //ASI_FL16_PRIMARY 1531 0xD2: FailUnimpl::stshortf_16p(); 1532 //ASI_FL16_SECONDARY 1533 0xD3: FailUnimpl::stshortf_16s(); 1534 //ASI_FL16_PRIMARY_LITTLE 1535 0xDA: FailUnimpl::stshortf_16pl(); 1536 //ASI_FL16_SECONDARY_LITTLE 1537 0xDB: FailUnimpl::stshortf_16sl(); 1538 //Not an ASI which is legal with lddfa 1539 default: Trap::stdfa_bad_asi( 1540 {{fault = new DataAccessException;}}); 1541 } 1542 } 1543 0x3C: CasAlt::casa({{ 1544 mem_data = htog(Rs2.uw); 1545 Mem.uw = Rd.uw;}}, 1546 {{ 1547 uint32_t tmp = mem_data; 1548 Rd.uw = tmp; 1549 }}, {{EXT_ASI}}, MEM_SWAP_COND); 1550 0x3D: Nop::prefetcha({{ }}); 1551 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1552 Mem.udw = Rd.udw; }}, 1553 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 1554 } 1555 } 1556} 1557