decoder.isa revision 3598:cf3d84886c9f
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: decode A 49 { 50 0x0: bpa(19, {{ 51 NNPC = xc->readPC() + disp; 52 }}); 53 0x1: bpa(19, {{ 54 NPC = xc->readPC() + disp; 55 NNPC = NPC + 4; 56 }}, ',a'); 57 } 58 //Branch Never 59 0x0: decode A 60 { 61 0x0: bpn(19, {{ 62 NNPC = NNPC;//Don't do anything 63 }}); 64 0x1: bpn(19, {{ 65 NPC = xc->readNextPC() + 4; 66 NNPC = NPC + 4; 67 }}, ',a'); 68 } 69 default: decode BPCC 70 { 71 0x0: bpcci(19, {{ 72 if(passesCondition(Ccr<3:0>, COND2)) 73 NNPC = xc->readPC() + disp; 74 else 75 handle_annul 76 }}); 77 0x2: bpccx(19, {{ 78 if(passesCondition(Ccr<7:4>, COND2)) 79 NNPC = xc->readPC() + disp; 80 else 81 handle_annul 82 }}); 83 } 84 } 85 //bicc 86 0x2: decode COND2 87 { 88 //Branch Always 89 0x8: decode A 90 { 91 0x0: ba(22, {{ 92 NNPC = xc->readPC() + disp; 93 }}); 94 0x1: ba(22, {{ 95 NPC = xc->readPC() + disp; 96 NNPC = NPC + 4; 97 }}, ',a'); 98 } 99 //Branch Never 100 0x0: decode A 101 { 102 0x0: bn(22, {{ 103 NNPC = NNPC;//Don't do anything 104 }}); 105 0x1: bn(22, {{ 106 NPC = xc->readNextPC() + 4; 107 NNPC = NPC + 4; 108 }}, ',a'); 109 } 110 default: bicc(22, {{ 111 if(passesCondition(Ccr<3:0>, COND2)) 112 NNPC = xc->readPC() + disp; 113 else 114 handle_annul 115 }}); 116 } 117 } 118 0x3: decode RCOND2 119 { 120 format BranchSplit 121 { 122 0x1: bpreq({{ 123 if(Rs1.sdw == 0) 124 NNPC = xc->readPC() + disp; 125 else 126 handle_annul 127 }}); 128 0x2: bprle({{ 129 if(Rs1.sdw <= 0) 130 NNPC = xc->readPC() + disp; 131 else 132 handle_annul 133 }}); 134 0x3: bprl({{ 135 if(Rs1.sdw < 0) 136 NNPC = xc->readPC() + disp; 137 else 138 handle_annul 139 }}); 140 0x5: bprne({{ 141 if(Rs1.sdw != 0) 142 NNPC = xc->readPC() + disp; 143 else 144 handle_annul 145 }}); 146 0x6: bprg({{ 147 if(Rs1.sdw > 0) 148 NNPC = xc->readPC() + disp; 149 else 150 handle_annul 151 }}); 152 0x7: bprge({{ 153 if(Rs1.sdw >= 0) 154 NNPC = xc->readPC() + disp; 155 else 156 handle_annul 157 }}); 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 163 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 164 } 165 0x1: BranchN::call(30, {{ 166 R15 = xc->readPC(); 167 NNPC = R15 + disp; 168 }}); 169 0x2: decode OP3 { 170 format IntOp { 171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 175 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 176 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 177 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 178 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 179 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 180 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 181 0x0A: umul({{ 182 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 183 Y = Rd<63:32>; 184 }}); 185 0x0B: smul({{ 186 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 187 Y = Rd.sdw; 188 }}); 189 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 190 0x0D: udivx({{ 191 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 192 else Rd.udw = Rs1.udw / Rs2_or_imm13; 193 }}); 194 0x0E: udiv({{ 195 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 196 else 197 { 198 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 199 if(Rd.udw >> 32 != 0) 200 Rd.udw = 0xFFFFFFFF; 201 } 202 }}); 203 0x0F: sdiv({{ 204 if(Rs2_or_imm13.sdw == 0) 205 fault = new DivisionByZero; 206 else 207 { 208 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 209 if(Rd.udw<63:31> != 0) 210 Rd.udw = 0x7FFFFFFF; 211 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 212 Rd.udw = 0xFFFFFFFF80000000ULL; 213 } 214 }}); 215 } 216 format IntOpCc { 217 0x10: addcc({{ 218 int64_t resTemp, val2 = Rs2_or_imm13; 219 Rd = resTemp = Rs1 + val2;}}, 220 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 221 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 222 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 223 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 224 ); 225 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 226 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 227 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 228 0x14: subcc({{ 229 int64_t val2 = Rs2_or_imm13; 230 Rd = Rs1 - val2;}}, 231 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 232 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 233 {{(~(Rs1<63:1> + (~val2)<63:1> + 234 (Rs1 | ~val2)<0:>))<63:>}}, 235 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 236 ); 237 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 238 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 239 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 240 0x18: addccc({{ 241 int64_t resTemp, val2 = Rs2_or_imm13; 242 int64_t carryin = Ccr<0:0>; 243 Rd = resTemp = Rs1 + val2 + carryin;}}, 244 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 245 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 246 {{(Rs1<63:1> + val2<63:1> + 247 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 248 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 249 ); 250 0x1A: umulcc({{ 251 uint64_t resTemp; 252 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 253 Y = resTemp<63:32>;}}, 254 {{0}},{{0}},{{0}},{{0}}); 255 0x1B: smulcc({{ 256 int64_t resTemp; 257 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 258 Y = resTemp<63:32>;}}, 259 {{0}},{{0}},{{0}},{{0}}); 260 0x1C: subccc({{ 261 int64_t resTemp, val2 = Rs2_or_imm13; 262 int64_t carryin = Ccr<0:0>; 263 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 264 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 265 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 266 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 267 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 268 ); 269 0x1D: udivxcc({{ 270 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 271 else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 272 ,{{0}},{{0}},{{0}},{{0}}); 273 0x1E: udivcc({{ 274 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 275 int32_t overflow = 0; 276 if(val2 == 0) fault = new DivisionByZero; 277 else 278 { 279 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 280 overflow = (resTemp<63:32> != 0); 281 if(overflow) Rd = resTemp = 0xFFFFFFFF; 282 else Rd = resTemp; 283 } }}, 284 {{0}}, 285 {{overflow}}, 286 {{0}}, 287 {{0}} 288 ); 289 0x1F: sdivcc({{ 290 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 291 bool overflow = false, underflow = false; 292 if(val2 == 0) fault = new DivisionByZero; 293 else 294 { 295 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 296 overflow = (Rd<63:31> != 0); 297 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 298 if(overflow) Rd = 0x7FFFFFFF; 299 else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 300 } }}, 301 {{0}}, 302 {{overflow || underflow}}, 303 {{0}}, 304 {{0}} 305 ); 306 0x20: taddcc({{ 307 int64_t resTemp, val2 = Rs2_or_imm13; 308 Rd = resTemp = Rs1 + val2; 309 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 310 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 311 {{overflow}}, 312 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 313 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 314 ); 315 0x21: tsubcc({{ 316 int64_t resTemp, val2 = Rs2_or_imm13; 317 Rd = resTemp = Rs1 + val2; 318 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 319 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 320 {{overflow}}, 321 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 322 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 323 ); 324 0x22: taddcctv({{ 325 int64_t val2 = Rs2_or_imm13; 326 Rd = Rs1 + val2; 327 int32_t overflow = Rs1<1:0> || val2<1:0> || 328 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 329 if(overflow) fault = new TagOverflow;}}, 330 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 331 {{overflow}}, 332 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 333 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 334 ); 335 0x23: tsubcctv({{ 336 int64_t resTemp, val2 = Rs2_or_imm13; 337 Rd = resTemp = Rs1 + val2; 338 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 339 if(overflow) fault = new TagOverflow;}}, 340 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 341 {{overflow}}, 342 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 343 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 344 ); 345 0x24: mulscc({{ 346 int64_t resTemp, multiplicand = Rs2_or_imm13; 347 int32_t multiplier = Rs1<31:0>; 348 int32_t savedLSB = Rs1<0:>; 349 multiplier = multiplier<31:1> | 350 ((Ccr<3:3> 351 ^ Ccr<1:1>) << 32); 352 if(!Y<0:>) 353 multiplicand = 0; 354 Rd = resTemp = multiplicand + multiplier; 355 Y = Y<31:1> | (savedLSB << 31);}}, 356 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 357 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 358 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 359 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 360 ); 361 } 362 format IntOp 363 { 364 0x25: decode X { 365 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 366 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 367 } 368 0x26: decode X { 369 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 370 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 371 } 372 0x27: decode X { 373 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 374 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 375 } 376 0x28: decode RS1 { 377 0x00: NoPriv::rdy({{Rd = Y;}}); 378 //1 should cause an illegal instruction exception 379 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 380 0x03: NoPriv::rdasi({{Rd = Asi;}}); 381 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 382 0x05: NoPriv::rdpc({{ 383 if(Pstate<3:>) 384 Rd = (xc->readPC())<31:0>; 385 else 386 Rd = xc->readPC();}}); 387 0x06: NoPriv::rdfprs({{ 388 //Wait for all fpops to finish. 389 Rd = Fprs; 390 }}); 391 //7-14 should cause an illegal instruction exception 392 0x0F: decode I { 393 0x0: Nop::stbar({{/*stuff*/}}); 394 0x1: Nop::membar({{/*stuff*/}}); 395 } 396 0x10: Priv::rdpcr({{Rd = Pcr;}}); 397 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 398 //0x12 should cause an illegal instruction exception 399 0x13: NoPriv::rdgsr({{ 400 if(Fprs<2:> == 0 || Pstate<4:> == 0) 401 Rd = Gsr; 402 else 403 fault = new FpDisabled; 404 }}); 405 //0x14-0x15 should cause an illegal instruction exception 406 0x16: Priv::rdsoftint({{Rd = Softint;}}); 407 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 408 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 409 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 410 0x1A: Priv::rdstrand_sts_reg({{ 411 if(Pstate<2:> && !Hpstate<2:>) 412 Rd = StrandStsReg<0:>; 413 else 414 Rd = StrandStsReg; 415 }}); 416 //0x1A is supposed to be reserved, but it reads the strand 417 //status register. 418 //0x1B-0x1F should cause an illegal instruction exception 419 } 420 0x29: decode RS1 { 421 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 422 0x01: HPriv::rdhprhtstate({{ 423 if(Tl == 0) 424 return new IllegalInstruction; 425 Rd = Htstate; 426 }}); 427 //0x02 should cause an illegal instruction exception 428 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 429 //0x04 should cause an illegal instruction exception 430 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 431 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 432 //0x07-0x1E should cause an illegal instruction exception 433 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 434 } 435 0x2A: decode RS1 { 436 0x00: Priv::rdprtpc({{ 437 if(Tl == 0) 438 return new IllegalInstruction; 439 Rd = Tpc; 440 }}); 441 0x01: Priv::rdprtnpc({{ 442 if(Tl == 0) 443 return new IllegalInstruction; 444 Rd = Tnpc; 445 }}); 446 0x02: Priv::rdprtstate({{ 447 if(Tl == 0) 448 return new IllegalInstruction; 449 Rd = Tstate; 450 }}); 451 0x03: Priv::rdprtt({{ 452 if(Tl == 0) 453 return new IllegalInstruction; 454 Rd = Tt; 455 }}); 456 0x04: Priv::rdprtick({{Rd = Tick;}}); 457 0x05: Priv::rdprtba({{Rd = Tba;}}); 458 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 459 0x07: Priv::rdprtl({{Rd = Tl;}}); 460 0x08: Priv::rdprpil({{Rd = Pil;}}); 461 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 462 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 463 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 464 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 465 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 466 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 467 //0x0F should cause an illegal instruction exception 468 0x10: Priv::rdprgl({{Rd = Gl;}}); 469 //0x11-0x1F should cause an illegal instruction exception 470 } 471 0x2B: BasicOperate::flushw({{ 472 if(NWindows - 2 - Cansave == 0) 473 { 474 if(Otherwin) 475 fault = new SpillNOther(Wstate<5:3>); 476 else 477 fault = new SpillNNormal(Wstate<2:0>); 478 } 479 }}); 480 0x2C: decode MOVCC3 481 { 482 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 483 0x1: decode CC 484 { 485 0x0: movcci({{ 486 if(passesCondition(Ccr<3:0>, COND4)) 487 Rd = Rs2_or_imm11; 488 else 489 Rd = Rd; 490 }}); 491 0x2: movccx({{ 492 if(passesCondition(Ccr<7:4>, COND4)) 493 Rd = Rs2_or_imm11; 494 else 495 Rd = Rd; 496 }}); 497 } 498 } 499 0x2D: sdivx({{ 500 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 501 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 502 }}); 503 0x2E: decode RS1 { 504 0x0: IntOp::popc({{ 505 int64_t count = 0; 506 uint64_t temp = Rs2_or_imm13; 507 //Count the 1s in the front 4bits until none are left 508 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 509 while(temp) 510 { 511 count += oneBits[temp & 0xF]; 512 temp = temp >> 4; 513 } 514 Rd = count; 515 }}); 516 } 517 0x2F: decode RCOND3 518 { 519 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 520 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 521 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 522 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 523 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 524 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 525 } 526 0x30: decode RD { 527 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 528 //0x01 should cause an illegal instruction exception 529 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 530 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 531 //0x04-0x05 should cause an illegal instruction exception 532 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 533 //0x07-0x0E should cause an illegal instruction exception 534 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 535 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 536 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 537 //0x12 should cause an illegal instruction exception 538 0x13: NoPriv::wrgsr({{ 539 if(Fprs<2:> == 0 || Pstate<4:> == 0) 540 return new FpDisabled; 541 Gsr = Rs1 ^ Rs2_or_imm13; 542 }}); 543 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 544 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 545 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 546 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 547 0x18: NoPriv::wrstick({{ 548 if(!Hpstate<2:>) 549 return new IllegalInstruction; 550 Stick = Rs1 ^ Rs2_or_imm13; 551 }}); 552 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 553 0x1A: Priv::wrstrand_sts_reg({{ 554 if(Pstate<2:> && !Hpstate<2:>) 555 StrandStsReg = StrandStsReg<63:1> | 556 (Rs1 ^ Rs2_or_imm13)<0:>; 557 else 558 StrandStsReg = Rs1 ^ Rs2_or_imm13; 559 }}); 560 //0x1A is supposed to be reserved, but it writes the strand 561 //status register. 562 //0x1B-0x1F should cause an illegal instruction exception 563 } 564 0x31: decode FCN { 565 0x0: Priv::saved({{ 566 assert(Cansave < NWindows - 2); 567 assert(Otherwin || Canrestore); 568 Cansave = Cansave + 1; 569 if(Otherwin == 0) 570 Canrestore = Canrestore - 1; 571 else 572 Otherwin = Otherwin - 1; 573 }}); 574 0x1: Priv::restored({{ 575 assert(Cansave || Otherwin); 576 assert(Canrestore < NWindows - 2); 577 Canrestore = Canrestore + 1; 578 if(Otherwin == 0) 579 Cansave = Cansave - 1; 580 else 581 Otherwin = Otherwin - 1; 582 }}); 583 } 584 0x32: decode RD { 585 0x00: Priv::wrprtpc({{ 586 if(Tl == 0) 587 return new IllegalInstruction; 588 else 589 Tpc = Rs1 ^ Rs2_or_imm13; 590 }}); 591 0x01: Priv::wrprtnpc({{ 592 if(Tl == 0) 593 return new IllegalInstruction; 594 else 595 Tnpc = Rs1 ^ Rs2_or_imm13; 596 }}); 597 0x02: Priv::wrprtstate({{ 598 if(Tl == 0) 599 return new IllegalInstruction; 600 else 601 Tstate = Rs1 ^ Rs2_or_imm13; 602 }}); 603 0x03: Priv::wrprtt({{ 604 if(Tl == 0) 605 return new IllegalInstruction; 606 else 607 Tt = Rs1 ^ Rs2_or_imm13; 608 }}); 609 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 610 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 611 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 612 0x07: Priv::wrprtl({{ 613 if(Pstate<2:> && !Hpstate<2:>) 614 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 615 else 616 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 617 }}); 618 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 619 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 620 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 621 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 622 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 623 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 624 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 625 //0x0F should cause an illegal instruction exception 626 0x10: Priv::wrprgl({{ 627 if(Pstate<2:> && !Hpstate<2:>) 628 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 629 else 630 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 631 }}); 632 //0x11-0x1F should cause an illegal instruction exception 633 } 634 0x33: decode RD { 635 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 636 0x01: HPriv::wrhprhtstate({{ 637 if(Tl == 0) 638 return new IllegalInstruction; 639 Htstate = Rs1 ^ Rs2_or_imm13; 640 }}); 641 //0x02 should cause an illegal instruction exception 642 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 643 //0x04 should cause an illegal instruction exception 644 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 645 //0x06-0x01D should cause an illegal instruction exception 646 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 647 } 648 0x34: decode OPF{ 649 format BasicOperate{ 650 0x01: fmovs({{ 651 Frds.uw = Frs2s.uw; 652 //fsr.ftt = fsr.cexc = 0 653 Fsr &= ~(7 << 14); 654 Fsr &= ~(0x1F); 655 }}); 656 0x02: fmovd({{ 657 Frd.udw = Frs2.udw; 658 //fsr.ftt = fsr.cexc = 0 659 Fsr &= ~(7 << 14); 660 Fsr &= ~(0x1F); 661 }}); 662 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 663 0x05: fnegs({{ 664 Frds.uw = Frs2s.uw ^ (1UL << 31); 665 //fsr.ftt = fsr.cexc = 0 666 Fsr &= ~(7 << 14); 667 Fsr &= ~(0x1F); 668 }}); 669 0x06: fnegd({{ 670 Frd.udw = Frs2.udw ^ (1ULL << 63); 671 //fsr.ftt = fsr.cexc = 0 672 Fsr &= ~(7 << 14); 673 Fsr &= ~(0x1F); 674 }}); 675 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 676 0x09: fabss({{ 677 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 678 //fsr.ftt = fsr.cexc = 0 679 Fsr &= ~(7 << 14); 680 Fsr &= ~(0x1F); 681 }}); 682 0x0A: fabsd({{ 683 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 684 //fsr.ftt = fsr.cexc = 0 685 Fsr &= ~(7 << 14); 686 Fsr &= ~(0x1F); 687 }}); 688 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 689 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); 690 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 691 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 692 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 693 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 694 0x43: Trap::faddq({{fault = new FpDisabled;}}); 695 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 696 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 697 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 698 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 699 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 700 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 701 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 702 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 703 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 704 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 705 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 706 0x81: fstox({{ 707 Frd.df = (double)static_cast<int64_t>(Frs2s.sf); 708 }}); 709 0x82: fdtox({{ 710 Frd.df = (double)static_cast<int64_t>(Frs2.df); 711 }}); 712 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 713 0x84: fxtos({{ 714 Frds.sf = static_cast<float>((int64_t)Frs2.df); 715 }}); 716 0x88: fxtod({{ 717 Frd.df = static_cast<double>((int64_t)Frs2.df); 718 }}); 719 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 720 0xC4: fitos({{ 721 Frds.sf = static_cast<float>((int32_t)Frs2s.sf); 722 }}); 723 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 724 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 725 0xC8: fitod({{ 726 Frd.df = static_cast<double>((int32_t)Frs2s.sf); 727 }}); 728 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 729 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 730 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 731 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 732 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 733 0xD1: fstoi({{ 734 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf); 735 }}); 736 0xD2: fdtoi({{ 737 Frds.sf = (float)static_cast<int32_t>(Frs2.df); 738 }}); 739 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 740 default: Trap::fpop1({{fault = new FpDisabled;}}); 741 } 742 } 743 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 744 //This used to be just impdep1, but now it's a whole bunch 745 //of instructions 746 0x36: decode OPF{ 747 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 748 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 749 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 750 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 751 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 752 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 753 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 754 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 755 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 756 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 757 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 758 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 759 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 760 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 761 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 762 0x18: BasicOperate::alignaddr({{ 763 uint64_t sum = Rs1 + Rs2; 764 Rd = sum & ~7; 765 Gsr = (Gsr & ~7) | (sum & 7); 766 }}); 767 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 768 0x1A: BasicOperate::alignaddresslittle({{ 769 uint64_t sum = Rs1 + Rs2; 770 Rd = sum & ~7; 771 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 772 }}); 773 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 774 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 775 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 776 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 777 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 778 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 779 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 780 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 781 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 782 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 783 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 784 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 785 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 786 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 787 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 788 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 789 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 790 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 791 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 792 0x48: BasicOperate::faligndata({{ 793 uint64_t msbX = Frs1.udw; 794 uint64_t lsbX = Frs2.udw; 795 //Some special cases need to be split out, first 796 //because they're the most likely to be used, and 797 //second because otherwise, we end up shifting by 798 //greater than the width of the type being shifted, 799 //namely 64, which produces undefined results according 800 //to the C standard. 801 switch(Gsr<2:0>) 802 { 803 case 0: 804 Frd.udw = msbX; 805 break; 806 case 8: 807 Frd.udw = lsbX; 808 break; 809 default: 810 uint64_t msbShift = Gsr<2:0> * 8; 811 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 812 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 813 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 814 Frd.udw = ((msbX & msbMask) << msbShift) | 815 ((lsbX & lsbMask) >> lsbShift); 816 } 817 }}); 818 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 819 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 820 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 821 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 822 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 823 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 824 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 825 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 826 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 827 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 828 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 829 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 830 0x61: BasicOperate::fzeros({{Frds.sf = 0;}}); 831 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 832 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 833 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 834 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 835 0x66: BasicOperate::fnot2({{ 836 Frd.df = (double)(~((uint64_t)Frs2.df)); 837 }}); 838 0x67: BasicOperate::fnot2s({{ 839 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 840 }}); 841 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 842 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 843 0x6A: BasicOperate::fnot1({{ 844 Frd.df = (double)(~((uint64_t)Frs1.df)); 845 }}); 846 0x6B: BasicOperate::fnot1s({{ 847 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 848 }}); 849 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 850 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 851 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 852 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 853 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 854 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 855 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 856 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 857 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); 858 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); 859 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 860 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 861 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); 862 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); 863 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 864 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 865 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 866 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 867 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 868 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 869 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 870 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 871 } 872 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 873 0x38: Branch::jmpl({{ 874 Addr target = Rs1 + Rs2_or_imm13; 875 if(target & 0x3) 876 fault = new MemAddressNotAligned; 877 else 878 { 879 Rd = xc->readPC(); 880 NNPC = target; 881 } 882 }}); 883 0x39: Branch::return({{ 884 //If both MemAddressNotAligned and 885 //a fill trap happen, it's not clear 886 //which one should be returned. 887 Addr target = Rs1 + Rs2_or_imm13; 888 if(target & 0x3) 889 fault = new MemAddressNotAligned; 890 else 891 NNPC = target; 892 if(fault == NoFault) 893 { 894 if(Canrestore == 0) 895 { 896 if(Otherwin) 897 fault = new FillNOther(Wstate<5:3>); 898 else 899 fault = new FillNNormal(Wstate<2:0>); 900 } 901 else 902 { 903 //CWP should be set directly so that it always happens 904 //Also, this will allow writing to the new window and 905 //reading from the old one 906 Cwp = (Cwp - 1 + NWindows) % NWindows; 907 Cansave = Cansave + 1; 908 Canrestore = Canrestore - 1; 909 //This is here to make sure the CWP is written 910 //no matter what. This ensures that the results 911 //are written in the new window as well. 912 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 913 } 914 } 915 }}); 916 0x3A: decode CC 917 { 918 0x0: Trap::tcci({{ 919 if(passesCondition(Ccr<3:0>, COND2)) 920 { 921#if FULL_SYSTEM 922 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 923 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 924 fault = new TrapInstruction(lTrapNum); 925#else 926 DPRINTF(Sparc, "The syscall number is %d\n", R1); 927 xc->syscall(R1); 928#endif 929 } 930 }}); 931 0x2: Trap::tccx({{ 932 if(passesCondition(Ccr<7:4>, COND2)) 933 { 934#if FULL_SYSTEM 935 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 936 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 937 fault = new TrapInstruction(lTrapNum); 938#else 939 DPRINTF(Sparc, "The syscall number is %d\n", R1); 940 xc->syscall(R1); 941#endif 942 } 943 }}); 944 } 945 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 946 0x3C: save({{ 947 //CWP should be set directly so that it always happens 948 //Also, this will allow writing to the new window and 949 //reading from the old one 950 if(Cansave == 0) 951 { 952 if(Otherwin) 953 fault = new SpillNOther(Wstate<5:3>); 954 else 955 fault = new SpillNNormal(Wstate<2:0>); 956 //Cwp = (Cwp + 2) % NWindows; 957 } 958 else if(Cleanwin - Canrestore == 0) 959 { 960 //Cwp = (Cwp + 1) % NWindows; 961 fault = new CleanWindow; 962 } 963 else 964 { 965 Cwp = (Cwp + 1) % NWindows; 966 Rd = Rs1 + Rs2_or_imm13; 967 Cansave = Cansave - 1; 968 Canrestore = Canrestore + 1; 969 //This is here to make sure the CWP is written 970 //no matter what. This ensures that the results 971 //are written in the new window as well. 972 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 973 } 974 }}); 975 0x3D: restore({{ 976 if(Canrestore == 0) 977 { 978 if(Otherwin) 979 fault = new FillNOther(Wstate<5:3>); 980 else 981 fault = new FillNNormal(Wstate<2:0>); 982 } 983 else 984 { 985 //CWP should be set directly so that it always happens 986 //Also, this will allow writing to the new window and 987 //reading from the old one 988 Cwp = (Cwp - 1 + NWindows) % NWindows; 989 Rd = Rs1 + Rs2_or_imm13; 990 Cansave = Cansave + 1; 991 Canrestore = Canrestore - 1; 992 //This is here to make sure the CWP is written 993 //no matter what. This ensures that the results 994 //are written in the new window as well. 995 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 996 } 997 }}); 998 0x3E: decode FCN { 999 0x0: Priv::done({{ 1000 if(Tl == 0) 1001 return new IllegalInstruction; 1002 1003 Cwp = Tstate<4:0>; 1004 Pstate = Tstate<20:8>; 1005 Asi = Tstate<31:24>; 1006 Ccr = Tstate<39:32>; 1007 Gl = Tstate<42:40>; 1008 NPC = Tnpc; 1009 NNPC = Tnpc + 4; 1010 Tl = Tl - 1; 1011 }}); 1012 0x1: Priv::retry({{ 1013 if(Tl == 0) 1014 return new IllegalInstruction; 1015 Cwp = Tstate<4:0>; 1016 Pstate = Tstate<20:8>; 1017 Asi = Tstate<31:24>; 1018 Ccr = Tstate<39:32>; 1019 Gl = Tstate<42:40>; 1020 NPC = Tpc; 1021 NNPC = Tnpc; 1022 Tl = Tl - 1; 1023 }}); 1024 } 1025 } 1026 } 1027 0x3: decode OP3 { 1028 format Load { 1029 0x00: lduw({{Rd = Mem.uw;}}); 1030 0x01: ldub({{Rd = Mem.ub;}}); 1031 0x02: lduh({{Rd = Mem.uhw;}}); 1032 0x03: ldd({{ 1033 uint64_t val = Mem.udw; 1034 RdLow = val<31:0>; 1035 RdHigh = val<63:32>; 1036 }}); 1037 } 1038 format Store { 1039 0x04: stw({{Mem.uw = Rd.sw;}}); 1040 0x05: stb({{Mem.ub = Rd.sb;}}); 1041 0x06: sth({{Mem.uhw = Rd.shw;}}); 1042 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 1043 } 1044 format Load { 1045 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1046 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1047 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1048 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1049 } 1050 0x0D: LoadStore::ldstub( 1051 {{Rd = Mem.ub;}}, 1052 {{Mem.ub = 0xFF;}}); 1053 0x0E: Store::stx({{Mem.udw = Rd}}); 1054 0x0F: LoadStore::swap( 1055 {{uReg0 = Rd.uw; 1056 Rd.uw = Mem.uw;}}, 1057 {{Mem.uw = uReg0;}}); 1058 format Load { 1059 0x10: lduwa({{Rd = Mem.uw;}}); 1060 0x11: lduba({{Rd = Mem.ub;}}); 1061 0x12: lduha({{Rd = Mem.uhw;}}); 1062 0x13: ldda({{ 1063 uint64_t val = Mem.udw; 1064 RdLow = val<31:0>; 1065 RdHigh = val<63:32>; 1066 }}); 1067 } 1068 format Store { 1069 0x14: stwa({{Mem.uw = Rd;}}); 1070 0x15: stba({{Mem.ub = Rd;}}); 1071 0x16: stha({{Mem.uhw = Rd;}}); 1072 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); 1073 } 1074 format Load { 1075 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1076 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1077 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1078 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 1079 } 1080 0x1D: LoadStore::ldstuba( 1081 {{Rd = Mem.ub;}}, 1082 {{Mem.ub = 0xFF}}); 1083 0x1E: Store::stxa({{Mem.udw = Rd}}); 1084 0x1F: LoadStore::swapa( 1085 {{uReg0 = Rd.uw; 1086 Rd.uw = Mem.uw;}}, 1087 {{Mem.uw = uReg0;}}); 1088 format Trap { 1089 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1090 0x21: decode X { 1091 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1092 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1093 } 1094 0x22: ldqf({{fault = new FpDisabled;}}); 1095 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1096 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1097 0x25: decode X { 1098 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1099 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1100 } 1101 0x26: stqf({{fault = new FpDisabled;}}); 1102 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1103 0x2D: Nop::prefetch({{ }}); 1104 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); 1105 0x32: ldqfa({{fault = new FpDisabled;}}); 1106 format LoadAlt { 1107 0x33: decode EXT_ASI { 1108 //ASI_NUCLEUS 1109 0x04: FailUnimpl::lddfa_n(); 1110 //ASI_NUCLEUS_LITTLE 1111 0x0C: FailUnimpl::lddfa_nl(); 1112 //ASI_AS_IF_USER_PRIMARY 1113 0x10: FailUnimpl::lddfa_aiup(); 1114 //ASI_AS_IF_USER_PRIMARY_LITTLE 1115 0x18: FailUnimpl::lddfa_aiupl(); 1116 //ASI_AS_IF_USER_SECONDARY 1117 0x11: FailUnimpl::lddfa_aius(); 1118 //ASI_AS_IF_USER_SECONDARY_LITTLE 1119 0x19: FailUnimpl::lddfa_aiusl(); 1120 //ASI_REAL 1121 0x14: FailUnimpl::lddfa_real(); 1122 //ASI_REAL_LITTLE 1123 0x1C: FailUnimpl::lddfa_real_l(); 1124 //ASI_REAL_IO 1125 0x15: FailUnimpl::lddfa_real_io(); 1126 //ASI_REAL_IO_LITTLE 1127 0x1D: FailUnimpl::lddfa_real_io_l(); 1128 //ASI_PRIMARY 1129 0x80: FailUnimpl::lddfa_p(); 1130 //ASI_PRIMARY_LITTLE 1131 0x88: FailUnimpl::lddfa_pl(); 1132 //ASI_SECONDARY 1133 0x81: FailUnimpl::lddfa_s(); 1134 //ASI_SECONDARY_LITTLE 1135 0x89: FailUnimpl::lddfa_sl(); 1136 //ASI_PRIMARY_NO_FAULT 1137 0x82: FailUnimpl::lddfa_pnf(); 1138 //ASI_PRIMARY_NO_FAULT_LITTLE 1139 0x8A: FailUnimpl::lddfa_pnfl(); 1140 //ASI_SECONDARY_NO_FAULT 1141 0x83: FailUnimpl::lddfa_snf(); 1142 //ASI_SECONDARY_NO_FAULT_LITTLE 1143 0x8B: FailUnimpl::lddfa_snfl(); 1144 1145 format BlockLoad { 1146 // LDBLOCKF 1147 //ASI_BLOCK_AS_IF_USER_PRIMARY 1148 0x16: FailUnimpl::ldblockf_aiup(); 1149 //ASI_BLOCK_AS_IF_USER_SECONDARY 1150 0x17: FailUnimpl::ldblockf_aius(); 1151 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1152 0x1E: FailUnimpl::ldblockf_aiupl(); 1153 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1154 0x1F: FailUnimpl::ldblockf_aiusl(); 1155 //ASI_BLOCK_PRIMARY 1156 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 1157 //ASI_BLOCK_SECONDARY 1158 0xF1: FailUnimpl::ldblockf_s(); 1159 //ASI_BLOCK_PRIMARY_LITTLE 1160 0xF8: FailUnimpl::ldblockf_pl(); 1161 //ASI_BLOCK_SECONDARY_LITTLE 1162 0xF9: FailUnimpl::ldblockf_sl(); 1163 } 1164 1165 //LDSHORTF 1166 //ASI_FL8_PRIMARY 1167 0xD0: FailUnimpl::ldshortf_8p(); 1168 //ASI_FL8_SECONDARY 1169 0xD1: FailUnimpl::ldshortf_8s(); 1170 //ASI_FL8_PRIMARY_LITTLE 1171 0xD8: FailUnimpl::ldshortf_8pl(); 1172 //ASI_FL8_SECONDARY_LITTLE 1173 0xD9: FailUnimpl::ldshortf_8sl(); 1174 //ASI_FL16_PRIMARY 1175 0xD2: FailUnimpl::ldshortf_16p(); 1176 //ASI_FL16_SECONDARY 1177 0xD3: FailUnimpl::ldshortf_16s(); 1178 //ASI_FL16_PRIMARY_LITTLE 1179 0xDA: FailUnimpl::ldshortf_16pl(); 1180 //ASI_FL16_SECONDARY_LITTLE 1181 0xDB: FailUnimpl::ldshortf_16sl(); 1182 //Not an ASI which is legal with lddfa 1183 default: Trap::lddfa_bad_asi( 1184 {{fault = new DataAccessException;}}); 1185 } 1186 } 1187 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); 1188 0x36: stqfa({{fault = new FpDisabled;}}); 1189 format StoreAlt { 1190 0x37: decode EXT_ASI { 1191 //ASI_NUCLEUS 1192 0x04: FailUnimpl::stdfa_n(); 1193 //ASI_NUCLEUS_LITTLE 1194 0x0C: FailUnimpl::stdfa_nl(); 1195 //ASI_AS_IF_USER_PRIMARY 1196 0x10: FailUnimpl::stdfa_aiup(); 1197 //ASI_AS_IF_USER_PRIMARY_LITTLE 1198 0x18: FailUnimpl::stdfa_aiupl(); 1199 //ASI_AS_IF_USER_SECONDARY 1200 0x11: FailUnimpl::stdfa_aius(); 1201 //ASI_AS_IF_USER_SECONDARY_LITTLE 1202 0x19: FailUnimpl::stdfa_aiusl(); 1203 //ASI_REAL 1204 0x14: FailUnimpl::stdfa_real(); 1205 //ASI_REAL_LITTLE 1206 0x1C: FailUnimpl::stdfa_real_l(); 1207 //ASI_REAL_IO 1208 0x15: FailUnimpl::stdfa_real_io(); 1209 //ASI_REAL_IO_LITTLE 1210 0x1D: FailUnimpl::stdfa_real_io_l(); 1211 //ASI_PRIMARY 1212 0x80: FailUnimpl::stdfa_p(); 1213 //ASI_PRIMARY_LITTLE 1214 0x88: FailUnimpl::stdfa_pl(); 1215 //ASI_SECONDARY 1216 0x81: FailUnimpl::stdfa_s(); 1217 //ASI_SECONDARY_LITTLE 1218 0x89: FailUnimpl::stdfa_sl(); 1219 //ASI_PRIMARY_NO_FAULT 1220 0x82: FailUnimpl::stdfa_pnf(); 1221 //ASI_PRIMARY_NO_FAULT_LITTLE 1222 0x8A: FailUnimpl::stdfa_pnfl(); 1223 //ASI_SECONDARY_NO_FAULT 1224 0x83: FailUnimpl::stdfa_snf(); 1225 //ASI_SECONDARY_NO_FAULT_LITTLE 1226 0x8B: FailUnimpl::stdfa_snfl(); 1227 1228 format BlockStore { 1229 // STBLOCKF 1230 //ASI_BLOCK_AS_IF_USER_PRIMARY 1231 0x16: FailUnimpl::stblockf_aiup(); 1232 //ASI_BLOCK_AS_IF_USER_SECONDARY 1233 0x17: FailUnimpl::stblockf_aius(); 1234 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1235 0x1E: FailUnimpl::stblockf_aiupl(); 1236 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1237 0x1F: FailUnimpl::stblockf_aiusl(); 1238 //ASI_BLOCK_PRIMARY 1239 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1240 //ASI_BLOCK_SECONDARY 1241 0xF1: FailUnimpl::stblockf_s(); 1242 //ASI_BLOCK_PRIMARY_LITTLE 1243 0xF8: FailUnimpl::stblockf_pl(); 1244 //ASI_BLOCK_SECONDARY_LITTLE 1245 0xF9: FailUnimpl::stblockf_sl(); 1246 } 1247 1248 //STSHORTF 1249 //ASI_FL8_PRIMARY 1250 0xD0: FailUnimpl::stshortf_8p(); 1251 //ASI_FL8_SECONDARY 1252 0xD1: FailUnimpl::stshortf_8s(); 1253 //ASI_FL8_PRIMARY_LITTLE 1254 0xD8: FailUnimpl::stshortf_8pl(); 1255 //ASI_FL8_SECONDARY_LITTLE 1256 0xD9: FailUnimpl::stshortf_8sl(); 1257 //ASI_FL16_PRIMARY 1258 0xD2: FailUnimpl::stshortf_16p(); 1259 //ASI_FL16_SECONDARY 1260 0xD3: FailUnimpl::stshortf_16s(); 1261 //ASI_FL16_PRIMARY_LITTLE 1262 0xDA: FailUnimpl::stshortf_16pl(); 1263 //ASI_FL16_SECONDARY_LITTLE 1264 0xDB: FailUnimpl::stshortf_16sl(); 1265 //Not an ASI which is legal with lddfa 1266 default: Trap::stdfa_bad_asi( 1267 {{fault = new DataAccessException;}}); 1268 } 1269 } 1270 0x3C: Cas::casa( 1271 {{uReg0 = Mem.uw;}}, 1272 {{if(Rs2.uw == uReg0) 1273 Mem.uw = Rd.uw; 1274 else 1275 storeCond = false; 1276 Rd.uw = uReg0;}}); 1277 0x3D: Nop::prefetcha({{ }}); 1278 0x3E: Cas::casxa( 1279 {{uReg0 = Mem.udw;}}, 1280 {{if(Rs2 == uReg0) 1281 Mem.udw = Rd; 1282 else 1283 storeCond = false; 1284 Rd = uReg0;}}); 1285 } 1286 } 1287} 1288