decoder.isa revision 3417:41aab2d0319b
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 0x1: decode COND2 45 { 46 //Branch Always 47 0x8: decode A 48 { 49 0x0: b(19, {{ 50 NNPC = xc->readPC() + disp; 51 }}); 52 0x1: b(19, {{ 53 NPC = xc->readPC() + disp; 54 NNPC = NPC + 4; 55 }}, ',a'); 56 } 57 //Branch Never 58 0x0: decode A 59 { 60 0x0: bn(19, {{ 61 NNPC = NNPC;//Don't do anything 62 }}); 63 0x1: bn(19, {{ 64 NPC = xc->readNextPC() + 4; 65 NNPC = NPC + 4; 66 }}, ',a'); 67 } 68 default: decode BPCC 69 { 70 0x0: bpcci(19, {{ 71 if(passesCondition(Ccr<3:0>, COND2)) 72 NNPC = xc->readPC() + disp; 73 else 74 handle_annul 75 }}); 76 0x2: bpccx(19, {{ 77 if(passesCondition(Ccr<7:4>, COND2)) 78 NNPC = xc->readPC() + disp; 79 else 80 handle_annul 81 }}); 82 } 83 } 84 0x2: bicc(22, {{ 85 if(passesCondition(Ccr<3:0>, COND2)) 86 NNPC = xc->readPC() + disp; 87 else 88 handle_annul 89 }}); 90 } 91 0x3: decode RCOND2 92 { 93 format BranchSplit 94 { 95 0x1: bpreq({{ 96 if(Rs1.sdw == 0) 97 NNPC = xc->readPC() + disp; 98 else 99 handle_annul 100 }}); 101 0x2: bprle({{ 102 if(Rs1.sdw <= 0) 103 NNPC = xc->readPC() + disp; 104 else 105 handle_annul 106 }}); 107 0x3: bprl({{ 108 if(Rs1.sdw < 0) 109 NNPC = xc->readPC() + disp; 110 else 111 handle_annul 112 }}); 113 0x5: bprne({{ 114 if(Rs1.sdw != 0) 115 NNPC = xc->readPC() + disp; 116 else 117 handle_annul 118 }}); 119 0x6: bprg({{ 120 if(Rs1.sdw > 0) 121 NNPC = xc->readPC() + disp; 122 else 123 handle_annul 124 }}); 125 0x7: bprge({{ 126 if(Rs1.sdw >= 0) 127 NNPC = xc->readPC() + disp; 128 else 129 handle_annul 130 }}); 131 } 132 } 133 //SETHI (or NOP if rd == 0 and imm == 0) 134 0x4: SetHi::sethi({{Rd.udw = imm;}}); 135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 136 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 137 } 138 0x1: BranchN::call(30, {{ 139 R15 = xc->readPC(); 140 NNPC = R15 + disp; 141 }}); 142 0x2: decode OP3 { 143 format IntOp { 144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 154 0x0A: umul({{ 155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 156 Y = Rd<63:32>; 157 }}); 158 0x0B: smul({{ 159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 160 Y = Rd.sdw; 161 }}); 162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 163 0x0D: udivx({{ 164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 165 else Rd.udw = Rs1.udw / Rs2_or_imm13; 166 }}); 167 0x0E: udiv({{ 168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 169 else 170 { 171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 172 if(Rd.udw >> 32 != 0) 173 Rd.udw = 0xFFFFFFFF; 174 } 175 }}); 176 0x0F: sdiv({{ 177 if(Rs2_or_imm13.sdw == 0) 178 fault = new DivisionByZero; 179 else 180 { 181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 182 if(Rd.udw<63:31> != 0) 183 Rd.udw = 0x7FFFFFFF; 184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 185 Rd.udw = 0xFFFFFFFF80000000ULL; 186 } 187 }}); 188 } 189 format IntOpCc { 190 0x10: addcc({{ 191 int64_t resTemp, val2 = Rs2_or_imm13; 192 Rd = resTemp = Rs1 + val2;}}, 193 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 197 ); 198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 201 0x14: subcc({{ 202 int64_t val2 = Rs2_or_imm13; 203 Rd = Rs1 - val2;}}, 204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 206 {{(~(Rs1<63:1> + (~val2)<63:1> + 207 (Rs1 | ~val2)<0:>))<63:>}}, 208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 209 ); 210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 213 0x18: addccc({{ 214 int64_t resTemp, val2 = Rs2_or_imm13; 215 int64_t carryin = Ccr<0:0>; 216 Rd = resTemp = Rs1 + val2 + carryin;}}, 217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 219 {{(Rs1<63:1> + val2<63:1> + 220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 222 ); 223 0x1A: umulcc({{ 224 uint64_t resTemp; 225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 226 Y = resTemp<63:32>;}}, 227 {{0}},{{0}},{{0}},{{0}}); 228 0x1B: smulcc({{ 229 int64_t resTemp; 230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 231 Y = resTemp<63:32>;}}, 232 {{0}},{{0}},{{0}},{{0}}); 233 0x1C: subccc({{ 234 int64_t resTemp, val2 = Rs2_or_imm13; 235 int64_t carryin = Ccr<0:0>; 236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 241 ); 242 0x1D: udivxcc({{ 243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 245 ,{{0}},{{0}},{{0}},{{0}}); 246 0x1E: udivcc({{ 247 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 248 int32_t overflow = 0; 249 if(val2 == 0) fault = new DivisionByZero; 250 else 251 { 252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 253 overflow = (resTemp<63:32> != 0); 254 if(overflow) Rd = resTemp = 0xFFFFFFFF; 255 else Rd = resTemp; 256 } }}, 257 {{0}}, 258 {{overflow}}, 259 {{0}}, 260 {{0}} 261 ); 262 0x1F: sdivcc({{ 263 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 264 bool overflow = false, underflow = false; 265 if(val2 == 0) fault = new DivisionByZero; 266 else 267 { 268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 269 overflow = (Rd<63:31> != 0); 270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 271 if(overflow) Rd = 0x7FFFFFFF; 272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 273 } }}, 274 {{0}}, 275 {{overflow || underflow}}, 276 {{0}}, 277 {{0}} 278 ); 279 0x20: taddcc({{ 280 int64_t resTemp, val2 = Rs2_or_imm13; 281 Rd = resTemp = Rs1 + val2; 282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 284 {{overflow}}, 285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 287 ); 288 0x21: tsubcc({{ 289 int64_t resTemp, val2 = Rs2_or_imm13; 290 Rd = resTemp = Rs1 + val2; 291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 293 {{overflow}}, 294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 296 ); 297 0x22: taddcctv({{ 298 int64_t val2 = Rs2_or_imm13; 299 Rd = Rs1 + val2; 300 int32_t overflow = Rs1<1:0> || val2<1:0> || 301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 302 if(overflow) fault = new TagOverflow;}}, 303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 304 {{overflow}}, 305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 307 ); 308 0x23: tsubcctv({{ 309 int64_t resTemp, val2 = Rs2_or_imm13; 310 Rd = resTemp = Rs1 + val2; 311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 312 if(overflow) fault = new TagOverflow;}}, 313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 314 {{overflow}}, 315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 317 ); 318 0x24: mulscc({{ 319 int64_t resTemp, multiplicand = Rs2_or_imm13; 320 int32_t multiplier = Rs1<31:0>; 321 int32_t savedLSB = Rs1<0:>; 322 multiplier = multiplier<31:1> | 323 ((Ccr<3:3> 324 ^ Ccr<1:1>) << 32); 325 if(!Y<0:>) 326 multiplicand = 0; 327 Rd = resTemp = multiplicand + multiplier; 328 Y = Y<31:1> | (savedLSB << 31);}}, 329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 333 ); 334 } 335 format IntOp 336 { 337 0x25: decode X { 338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 340 } 341 0x26: decode X { 342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 344 } 345 0x27: decode X { 346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 348 } 349 // XXX might want a format rdipr thing here 350 0x28: decode RS1 { 351 0xF: decode I { 352 0x0: Nop::stbar({{/*stuff*/}}); 353 0x1: Nop::membar({{/*stuff*/}}); 354 } 355 default: rdasr({{ 356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 357 }}); 358 } 359 0x29: HPriv::rdhpr({{ 360 // XXX Need to protect with format that traps non-priv/priv 361 // access 362 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 363 }}); 364 0x2A: Priv::rdpr({{ 365 // XXX Need to protect with format that traps non-priv 366 // access 367 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 368 }}); 369 0x2B: BasicOperate::flushw({{ 370 if(NWindows - 2 - Cansave == 0) 371 { 372 if(Otherwin) 373 fault = new SpillNOther(Wstate<5:3>); 374 else 375 fault = new SpillNNormal(Wstate<2:0>); 376 } 377 }}); 378 0x2C: decode MOVCC3 379 { 380 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 381 0x1: decode CC 382 { 383 0x0: movcci({{ 384 if(passesCondition(Ccr<3:0>, COND4)) 385 Rd = Rs2_or_imm11; 386 else 387 Rd = Rd; 388 }}); 389 0x2: movccx({{ 390 if(passesCondition(Ccr<7:4>, COND4)) 391 Rd = Rs2_or_imm11; 392 else 393 Rd = Rd; 394 }}); 395 } 396 } 397 0x2D: sdivx({{ 398 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 399 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 400 }}); 401 0x2E: decode RS1 { 402 0x0: IntOp::popc({{ 403 int64_t count = 0; 404 uint64_t temp = Rs2_or_imm13; 405 //Count the 1s in the front 4bits until none are left 406 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 407 while(temp) 408 { 409 count += oneBits[temp & 0xF]; 410 temp = temp >> 4; 411 } 412 Rd = count; 413 }}); 414 } 415 0x2F: decode RCOND3 416 { 417 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 418 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 419 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 420 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 421 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 422 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 423 } 424 0x30: wrasr({{ 425 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 426 }}); 427 0x31: decode FCN { 428 0x0: Priv::saved({{ 429 assert(Cansave < NWindows - 2); 430 assert(Otherwin || Canrestore); 431 Cansave = Cansave + 1; 432 if(Otherwin == 0) 433 Canrestore = Canrestore - 1; 434 else 435 Otherwin = Otherwin - 1; 436 }}); 437 0x1: BasicOperate::restored({{ 438 assert(Cansave || Otherwin); 439 assert(Canrestore < NWindows - 2); 440 Canrestore = Canrestore + 1; 441 if(Otherwin == 0) 442 Cansave = Cansave - 1; 443 else 444 Otherwin = Otherwin - 1; 445 }}); 446 } 447 0x32: Priv::wrpr({{ 448 // XXX Need to protect with format that traps non-priv 449 // access 450 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 451 }}); 452 0x33: HPriv::wrhpr({{ 453 // XXX Need to protect with format that traps non-priv/priv 454 // access 455 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 456 }}); 457 0x34: decode OPF{ 458 format BasicOperate{ 459 0x01: fmovs({{ 460 Frds.uw = Frs2s.uw; 461 //fsr.ftt = fsr.cexc = 0 462 Fsr &= ~(7 << 14); 463 Fsr &= ~(0x1F); 464 }}); 465 0x02: fmovd({{ 466 Frd.udw = Frs2.udw; 467 //fsr.ftt = fsr.cexc = 0 468 Fsr &= ~(7 << 14); 469 Fsr &= ~(0x1F); 470 }}); 471 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 472 0x05: fnegs({{ 473 Frds.uw = Frs2s.uw ^ (1UL << 31); 474 //fsr.ftt = fsr.cexc = 0 475 Fsr &= ~(7 << 14); 476 Fsr &= ~(0x1F); 477 }}); 478 0x06: fnegd({{ 479 Frd.udw = Frs2.udw ^ (1ULL << 63); 480 //fsr.ftt = fsr.cexc = 0 481 Fsr &= ~(7 << 14); 482 Fsr &= ~(0x1F); 483 }}); 484 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 485 0x09: fabss({{ 486 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 487 //fsr.ftt = fsr.cexc = 0 488 Fsr &= ~(7 << 14); 489 Fsr &= ~(0x1F); 490 }}); 491 0x0A: fabsd({{ 492 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 493 //fsr.ftt = fsr.cexc = 0 494 Fsr &= ~(7 << 14); 495 Fsr &= ~(0x1F); 496 }}); 497 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 498 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); 499 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 500 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 501 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 502 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 503 0x43: Trap::faddq({{fault = new FpDisabled;}}); 504 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 505 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 506 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 507 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 508 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 509 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 510 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 511 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 512 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 513 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 514 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 515 0x81: fstox({{ 516 Frd.df = (double)static_cast<int64_t>(Frs2s.sf); 517 }}); 518 0x82: fdtox({{ 519 Frd.df = (double)static_cast<int64_t>(Frs2.df); 520 }}); 521 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 522 0x84: fxtos({{ 523 Frds.sf = static_cast<float>((int64_t)Frs2.df); 524 }}); 525 0x88: fxtod({{ 526 Frd.df = static_cast<double>((int64_t)Frs2.df); 527 }}); 528 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 529 0xC4: fitos({{ 530 Frds.sf = static_cast<float>((int32_t)Frs2s.sf); 531 }}); 532 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 533 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 534 0xC8: fitod({{ 535 Frd.df = static_cast<double>((int32_t)Frs2s.sf); 536 }}); 537 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 538 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 539 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 540 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 541 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 542 0xD1: fstoi({{ 543 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf); 544 }}); 545 0xD2: fdtoi({{ 546 Frds.sf = (float)static_cast<int32_t>(Frs2.df); 547 }}); 548 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 549 default: Trap::fpop1({{fault = new FpDisabled;}}); 550 } 551 } 552 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 553 //This used to be just impdep1, but now it's a whole bunch 554 //of instructions 555 0x36: decode OPF{ 556 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 557 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 558 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 559 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 560 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 561 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 562 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 563 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 564 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 565 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 566 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 567 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 568 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 569 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 570 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 571 0x18: BasicOperate::alignaddr({{ 572 uint64_t sum = Rs1 + Rs2; 573 Rd = sum & ~7; 574 Gsr = (Gsr & ~7) | (sum & 7); 575 }}); 576 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 577 0x1A: BasicOperate::alignaddresslittle({{ 578 uint64_t sum = Rs1 + Rs2; 579 Rd = sum & ~7; 580 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 581 }}); 582 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 583 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 584 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 585 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 586 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 587 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 588 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 589 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 590 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 591 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 592 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 593 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 594 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 595 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 596 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 597 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 598 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 599 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 600 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 601 0x48: BasicOperate::faligndata({{ 602 uint64_t msbX = Frs1.udw; 603 uint64_t lsbX = Frs2.udw; 604 //Some special cases need to be split out, first 605 //because they're the most likely to be used, and 606 //second because otherwise, we end up shifting by 607 //greater than the width of the type being shifted, 608 //namely 64, which produces undefined results according 609 //to the C standard. 610 switch(Gsr<2:0>) 611 { 612 case 0: 613 Frd.udw = msbX; 614 break; 615 case 8: 616 Frd.udw = lsbX; 617 break; 618 default: 619 uint64_t msbShift = Gsr<2:0> * 8; 620 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 621 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 622 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 623 Frd.udw = ((msbX & msbMask) << msbShift) | 624 ((lsbX & lsbMask) >> lsbShift); 625 } 626 }}); 627 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 628 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 629 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 630 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 631 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 632 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 633 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 634 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 635 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 636 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 637 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 638 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 639 0x61: BasicOperate::fzeros({{Frds.sf = 0;}}); 640 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 641 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 642 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 643 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 644 0x66: BasicOperate::fnot2({{ 645 Frd.df = (double)(~((uint64_t)Frs2.df)); 646 }}); 647 0x67: BasicOperate::fnot2s({{ 648 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 649 }}); 650 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 651 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 652 0x6A: BasicOperate::fnot1({{ 653 Frd.df = (double)(~((uint64_t)Frs1.df)); 654 }}); 655 0x6B: BasicOperate::fnot1s({{ 656 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 657 }}); 658 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 659 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 660 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 661 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 662 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 663 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 664 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 665 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 666 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); 667 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); 668 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 669 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 670 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); 671 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); 672 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 673 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 674 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 675 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 676 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 677 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 678 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 679 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 680 } 681 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 682 0x38: Branch::jmpl({{ 683 Addr target = Rs1 + Rs2_or_imm13; 684 if(target & 0x3) 685 fault = new MemAddressNotAligned; 686 else 687 { 688 Rd = xc->readPC(); 689 NNPC = target; 690 } 691 }}); 692 0x39: Branch::return({{ 693 //If both MemAddressNotAligned and 694 //a fill trap happen, it's not clear 695 //which one should be returned. 696 Addr target = Rs1 + Rs2_or_imm13; 697 if(target & 0x3) 698 fault = new MemAddressNotAligned; 699 else 700 NNPC = target; 701 if(fault == NoFault) 702 { 703 if(Canrestore == 0) 704 { 705 if(Otherwin) 706 fault = new FillNOther(Wstate<5:3>); 707 else 708 fault = new FillNNormal(Wstate<2:0>); 709 } 710 else 711 { 712 //CWP should be set directly so that it always happens 713 //Also, this will allow writing to the new window and 714 //reading from the old one 715 Cwp = (Cwp - 1 + NWindows) % NWindows; 716 Cansave = Cansave + 1; 717 Canrestore = Canrestore - 1; 718 //This is here to make sure the CWP is written 719 //no matter what. This ensures that the results 720 //are written in the new window as well. 721 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 722 warn("About to set the CWP to %d\n", Cwp); 723 } 724 } 725 }}); 726 0x3A: decode CC 727 { 728 0x0: Trap::tcci({{ 729 if(passesCondition(Ccr<3:0>, COND2)) 730 { 731#if FULL_SYSTEM 732 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 733 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 734 fault = new TrapInstruction(lTrapNum); 735#else 736 DPRINTF(Sparc, "The syscall number is %d\n", R1); 737 xc->syscall(R1); 738#endif 739 } 740 }}); 741 0x2: Trap::tccx({{ 742 if(passesCondition(Ccr<7:4>, COND2)) 743 { 744#if FULL_SYSTEM 745 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 746 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 747 fault = new TrapInstruction(lTrapNum); 748#else 749 DPRINTF(Sparc, "The syscall number is %d\n", R1); 750 xc->syscall(R1); 751#endif 752 } 753 }}); 754 } 755 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 756 0x3C: save({{ 757 //CWP should be set directly so that it always happens 758 //Also, this will allow writing to the new window and 759 //reading from the old one 760 if(Cansave == 0) 761 { 762 if(Otherwin) 763 fault = new SpillNOther(Wstate<5:3>); 764 else 765 fault = new SpillNNormal(Wstate<2:0>); 766 //Cwp = (Cwp + 2) % NWindows; 767 } 768 else if(Cleanwin - Canrestore == 0) 769 { 770 //Cwp = (Cwp + 1) % NWindows; 771 fault = new CleanWindow; 772 } 773 else 774 { 775 Cwp = (Cwp + 1) % NWindows; 776 Rd = Rs1 + Rs2_or_imm13; 777 Cansave = Cansave - 1; 778 Canrestore = Canrestore + 1; 779 //This is here to make sure the CWP is written 780 //no matter what. This ensures that the results 781 //are written in the new window as well. 782 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 783 } 784 }}); 785 0x3D: restore({{ 786 if(Canrestore == 0) 787 { 788 if(Otherwin) 789 fault = new FillNOther(Wstate<5:3>); 790 else 791 fault = new FillNNormal(Wstate<2:0>); 792 } 793 else 794 { 795 //CWP should be set directly so that it always happens 796 //Also, this will allow writing to the new window and 797 //reading from the old one 798 Cwp = (Cwp - 1 + NWindows) % NWindows; 799 Rd = Rs1 + Rs2_or_imm13; 800 Cansave = Cansave + 1; 801 Canrestore = Canrestore - 1; 802 //This is here to make sure the CWP is written 803 //no matter what. This ensures that the results 804 //are written in the new window as well. 805 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 806 } 807 }}); 808 0x3E: decode FCN { 809 0x0: Priv::done({{ 810 if(Tl == 0) 811 return new IllegalInstruction; 812 813 Cwp = Tstate<4:0>; 814 Pstate = Tstate<20:8>; 815 Asi = Tstate<31:24>; 816 Ccr = Tstate<39:32>; 817 Gl = Tstate<42:40>; 818 NPC = Tnpc; 819 NNPC = Tnpc + 4; 820 Tl = Tl - 1; 821 }}); 822 0x1: Priv::retry({{ 823 if(Tl == 0) 824 return new IllegalInstruction; 825 Cwp = Tstate<4:0>; 826 Pstate = Tstate<20:8>; 827 Asi = Tstate<31:24>; 828 Ccr = Tstate<39:32>; 829 Gl = Tstate<42:40>; 830 NPC = Tpc; 831 NNPC = Tnpc; 832 Tl = Tl - 1; 833 }}); 834 } 835 } 836 } 837 0x3: decode OP3 { 838 format Load { 839 0x00: lduw({{Rd = Mem.uw;}}); 840 0x01: ldub({{Rd = Mem.ub;}}); 841 0x02: lduh({{Rd = Mem.uhw;}}); 842 0x03: ldd({{ 843 uint64_t val = Mem.udw; 844 RdLow = val<31:0>; 845 RdHigh = val<63:32>; 846 }}); 847 } 848 format Store { 849 0x04: stw({{Mem.uw = Rd.sw;}}); 850 0x05: stb({{Mem.ub = Rd.sb;}}); 851 0x06: sth({{Mem.uhw = Rd.shw;}}); 852 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 853 } 854 format Load { 855 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 856 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 857 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 858 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 859 0x0D: ldstub({{ 860 Rd = Mem.ub; 861 Mem.ub = 0xFF; 862 }}); 863 } 864 0x0E: Store::stx({{Mem.udw = Rd}}); 865 0x0F: LoadStore::swap( 866 {{*temp = Rd.uw; 867 Rd.uw = Mem.uw;}}, 868 {{Mem.uw = *temp;}}); 869 format Load { 870 0x10: lduwa({{Rd = Mem.uw;}}); 871 0x11: lduba({{Rd = Mem.ub;}}); 872 0x12: lduha({{Rd = Mem.uhw;}}); 873 0x13: ldda({{ 874 uint64_t val = Mem.udw; 875 RdLow = val<31:0>; 876 RdHigh = val<63:32>; 877 }}); 878 } 879 format Store { 880 0x14: stwa({{Mem.uw = Rd;}}); 881 0x15: stba({{Mem.ub = Rd;}}); 882 0x16: stha({{Mem.uhw = Rd;}}); 883 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); 884 } 885 format Load { 886 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 887 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 888 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 889 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 890 } 891 0x1D: LoadStore::ldstuba( 892 {{Rd = Mem.ub;}}, 893 {{Mem.ub = 0xFF}}); 894 0x1E: Store::stxa({{Mem.udw = Rd}}); 895 0x1F: LoadStore::swapa( 896 {{*temp = Rd.uw; 897 Rd.uw = Mem.uw;}}, 898 {{Mem.uw = *temp;}}); 899 format Trap { 900 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 901 0x21: decode X { 902 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 903 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 904 } 905 0x22: ldqf({{fault = new FpDisabled;}}); 906 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 907 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 908 0x25: decode X { 909 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 910 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 911 } 912 0x26: stqf({{fault = new FpDisabled;}}); 913 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 914 0x2D: Nop::prefetch({{ }}); 915 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); 916 0x32: ldqfa({{fault = new FpDisabled;}}); 917 format LoadAlt { 918 0x33: decode EXT_ASI { 919 //ASI_NUCLEUS 920 0x04: FailUnimpl::lddfa_n(); 921 //ASI_NUCLEUS_LITTLE 922 0x0C: FailUnimpl::lddfa_nl(); 923 //ASI_AS_IF_USER_PRIMARY 924 0x10: FailUnimpl::lddfa_aiup(); 925 //ASI_AS_IF_USER_PRIMARY_LITTLE 926 0x18: FailUnimpl::lddfa_aiupl(); 927 //ASI_AS_IF_USER_SECONDARY 928 0x11: FailUnimpl::lddfa_aius(); 929 //ASI_AS_IF_USER_SECONDARY_LITTLE 930 0x19: FailUnimpl::lddfa_aiusl(); 931 //ASI_REAL 932 0x14: FailUnimpl::lddfa_real(); 933 //ASI_REAL_LITTLE 934 0x1C: FailUnimpl::lddfa_real_l(); 935 //ASI_REAL_IO 936 0x15: FailUnimpl::lddfa_real_io(); 937 //ASI_REAL_IO_LITTLE 938 0x1D: FailUnimpl::lddfa_real_io_l(); 939 //ASI_PRIMARY 940 0x80: FailUnimpl::lddfa_p(); 941 //ASI_PRIMARY_LITTLE 942 0x88: FailUnimpl::lddfa_pl(); 943 //ASI_SECONDARY 944 0x81: FailUnimpl::lddfa_s(); 945 //ASI_SECONDARY_LITTLE 946 0x89: FailUnimpl::lddfa_sl(); 947 //ASI_PRIMARY_NO_FAULT 948 0x82: FailUnimpl::lddfa_pnf(); 949 //ASI_PRIMARY_NO_FAULT_LITTLE 950 0x8A: FailUnimpl::lddfa_pnfl(); 951 //ASI_SECONDARY_NO_FAULT 952 0x83: FailUnimpl::lddfa_snf(); 953 //ASI_SECONDARY_NO_FAULT_LITTLE 954 0x8B: FailUnimpl::lddfa_snfl(); 955 956 format BlockLoad { 957 // LDBLOCKF 958 //ASI_BLOCK_AS_IF_USER_PRIMARY 959 0x16: FailUnimpl::ldblockf_aiup(); 960 //ASI_BLOCK_AS_IF_USER_SECONDARY 961 0x17: FailUnimpl::ldblockf_aius(); 962 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 963 0x1E: FailUnimpl::ldblockf_aiupl(); 964 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 965 0x1F: FailUnimpl::ldblockf_aiusl(); 966 //ASI_BLOCK_PRIMARY 967 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 968 //ASI_BLOCK_SECONDARY 969 0xF1: FailUnimpl::ldblockf_s(); 970 //ASI_BLOCK_PRIMARY_LITTLE 971 0xF8: FailUnimpl::ldblockf_pl(); 972 //ASI_BLOCK_SECONDARY_LITTLE 973 0xF9: FailUnimpl::ldblockf_sl(); 974 } 975 976 //LDSHORTF 977 //ASI_FL8_PRIMARY 978 0xD0: FailUnimpl::ldshortf_8p(); 979 //ASI_FL8_SECONDARY 980 0xD1: FailUnimpl::ldshortf_8s(); 981 //ASI_FL8_PRIMARY_LITTLE 982 0xD8: FailUnimpl::ldshortf_8pl(); 983 //ASI_FL8_SECONDARY_LITTLE 984 0xD9: FailUnimpl::ldshortf_8sl(); 985 //ASI_FL16_PRIMARY 986 0xD2: FailUnimpl::ldshortf_16p(); 987 //ASI_FL16_SECONDARY 988 0xD3: FailUnimpl::ldshortf_16s(); 989 //ASI_FL16_PRIMARY_LITTLE 990 0xDA: FailUnimpl::ldshortf_16pl(); 991 //ASI_FL16_SECONDARY_LITTLE 992 0xDB: FailUnimpl::ldshortf_16sl(); 993 //Not an ASI which is legal with lddfa 994 default: Trap::lddfa_bad_asi( 995 {{fault = new DataAccessException;}}); 996 } 997 } 998 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); 999 0x36: stqfa({{fault = new FpDisabled;}}); 1000 format StoreAlt { 1001 0x37: decode EXT_ASI { 1002 //ASI_NUCLEUS 1003 0x04: FailUnimpl::stdfa_n(); 1004 //ASI_NUCLEUS_LITTLE 1005 0x0C: FailUnimpl::stdfa_nl(); 1006 //ASI_AS_IF_USER_PRIMARY 1007 0x10: FailUnimpl::stdfa_aiup(); 1008 //ASI_AS_IF_USER_PRIMARY_LITTLE 1009 0x18: FailUnimpl::stdfa_aiupl(); 1010 //ASI_AS_IF_USER_SECONDARY 1011 0x11: FailUnimpl::stdfa_aius(); 1012 //ASI_AS_IF_USER_SECONDARY_LITTLE 1013 0x19: FailUnimpl::stdfa_aiusl(); 1014 //ASI_REAL 1015 0x14: FailUnimpl::stdfa_real(); 1016 //ASI_REAL_LITTLE 1017 0x1C: FailUnimpl::stdfa_real_l(); 1018 //ASI_REAL_IO 1019 0x15: FailUnimpl::stdfa_real_io(); 1020 //ASI_REAL_IO_LITTLE 1021 0x1D: FailUnimpl::stdfa_real_io_l(); 1022 //ASI_PRIMARY 1023 0x80: FailUnimpl::stdfa_p(); 1024 //ASI_PRIMARY_LITTLE 1025 0x88: FailUnimpl::stdfa_pl(); 1026 //ASI_SECONDARY 1027 0x81: FailUnimpl::stdfa_s(); 1028 //ASI_SECONDARY_LITTLE 1029 0x89: FailUnimpl::stdfa_sl(); 1030 //ASI_PRIMARY_NO_FAULT 1031 0x82: FailUnimpl::stdfa_pnf(); 1032 //ASI_PRIMARY_NO_FAULT_LITTLE 1033 0x8A: FailUnimpl::stdfa_pnfl(); 1034 //ASI_SECONDARY_NO_FAULT 1035 0x83: FailUnimpl::stdfa_snf(); 1036 //ASI_SECONDARY_NO_FAULT_LITTLE 1037 0x8B: FailUnimpl::stdfa_snfl(); 1038 1039 format BlockStore { 1040 // STBLOCKF 1041 //ASI_BLOCK_AS_IF_USER_PRIMARY 1042 0x16: FailUnimpl::stblockf_aiup(); 1043 //ASI_BLOCK_AS_IF_USER_SECONDARY 1044 0x17: FailUnimpl::stblockf_aius(); 1045 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1046 0x1E: FailUnimpl::stblockf_aiupl(); 1047 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1048 0x1F: FailUnimpl::stblockf_aiusl(); 1049 //ASI_BLOCK_PRIMARY 1050 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1051 //ASI_BLOCK_SECONDARY 1052 0xF1: FailUnimpl::stblockf_s(); 1053 //ASI_BLOCK_PRIMARY_LITTLE 1054 0xF8: FailUnimpl::stblockf_pl(); 1055 //ASI_BLOCK_SECONDARY_LITTLE 1056 0xF9: FailUnimpl::stblockf_sl(); 1057 } 1058 1059 //STSHORTF 1060 //ASI_FL8_PRIMARY 1061 0xD0: FailUnimpl::stshortf_8p(); 1062 //ASI_FL8_SECONDARY 1063 0xD1: FailUnimpl::stshortf_8s(); 1064 //ASI_FL8_PRIMARY_LITTLE 1065 0xD8: FailUnimpl::stshortf_8pl(); 1066 //ASI_FL8_SECONDARY_LITTLE 1067 0xD9: FailUnimpl::stshortf_8sl(); 1068 //ASI_FL16_PRIMARY 1069 0xD2: FailUnimpl::stshortf_16p(); 1070 //ASI_FL16_SECONDARY 1071 0xD3: FailUnimpl::stshortf_16s(); 1072 //ASI_FL16_PRIMARY_LITTLE 1073 0xDA: FailUnimpl::stshortf_16pl(); 1074 //ASI_FL16_SECONDARY_LITTLE 1075 0xDB: FailUnimpl::stshortf_16sl(); 1076 //Not an ASI which is legal with lddfa 1077 default: Trap::stdfa_bad_asi( 1078 {{fault = new DataAccessException;}}); 1079 } 1080 } 1081 0x3C: Cas::casa({{ 1082 uint64_t val = Mem.uw; 1083 if(Rs2.uw == val) 1084 Mem.uw = Rd.uw; 1085 Rd.uw = val; 1086 }}); 1087 0x3D: Nop::prefetcha({{ }}); 1088 0x3E: Cas::casxa({{ 1089 uint64_t val = Mem.udw; 1090 if(Rs2 == val) 1091 Mem.udw = Rd; 1092 Rd = val; 1093 }}); 1094 } 1095 } 1096} 1097