decoder.isa revision 3056:f613791cfec0
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 0x1: decode COND2 45 { 46 //Branch Always 47 0x8: decode A 48 { 49 0x0: b(19, {{ 50 NNPC = xc->readPC() + disp; 51 }}); 52 0x1: b(19, {{ 53 NPC = xc->readPC() + disp; 54 NNPC = NPC + 4; 55 }}, ',a'); 56 } 57 //Branch Never 58 0x0: decode A 59 { 60 0x0: bn(19, {{ 61 NNPC = NNPC;//Don't do anything 62 }}); 63 0x1: bn(19, {{ 64 NPC = xc->readNextPC() + 4; 65 NNPC = NPC + 4; 66 }}, ',a'); 67 } 68 default: decode BPCC 69 { 70 0x0: bpcci(19, {{ 71 if(passesCondition(Ccr<3:0>, COND2)) 72 NNPC = xc->readPC() + disp; 73 else 74 handle_annul 75 }}); 76 0x2: bpccx(19, {{ 77 if(passesCondition(Ccr<7:4>, COND2)) 78 NNPC = xc->readPC() + disp; 79 else 80 handle_annul 81 }}); 82 } 83 } 84 0x2: bicc(22, {{ 85 if(passesCondition(Ccr<3:0>, COND2)) 86 NNPC = xc->readPC() + disp; 87 else 88 handle_annul 89 }}); 90 } 91 0x3: decode RCOND2 92 { 93 format BranchSplit 94 { 95 0x1: bpreq({{ 96 if(Rs1.sdw == 0) 97 NNPC = xc->readPC() + disp; 98 else 99 handle_annul 100 }}); 101 0x2: bprle({{ 102 if(Rs1.sdw <= 0) 103 NNPC = xc->readPC() + disp; 104 else 105 handle_annul 106 }}); 107 0x3: bprl({{ 108 if(Rs1.sdw < 0) 109 NNPC = xc->readPC() + disp; 110 else 111 handle_annul 112 }}); 113 0x5: bprne({{ 114 if(Rs1.sdw != 0) 115 NNPC = xc->readPC() + disp; 116 else 117 handle_annul 118 }}); 119 0x6: bprg({{ 120 if(Rs1.sdw > 0) 121 NNPC = xc->readPC() + disp; 122 else 123 handle_annul 124 }}); 125 0x7: bprge({{ 126 if(Rs1.sdw >= 0) 127 NNPC = xc->readPC() + disp; 128 else 129 handle_annul 130 }}); 131 } 132 } 133 //SETHI (or NOP if rd == 0 and imm == 0) 134 0x4: SetHi::sethi({{Rd.udw = imm;}}); 135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 136 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 137 } 138 0x1: BranchN::call(30, {{ 139 R15 = xc->readPC(); 140 NNPC = R15 + disp; 141 }}); 142 0x2: decode OP3 { 143 format IntOp { 144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 154 0x0A: umul({{ 155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 156 Y = Rd<63:32>; 157 }}); 158 0x0B: smul({{ 159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 160 Y = Rd.sdw; 161 }}); 162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 163 0x0D: udivx({{ 164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 165 else Rd.udw = Rs1.udw / Rs2_or_imm13; 166 }}); 167 0x0E: udiv({{ 168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 169 else 170 { 171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 172 if(Rd.udw >> 32 != 0) 173 Rd.udw = 0xFFFFFFFF; 174 } 175 }}); 176 0x0F: sdiv({{ 177 if(Rs2_or_imm13.sdw == 0) 178 fault = new DivisionByZero; 179 else 180 { 181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 182 if(Rd.udw<63:31> != 0) 183 Rd.udw = 0x7FFFFFFF; 184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 185 Rd.udw = 0xFFFFFFFF80000000ULL; 186 } 187 }}); 188 } 189 format IntOpCc { 190 0x10: addcc({{ 191 int64_t resTemp, val2 = Rs2_or_imm13; 192 Rd = resTemp = Rs1 + val2;}}, 193 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 197 ); 198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 201 0x14: subcc({{ 202 int64_t val2 = Rs2_or_imm13; 203 Rd = Rs1 - val2;}}, 204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 206 {{(~(Rs1<63:1> + (~val2)<63:1> + 207 (Rs1 | ~val2)<0:>))<63:>}}, 208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 209 ); 210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 213 0x18: addccc({{ 214 int64_t resTemp, val2 = Rs2_or_imm13; 215 int64_t carryin = Ccr<0:0>; 216 Rd = resTemp = Rs1 + val2 + carryin;}}, 217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 219 {{(Rs1<63:1> + val2<63:1> + 220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 222 ); 223 0x1A: umulcc({{ 224 uint64_t resTemp; 225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 226 Y = resTemp<63:32>;}}, 227 {{0}},{{0}},{{0}},{{0}}); 228 0x1B: smulcc({{ 229 int64_t resTemp; 230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 231 Y = resTemp<63:32>;}}, 232 {{0}},{{0}},{{0}},{{0}}); 233 0x1C: subccc({{ 234 int64_t resTemp, val2 = Rs2_or_imm13; 235 int64_t carryin = Ccr<0:0>; 236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 241 ); 242 0x1D: udivxcc({{ 243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 245 ,{{0}},{{0}},{{0}},{{0}}); 246 0x1E: udivcc({{ 247 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 248 int32_t overflow = 0; 249 if(val2 == 0) fault = new DivisionByZero; 250 else 251 { 252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 253 overflow = (resTemp<63:32> != 0); 254 if(overflow) Rd = resTemp = 0xFFFFFFFF; 255 else Rd = resTemp; 256 } }}, 257 {{0}}, 258 {{overflow}}, 259 {{0}}, 260 {{0}} 261 ); 262 0x1F: sdivcc({{ 263 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 264 bool overflow = false, underflow = false; 265 if(val2 == 0) fault = new DivisionByZero; 266 else 267 { 268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 269 overflow = (Rd<63:31> != 0); 270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 271 if(overflow) Rd = 0x7FFFFFFF; 272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 273 } }}, 274 {{0}}, 275 {{overflow || underflow}}, 276 {{0}}, 277 {{0}} 278 ); 279 0x20: taddcc({{ 280 int64_t resTemp, val2 = Rs2_or_imm13; 281 Rd = resTemp = Rs1 + val2; 282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 284 {{overflow}}, 285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 287 ); 288 0x21: tsubcc({{ 289 int64_t resTemp, val2 = Rs2_or_imm13; 290 Rd = resTemp = Rs1 + val2; 291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 293 {{overflow}}, 294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 296 ); 297 0x22: taddcctv({{ 298 int64_t val2 = Rs2_or_imm13; 299 Rd = Rs1 + val2; 300 int32_t overflow = Rs1<1:0> || val2<1:0> || 301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 302 if(overflow) fault = new TagOverflow;}}, 303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 304 {{overflow}}, 305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 307 ); 308 0x23: tsubcctv({{ 309 int64_t resTemp, val2 = Rs2_or_imm13; 310 Rd = resTemp = Rs1 + val2; 311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 312 if(overflow) fault = new TagOverflow;}}, 313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 314 {{overflow}}, 315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 317 ); 318 0x24: mulscc({{ 319 int64_t resTemp, multiplicand = Rs2_or_imm13; 320 int32_t multiplier = Rs1<31:0>; 321 int32_t savedLSB = Rs1<0:>; 322 multiplier = multiplier<31:1> | 323 ((Ccr<3:3> 324 ^ Ccr<1:1>) << 32); 325 if(!Y<0:>) 326 multiplicand = 0; 327 Rd = resTemp = multiplicand + multiplier; 328 Y = Y<31:1> | (savedLSB << 31);}}, 329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 333 ); 334 } 335 format IntOp 336 { 337 0x25: decode X { 338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 340 } 341 0x26: decode X { 342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 344 } 345 0x27: decode X { 346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 348 } 349 // XXX might want a format rdipr thing here 350 0x28: decode RS1 { 351 0xF: decode I { 352 0x0: Nop::stbar({{/*stuff*/}}); 353 0x1: Nop::membar({{/*stuff*/}}); 354 } 355 default: rdasr({{ 356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 357 }}); 358 } 359 0x29: HPriv::rdhpr({{ 360 // XXX Need to protect with format that traps non-priv/priv 361 // access 362 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 363 }}); 364 0x2A: Priv::rdpr({{ 365 // XXX Need to protect with format that traps non-priv 366 // access 367 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 368 }}); 369 0x2B: BasicOperate::flushw({{ 370 if(NWindows - 2 - Cansave == 0) 371 { 372 if(Otherwin) 373 fault = new SpillNOther(Wstate<5:3>); 374 else 375 fault = new SpillNNormal(Wstate<2:0>); 376 } 377 }}); 378 0x2C: decode MOVCC3 379 { 380 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 381 0x1: decode CC 382 { 383 0x0: movcci({{ 384 if(passesCondition(Ccr<3:0>, COND4)) 385 Rd = Rs2_or_imm11; 386 else 387 Rd = Rd; 388 }}); 389 0x2: movccx({{ 390 if(passesCondition(Ccr<7:4>, COND4)) 391 Rd = Rs2_or_imm11; 392 else 393 Rd = Rd; 394 }}); 395 } 396 } 397 0x2D: sdivx({{ 398 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 399 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 400 }}); 401 0x2E: decode RS1 { 402 0x0: IntOp::popc({{ 403 int64_t count = 0; 404 uint64_t temp = Rs2_or_imm13; 405 //Count the 1s in the front 4bits until none are left 406 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 407 while(temp) 408 { 409 count += oneBits[temp & 0xF]; 410 temp = temp >> 4; 411 } 412 Rd = count; 413 }}); 414 } 415 0x2F: decode RCOND3 416 { 417 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 418 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 419 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 420 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 421 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 422 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 423 } 424 0x30: wrasr({{ 425 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 426 }}); 427 0x31: decode FCN { 428 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 429 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 430 } 431 0x32: Priv::wrpr({{ 432 // XXX Need to protect with format that traps non-priv 433 // access 434 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 435 }}); 436 0x33: HPriv::wrhpr({{ 437 // XXX Need to protect with format that traps non-priv/priv 438 // access 439 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 440 }}); 441 0x34: decode OPF{ 442 format BasicOperate{ 443 0x01: fmovs({{ 444 Frd.sf = Frs2.sf; 445 //fsr.ftt = fsr.cexc = 0 446 Fsr &= ~(7 << 14); 447 Fsr &= ~(0x1F); 448 }}); 449 0x02: fmovd({{ 450 Frd.df = Frs2.df; 451 //fsr.ftt = fsr.cexc = 0 452 Fsr &= ~(7 << 14); 453 Fsr &= ~(0x1F); 454 }}); 455 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 456 0x05: fnegs({{ 457 //XXX might want to explicitly flip the sign bit 458 //So cases with Nan and +/-0 don't do weird things 459 Frd.sf = -Frs2.sf; 460 //fsr.ftt = fsr.cexc = 0 461 Fsr &= ~(7 << 14); 462 Fsr &= ~(0x1F); 463 }}); 464 0x06: fnegd({{ 465 //XXX might want to explicitly flip the sign bit 466 //So cases with Nan and +/-0 don't do weird things 467 Frd.df = -Frs2.df; 468 //fsr.ftt = fsr.cexc = 0 469 Fsr &= ~(7 << 14); 470 Fsr &= ~(0x1F); 471 }}); 472 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 473 0x09: fabss({{ 474 //XXX this instruction should be tested individually 475 //Clear the sign bit 476 Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf)); 477 //fsr.ftt = fsr.cexc = 0 478 Fsr &= ~(7 << 14); 479 Fsr &= ~(0x1F); 480 }}); 481 0x0A: fabsd({{ 482 //XXX this instruction should be tested individually 483 //Clear the sign bit 484 Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df)); 485 //fsr.ftt = fsr.cexc = 0 486 Fsr &= ~(7 << 14); 487 Fsr &= ~(0x1F); 488 }}); 489 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 490 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}}); 491 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 492 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 493 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}}); 494 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 495 0x43: Trap::faddq({{fault = new FpDisabled;}}); 496 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}}); 497 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 498 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 499 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}}); 500 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 501 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 502 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}}); 503 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 504 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 505 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}}); 506 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 507 0x81: fstox({{ 508 Frd.df = (double)static_cast<int64_t>(Frs2.sf); 509 }}); 510 0x82: fdtox({{ 511 Frd.df = (double)static_cast<int64_t>(Frs2.df); 512 }}); 513 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 514 0x84: fxtos({{ 515 Frd.sf = static_cast<float>((int64_t)Frs2.df); 516 }}); 517 0x88: fxtod({{ 518 Frd.df = static_cast<double>((int64_t)Frs2.df); 519 }}); 520 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 521 0xC4: fitos({{ 522 Frd.sf = static_cast<float>((int32_t)Frs2.sf); 523 }}); 524 0xC6: fdtos({{Frd.sf = Frs2.df;}}); 525 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 526 0xC8: fitod({{ 527 Frd.df = static_cast<double>((int32_t)Frs2.sf); 528 }}); 529 0xC9: fstod({{Frd.df = Frs2.sf;}}); 530 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 531 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 532 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 533 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 534 0xD1: fstoi({{ 535 Frd.sf = (float)static_cast<int32_t>(Frs2.sf); 536 }}); 537 0xD2: fdtoi({{ 538 Frd.sf = (float)static_cast<int32_t>(Frs2.df); 539 }}); 540 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 541 default: Trap::fpop1({{fault = new FpDisabled;}}); 542 } 543 } 544 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 545 //This used to be just impdep1, but now it's a whole bunch 546 //of instructions 547 0x36: decode OPF{ 548 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 549 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 550 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 551 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 552 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 553 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 554 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 555 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 556 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 557 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 558 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 559 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 560 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 561 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 562 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 563 0x18: BasicOperate::alignaddr({{ 564 uint64_t sum = Rs1 + Rs2; 565 Rd = sum & ~7; 566 Gsr = (Gsr & ~7) | (sum & 7); 567 }}); 568 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 569 0x1A: BasicOperate::alignaddresslittle({{ 570 uint64_t sum = Rs1 + Rs2; 571 Rd = sum & ~7; 572 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 573 }}); 574 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 575 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 576 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 577 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 578 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 579 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 580 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 581 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 582 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 583 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 584 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 585 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 586 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 587 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 588 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 589 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 590 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 591 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 592 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 593 0x48: BasicOperate::faligndata({{ 594 uint64_t msbX = (uint64_t)Frs1; 595 uint64_t lsbX = (uint64_t)Frs2; 596 uint64_t msbShift = Gsr<2:0> * 8; 597 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 598 uint64_t msbMask = ((uint64_t)(-1)) << msbShift; 599 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 600 Frd = ((msbX << msbShift) & msbMask) | 601 ((lsbX << lsbShift) & lsbMask); 602 }}); 603 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 604 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 605 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 606 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 607 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 608 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 609 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 610 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 611 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 612 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 613 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 614 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 615 0x61: BasicOperate::fzeros({{Frd.sf = 0;}}); 616 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 617 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 618 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 619 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 620 0x66: BasicOperate::fnot2({{ 621 Frd.df = (double)(~((uint64_t)Frs2.df)); 622 }}); 623 0x67: BasicOperate::fnot2s({{ 624 Frd.sf = (float)(~((uint32_t)Frs2.sf)); 625 }}); 626 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 627 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 628 0x6A: BasicOperate::fnot1({{ 629 Frd.df = (double)(~((uint64_t)Frs1.df)); 630 }}); 631 0x6B: BasicOperate::fnot1s({{ 632 Frd.sf = (float)(~((uint32_t)Frs1.sf)); 633 }}); 634 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 635 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 636 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 637 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 638 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 639 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 640 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 641 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 642 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}}); 643 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}}); 644 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 645 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 646 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}}); 647 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}}); 648 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 649 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 650 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 651 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 652 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 653 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 654 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 655 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 656 } 657 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 658 0x38: Branch::jmpl({{ 659 Addr target = Rs1 + Rs2_or_imm13; 660 if(target & 0x3) 661 fault = new MemAddressNotAligned; 662 else 663 { 664 Rd = xc->readPC(); 665 NNPC = target; 666 } 667 }}); 668 0x39: Branch::return({{ 669 //If both MemAddressNotAligned and 670 //a fill trap happen, it's not clear 671 //which one should be returned. 672 Addr target = Rs1 + Rs2_or_imm13; 673 if(target & 0x3) 674 fault = new MemAddressNotAligned; 675 else 676 NNPC = target; 677 if(fault == NoFault) 678 { 679 //CWP should be set directly so that it always happens 680 //Also, this will allow writing to the new window and 681 //reading from the old one 682 Cwp = (Cwp - 1 + NWindows) % NWindows; 683 if(Canrestore == 0) 684 { 685 if(Otherwin) 686 fault = new FillNOther(Wstate<5:3>); 687 else 688 fault = new FillNNormal(Wstate<2:0>); 689 } 690 else 691 { 692 Rd = Rs1 + Rs2_or_imm13; 693 Cansave = Cansave + 1; 694 Canrestore = Canrestore - 1; 695 } 696 //This is here to make sure the CWP is written 697 //no matter what. This ensures that the results 698 //are written in the new window as well. 699 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 700 } 701 }}); 702 0x3A: decode CC 703 { 704 0x0: Trap::tcci({{ 705 if(passesCondition(Ccr<3:0>, COND2)) 706 { 707#if FULL_SYSTEM 708 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 709 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 710 fault = new TrapInstruction(lTrapNum); 711#else 712 DPRINTF(Sparc, "The syscall number is %d\n", R1); 713 xc->syscall(R1); 714#endif 715 } 716 }}); 717 0x2: Trap::tccx({{ 718 if(passesCondition(Ccr<7:4>, COND2)) 719 { 720#if FULL_SYSTEM 721 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 722 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 723 fault = new TrapInstruction(lTrapNum); 724#else 725 DPRINTF(Sparc, "The syscall number is %d\n", R1); 726 xc->syscall(R1); 727#endif 728 } 729 }}); 730 } 731 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 732 0x3C: save({{ 733 //CWP should be set directly so that it always happens 734 //Also, this will allow writing to the new window and 735 //reading from the old one 736 if(Cansave == 0) 737 { 738 if(Otherwin) 739 fault = new SpillNOther(Wstate<5:3>); 740 else 741 fault = new SpillNNormal(Wstate<2:0>); 742 Cwp = (Cwp + 2) % NWindows; 743 } 744 else if(Cleanwin - Canrestore == 0) 745 { 746 Cwp = (Cwp + 1) % NWindows; 747 fault = new CleanWindow; 748 } 749 else 750 { 751 Cwp = (Cwp + 1) % NWindows; 752 Rd = Rs1 + Rs2_or_imm13; 753 Cansave = Cansave - 1; 754 Canrestore = Canrestore + 1; 755 } 756 //This is here to make sure the CWP is written 757 //no matter what. This ensures that the results 758 //are written in the new window as well. 759 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 760 }}); 761 0x3D: restore({{ 762 //CWP should be set directly so that it always happens 763 //Also, this will allow writing to the new window and 764 //reading from the old one 765 Cwp = (Cwp - 1 + NWindows) % NWindows; 766 if(Canrestore == 0) 767 { 768 if(Otherwin) 769 fault = new FillNOther(Wstate<5:3>); 770 else 771 fault = new FillNNormal(Wstate<2:0>); 772 } 773 else 774 { 775 Rd = Rs1 + Rs2_or_imm13; 776 Cansave = Cansave + 1; 777 Canrestore = Canrestore - 1; 778 } 779 //This is here to make sure the CWP is written 780 //no matter what. This ensures that the results 781 //are written in the new window as well. 782 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 783 }}); 784 0x3E: decode FCN { 785 0x0: Priv::done({{ 786 if(Tl == 0) 787 return new IllegalInstruction; 788 789 Cwp = Tstate<4:0>; 790 Pstate = Tstate<20:8>; 791 Asi = Tstate<31:24>; 792 Ccr = Tstate<39:32>; 793 Gl = Tstate<42:40>; 794 NPC = Tnpc; 795 NNPC = Tnpc + 4; 796 Tl = Tl - 1; 797 }}); 798 0x1: Priv::retry({{ 799 if(Tl == 0) 800 return new IllegalInstruction; 801 Cwp = Tstate<4:0>; 802 Pstate = Tstate<20:8>; 803 Asi = Tstate<31:24>; 804 Ccr = Tstate<39:32>; 805 Gl = Tstate<42:40>; 806 NPC = Tpc; 807 NNPC = Tnpc + 4; 808 Tl = Tl - 1; 809 }}); 810 } 811 } 812 } 813 0x3: decode OP3 { 814 format Load { 815 0x00: lduw({{Rd = Mem;}}, {{32}}); 816 0x01: ldub({{Rd = Mem;}}, {{8}}); 817 0x02: lduh({{Rd = Mem;}}, {{16}}); 818 0x03: ldd({{ 819 uint64_t val = Mem; 820 RdLow = val<31:0>; 821 RdHigh = val<63:32>; 822 }}, {{64}}); 823 } 824 format Store { 825 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 826 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 827 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 828 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 829 } 830 format Load { 831 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 832 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 833 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 834 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 835 0x0D: ldstub({{ 836 Rd = Mem; 837 Mem = 0xFF; 838 }}, {{8}}); 839 } 840 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 841 0x0F: LoadStore::swap({{ 842 uint32_t temp = Rd; 843 Rd = Mem; 844 Mem = temp; 845 }}, {{32}}); 846 format Load { 847 0x10: lduwa({{Rd = Mem;}}, {{32}}); 848 0x11: lduba({{Rd = Mem;}}, {{8}}); 849 0x12: lduha({{Rd = Mem;}}, {{16}}); 850 0x13: ldda({{ 851 uint64_t val = Mem; 852 RdLow = val<31:0>; 853 RdHigh = val<63:32>; 854 }}, {{64}}); 855 } 856 format Store { 857 0x14: stwa({{Mem = Rd;}}, {{32}}); 858 0x15: stba({{Mem = Rd;}}, {{8}}); 859 0x16: stha({{Mem = Rd;}}, {{16}}); 860 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 861 } 862 format Load { 863 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 864 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 865 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 866 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 867 } 868 0x1D: LoadStore::ldstuba({{ 869 Rd = Mem; 870 Mem = 0xFF; 871 }}, {{8}}); 872 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 873 0x1F: LoadStore::swapa({{ 874 uint32_t temp = Rd; 875 Rd = Mem; 876 Mem = temp; 877 }}, {{32}}); 878 format Trap { 879 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}}); 880 0x21: decode X { 881 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 882 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 883 } 884 0x22: ldqf({{fault = new FpDisabled;}}); 885 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}}); 886 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 887 0x25: decode X { 888 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 889 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 890 } 891 0x26: stqf({{fault = new FpDisabled;}}); 892 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}}); 893 0x2D: Nop::prefetch({{ }}); 894 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}}); 895 0x32: ldqfa({{fault = new FpDisabled;}}); 896 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}}); 897 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 898 0x36: stqfa({{fault = new FpDisabled;}}); 899 //XXX need to work in the ASI thing 900 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}}); 901 0x3C: Cas::casa({{ 902 uint64_t val = Mem.uw; 903 if(Rs2.uw == val) 904 Mem.uw = Rd.uw; 905 Rd.uw = val; 906 }}); 907 0x3D: Nop::prefetcha({{ }}); 908 0x3E: Cas::casxa({{ 909 uint64_t val = Mem.udw; 910 if(Rs2 == val) 911 Mem.udw = Rd; 912 Rd = val; 913 }}); 914 } 915 } 916} 917