decoder.isa revision 7741
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 407741Sgblack@eecs.umich.edu // Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 447741Sgblack@eecs.umich.edu // bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 477741Sgblack@eecs.umich.edu // Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 497720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 507720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 517720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 527720Sgblack@eecs.umich.edu PCS = pc; 535091Sgblack@eecs.umich.edu }}); 547741Sgblack@eecs.umich.edu // Branch Never 555091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 565091Sgblack@eecs.umich.edu annul_code={{ 577720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 587720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 597720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 607720Sgblack@eecs.umich.edu PCS = pc; 615091Sgblack@eecs.umich.edu }}); 623056Sgblack@eecs.umich.edu default: decode BPCC 633056Sgblack@eecs.umich.edu { 645091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 655091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 663056Sgblack@eecs.umich.edu } 672482SN/A } 687741Sgblack@eecs.umich.edu // bicc 693598Sgblack@eecs.umich.edu 0x2: decode COND2 703598Sgblack@eecs.umich.edu { 717741Sgblack@eecs.umich.edu // Branch Always 725091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 737720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 747720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 757720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 767720Sgblack@eecs.umich.edu PCS = pc; 775091Sgblack@eecs.umich.edu }}); 787741Sgblack@eecs.umich.edu // Branch Never 795091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 805091Sgblack@eecs.umich.edu annul_code={{ 817720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 827720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 837720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 847720Sgblack@eecs.umich.edu PCS = pc; 855091Sgblack@eecs.umich.edu }}); 865091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 873598Sgblack@eecs.umich.edu } 882516SN/A } 892516SN/A 0x3: decode RCOND2 902516SN/A { 912516SN/A format BranchSplit 922482SN/A { 935091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 945091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 955091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 965091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 975091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 985091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 992469SN/A } 1002482SN/A } 1017741Sgblack@eecs.umich.edu // SETHI (or NOP if rd == 0 and imm == 0) 1023042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1037741Sgblack@eecs.umich.edu // fbpfcc 1044004Sgblack@eecs.umich.edu 0x5: decode COND2 { 1054004Sgblack@eecs.umich.edu format BranchN { 1067741Sgblack@eecs.umich.edu // Branch Always 1075091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1087720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1097720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 1107720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 1117720Sgblack@eecs.umich.edu PCS = pc; 1125091Sgblack@eecs.umich.edu }}); 1137741Sgblack@eecs.umich.edu // Branch Never 1145091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1155091Sgblack@eecs.umich.edu annul_code={{ 1167720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1177720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 1187720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 1197720Sgblack@eecs.umich.edu PCS = pc; 1205091Sgblack@eecs.umich.edu }}); 1214004Sgblack@eecs.umich.edu default: decode BPCC { 1225091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1235091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1245091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1255091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1265091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1275091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1285091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1295091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1304004Sgblack@eecs.umich.edu } 1314004Sgblack@eecs.umich.edu } 1324004Sgblack@eecs.umich.edu } 1337741Sgblack@eecs.umich.edu // fbfcc 1344004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1354004Sgblack@eecs.umich.edu format BranchN { 1367741Sgblack@eecs.umich.edu // Branch Always 1375091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1387720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1397720Sgblack@eecs.umich.edu pc.npc(pc.pc() + disp); 1407720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 4); 1417720Sgblack@eecs.umich.edu PCS = pc; 1425091Sgblack@eecs.umich.edu }}); 1437741Sgblack@eecs.umich.edu // Branch Never 1445091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1455091Sgblack@eecs.umich.edu annul_code={{ 1467720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1477720Sgblack@eecs.umich.edu pc.nnpc(pc.npc() + 8); 1487720Sgblack@eecs.umich.edu pc.npc(pc.npc() + 4); 1497720Sgblack@eecs.umich.edu PCS = pc; 1505091Sgblack@eecs.umich.edu }}); 1515091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1525091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1534004Sgblack@eecs.umich.edu } 1544004Sgblack@eecs.umich.edu } 1552469SN/A } 1562944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1577720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 1583928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1597720Sgblack@eecs.umich.edu R15 = (pc.pc())<31:0>; 1603928Ssaidi@eecs.umich.edu else 1617720Sgblack@eecs.umich.edu R15 = pc.pc(); 1627720Sgblack@eecs.umich.edu pc.nnpc(R15 + disp); 1637720Sgblack@eecs.umich.edu PCS = pc; 1642469SN/A }}); 1652469SN/A 0x2: decode OP3 { 1662482SN/A format IntOp { 1672482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1682974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1692974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1702974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1712526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1722974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1732974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1742974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1752646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1762974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1772469SN/A 0x0A: umul({{ 1782516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1792646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1802482SN/A }}); 1812469SN/A 0x0B: smul({{ 1823931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1833900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1842482SN/A }}); 1852954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1862469SN/A 0x0D: udivx({{ 1877741Sgblack@eecs.umich.edu if (Rs2_or_imm13 == 0) 1887741Sgblack@eecs.umich.edu fault = new DivisionByZero; 1897741Sgblack@eecs.umich.edu else 1907741Sgblack@eecs.umich.edu Rd.udw = Rs1.udw / Rs2_or_imm13; 1912482SN/A }}); 1922469SN/A 0x0E: udiv({{ 1937741Sgblack@eecs.umich.edu if (Rs2_or_imm13 == 0) { 1947741Sgblack@eecs.umich.edu fault = new DivisionByZero; 1957741Sgblack@eecs.umich.edu } else { 1962646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1977741Sgblack@eecs.umich.edu if (Rd.udw >> 32 != 0) 1982482SN/A Rd.udw = 0xFFFFFFFF; 1992482SN/A } 2002482SN/A }}); 2012482SN/A 0x0F: sdiv({{ 2027741Sgblack@eecs.umich.edu if (Rs2_or_imm13.sdw == 0) { 2032469SN/A fault = new DivisionByZero; 2047741Sgblack@eecs.umich.edu } else { 2057741Sgblack@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | 2067741Sgblack@eecs.umich.edu Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 2077741Sgblack@eecs.umich.edu if ((int64_t)Rd.udw >= 2087741Sgblack@eecs.umich.edu std::numeric_limits<int32_t>::max()) { 2092482SN/A Rd.udw = 0x7FFFFFFF; 2107741Sgblack@eecs.umich.edu } else if ((int64_t)Rd.udw <= 2117741Sgblack@eecs.umich.edu std::numeric_limits<int32_t>::min()) { 2123929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 2137741Sgblack@eecs.umich.edu } 2142482SN/A } 2152526SN/A }}); 2162469SN/A } 2172482SN/A format IntOpCc { 2182469SN/A 0x10: addcc({{ 2195093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2205093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 2215093Sgblack@eecs.umich.edu }}); 2222482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2232482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2242482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2252469SN/A 0x14: subcc({{ 2265093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2275093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2285093Sgblack@eecs.umich.edu }}, sub=True); 2292482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2302482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2312482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2322469SN/A 0x18: addccc({{ 2335093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2345093Sgblack@eecs.umich.edu Rd = res = op1 + op2 + Ccr<0:>; 2355093Sgblack@eecs.umich.edu }}); 2363765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2372615SN/A uint64_t resTemp; 2382615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2393765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2403765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2412615SN/A int64_t resTemp; 2423931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2433765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2442469SN/A 0x1C: subccc({{ 2455093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2465093Sgblack@eecs.umich.edu Rd = res = op1 - op2 - Ccr<0:>; 2475093Sgblack@eecs.umich.edu }}, sub=True); 2483765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2497741Sgblack@eecs.umich.edu if (Rs2_or_imm13.udw == 0) 2507741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2517741Sgblack@eecs.umich.edu else 2527741Sgblack@eecs.umich.edu Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2535093Sgblack@eecs.umich.edu 0x1E: IntOpCcRes::udivcc({{ 2546639Svince@csl.cornell.edu uint64_t resTemp; 2556639Svince@csl.cornell.edu uint32_t val2 = Rs2_or_imm13.udw; 2565093Sgblack@eecs.umich.edu int32_t overflow = 0; 2577741Sgblack@eecs.umich.edu if (val2 == 0) { 2587741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2597741Sgblack@eecs.umich.edu } else { 2605093Sgblack@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2615093Sgblack@eecs.umich.edu overflow = (resTemp<63:32> != 0); 2627741Sgblack@eecs.umich.edu if (overflow) 2637741Sgblack@eecs.umich.edu Rd = resTemp = 0xFFFFFFFF; 2647741Sgblack@eecs.umich.edu else 2657741Sgblack@eecs.umich.edu Rd = resTemp; 2665093Sgblack@eecs.umich.edu } 2675093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2685093Sgblack@eecs.umich.edu 0x1F: IntOpCcRes::sdivcc({{ 2695093Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2705093Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2717741Sgblack@eecs.umich.edu if (val2 == 0) { 2727741Sgblack@eecs.umich.edu fault = new DivisionByZero; 2737741Sgblack@eecs.umich.edu } else { 2745093Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2755093Sgblack@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2765093Sgblack@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2777741Sgblack@eecs.umich.edu if (overflow) 2787741Sgblack@eecs.umich.edu Rd = 0x7FFFFFFF; 2797741Sgblack@eecs.umich.edu else if (underflow) 2807741Sgblack@eecs.umich.edu Rd = ULL(0xFFFFFFFF80000000); 2815093Sgblack@eecs.umich.edu } 2825093Sgblack@eecs.umich.edu }}, iv={{overflow || underflow}}); 2832469SN/A 0x20: taddcc({{ 2845093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2855093Sgblack@eecs.umich.edu Rd = res = Rs1 + op2; 2865093Sgblack@eecs.umich.edu }}, iv={{ 2875093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2885093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2) 2895093Sgblack@eecs.umich.edu }}); 2902469SN/A 0x21: tsubcc({{ 2915093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2925093Sgblack@eecs.umich.edu Rd = res = Rs1 - op2; 2935093Sgblack@eecs.umich.edu }}, iv={{ 2945093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2955093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2) 2965093Sgblack@eecs.umich.edu }}, sub=True); 2972469SN/A 0x22: taddcctv({{ 2985093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2995093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 3005093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 3015093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2); 3027741Sgblack@eecs.umich.edu if (overflow) 3037741Sgblack@eecs.umich.edu fault = new TagOverflow; 3045093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 3052469SN/A 0x23: tsubcctv({{ 3065093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 3075093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 3085093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 3095093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2); 3107741Sgblack@eecs.umich.edu if (overflow) 3117741Sgblack@eecs.umich.edu fault = new TagOverflow; 3125093Sgblack@eecs.umich.edu }}, iv={{overflow}}, sub=True); 3132469SN/A 0x24: mulscc({{ 3145093Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 3154237Sgblack@eecs.umich.edu 3167741Sgblack@eecs.umich.edu // Step 1 3175093Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 3187741Sgblack@eecs.umich.edu // Step 2 3195093Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 3205093Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 3217741Sgblack@eecs.umich.edu // Step 3 3225093Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 3235093Sgblack@eecs.umich.edu int64_t res, op1 = partialP, op2 = added; 3245093Sgblack@eecs.umich.edu Rd = res = partialP + added; 3257741Sgblack@eecs.umich.edu // Steps 4 & 5 3265093Sgblack@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31); 3275093Sgblack@eecs.umich.edu }}); 3282526SN/A } 3292526SN/A format IntOp 3302526SN/A { 3312526SN/A 0x25: decode X { 3322526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3332526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3342469SN/A } 3352526SN/A 0x26: decode X { 3362526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3372526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3382526SN/A } 3392526SN/A 0x27: decode X { 3402526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3412526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3422526SN/A } 3432954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3443929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3457741Sgblack@eecs.umich.edu // 1 should cause an illegal instruction exception 3463587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3473587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3485094Sgblack@eecs.umich.edu 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3493587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3507720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 3517741Sgblack@eecs.umich.edu if (Pstate<3:>) 3527720Sgblack@eecs.umich.edu Rd = (pc.pc())<31:0>; 3533587Sgblack@eecs.umich.edu else 3547720Sgblack@eecs.umich.edu Rd = pc.pc(); 3557720Sgblack@eecs.umich.edu }}); 3563587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3577741Sgblack@eecs.umich.edu // Wait for all fpops to finish. 3583587Sgblack@eecs.umich.edu Rd = Fprs; 3593587Sgblack@eecs.umich.edu }}); 3607741Sgblack@eecs.umich.edu // 7-14 should cause an illegal instruction exception 3613587Sgblack@eecs.umich.edu 0x0F: decode I { 3624040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3634040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3642954Sgblack@eecs.umich.edu } 3653587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3665094Sgblack@eecs.umich.edu 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3677741Sgblack@eecs.umich.edu // 0x12 should cause an illegal instruction exception 3683587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3694010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3704010Ssaidi@eecs.umich.edu if (fault) 3714010Ssaidi@eecs.umich.edu return fault; 3724010Ssaidi@eecs.umich.edu Rd = Gsr; 3732954Sgblack@eecs.umich.edu }}); 3747741Sgblack@eecs.umich.edu // 0x14-0x15 should cause an illegal instruction exception 3753587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3763823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3775094Sgblack@eecs.umich.edu 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3783823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3793598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3807741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 3813598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3823598Sgblack@eecs.umich.edu else 3833598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3843598Sgblack@eecs.umich.edu }}); 3857741Sgblack@eecs.umich.edu // 0x1A is supposed to be reserved, but it reads the strand 3867741Sgblack@eecs.umich.edu // status register. 3877741Sgblack@eecs.umich.edu // 0x1B-0x1F should cause an illegal instruction exception 3882954Sgblack@eecs.umich.edu } 3893587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3903587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3915094Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 3927741Sgblack@eecs.umich.edu // 0x02 should cause an illegal instruction exception 3933587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 3947741Sgblack@eecs.umich.edu // 0x04 should cause an illegal instruction exception 3953587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 3963587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 3977741Sgblack@eecs.umich.edu // 0x07-0x1E should cause an illegal instruction exception 3983823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 3993587Sgblack@eecs.umich.edu } 4003587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 4015094Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 4025094Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 4035094Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 4045094Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 4053823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 4063587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 4073587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 4083587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 4093587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 4103587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 4113587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 4123587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 4133587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 4143587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 4153587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 4167741Sgblack@eecs.umich.edu // 0x0F should cause an illegal instruction exception 4173587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 4187741Sgblack@eecs.umich.edu // 0x11-0x1F should cause an illegal instruction exception 4193587Sgblack@eecs.umich.edu } 4202526SN/A 0x2B: BasicOperate::flushw({{ 4217741Sgblack@eecs.umich.edu if (NWindows - 2 - Cansave != 0) { 4227741Sgblack@eecs.umich.edu if (Otherwin) 4233909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 4242526SN/A else 4253909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 4262526SN/A } 4272526SN/A }}); 4282526SN/A 0x2C: decode MOVCC3 4292469SN/A { 4307085Sgblack@eecs.umich.edu 0x0: decode CC 4317085Sgblack@eecs.umich.edu { 4327085Sgblack@eecs.umich.edu 0x0: movccfcc0({{ 4337741Sgblack@eecs.umich.edu if (passesCondition(Fsr<11:10>, COND4)) 4347085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4357085Sgblack@eecs.umich.edu else 4367085Sgblack@eecs.umich.edu Rd = Rd; 4377085Sgblack@eecs.umich.edu }}); 4387085Sgblack@eecs.umich.edu 0x1: movccfcc1({{ 4397741Sgblack@eecs.umich.edu if (passesCondition(Fsr<33:32>, COND4)) 4407085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4417085Sgblack@eecs.umich.edu else 4427085Sgblack@eecs.umich.edu Rd = Rd; 4437085Sgblack@eecs.umich.edu }}); 4447085Sgblack@eecs.umich.edu 0x2: movccfcc2({{ 4457741Sgblack@eecs.umich.edu if (passesCondition(Fsr<35:34>, COND4)) 4467085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4477085Sgblack@eecs.umich.edu else 4487085Sgblack@eecs.umich.edu Rd = Rd; 4497085Sgblack@eecs.umich.edu }}); 4507085Sgblack@eecs.umich.edu 0x3: movccfcc3({{ 4517741Sgblack@eecs.umich.edu if (passesCondition(Fsr<37:36>, COND4)) 4527085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4537085Sgblack@eecs.umich.edu else 4547085Sgblack@eecs.umich.edu Rd = Rd; 4557085Sgblack@eecs.umich.edu }}); 4567085Sgblack@eecs.umich.edu } 4572526SN/A 0x1: decode CC 4582526SN/A { 4592526SN/A 0x0: movcci({{ 4607741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 4612591SN/A Rd = Rs2_or_imm11; 4622591SN/A else 4632591SN/A Rd = Rd; 4642526SN/A }}); 4652526SN/A 0x2: movccx({{ 4667741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 4672591SN/A Rd = Rs2_or_imm11; 4682591SN/A else 4692591SN/A Rd = Rd; 4702526SN/A }}); 4712224SN/A } 4722526SN/A } 4732526SN/A 0x2D: sdivx({{ 4747741Sgblack@eecs.umich.edu if (Rs2_or_imm13.sdw == 0) 4757741Sgblack@eecs.umich.edu fault = new DivisionByZero; 4767741Sgblack@eecs.umich.edu else 4777741Sgblack@eecs.umich.edu Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4782526SN/A }}); 4793941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4802526SN/A 0x2F: decode RCOND3 4812526SN/A { 4822615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4832615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4842615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4852615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4862615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4872615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4882526SN/A } 4893587Sgblack@eecs.umich.edu 0x30: decode RD { 4903929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4917741Sgblack@eecs.umich.edu // 0x01 should cause an illegal instruction exception 4923587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4933826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 4947741Sgblack@eecs.umich.edu // 0x04-0x05 should cause an illegal instruction exception 4953587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4967741Sgblack@eecs.umich.edu // 0x07-0x0E should cause an illegal instruction exception 4973587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4983587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 4995094Sgblack@eecs.umich.edu 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 5007741Sgblack@eecs.umich.edu // 0x12 should cause an illegal instruction exception 5013587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 5027741Sgblack@eecs.umich.edu if (Fprs<2:> == 0 || Pstate<4:> == 0) 5033587Sgblack@eecs.umich.edu return new FpDisabled; 5043587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 5053587Sgblack@eecs.umich.edu }}); 5063587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 5073587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 5083587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 5093823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5103587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 5117741Sgblack@eecs.umich.edu if (!Hpstate<2:>) 5123587Sgblack@eecs.umich.edu return new IllegalInstruction; 5133823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 5143587Sgblack@eecs.umich.edu }}); 5153823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5163598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 5173598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 5183598Sgblack@eecs.umich.edu }}); 5197741Sgblack@eecs.umich.edu // 0x1A is supposed to be reserved, but it writes the strand 5207741Sgblack@eecs.umich.edu // status register. 5217741Sgblack@eecs.umich.edu // 0x1B-0x1F should cause an illegal instruction exception 5223587Sgblack@eecs.umich.edu } 5232526SN/A 0x31: decode FCN { 5243417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 5253417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 5263417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 5273417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 5287741Sgblack@eecs.umich.edu if (Otherwin == 0) 5293417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 5303417Sgblack@eecs.umich.edu else 5313417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5323417Sgblack@eecs.umich.edu }}); 5333598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 5343417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 5353417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 5363417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 5377741Sgblack@eecs.umich.edu if (Otherwin == 0) 5383417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 5393417Sgblack@eecs.umich.edu else 5403417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5413928Ssaidi@eecs.umich.edu 5427741Sgblack@eecs.umich.edu if (Cleanwin < NWindows - 1) 5433928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 5443417Sgblack@eecs.umich.edu }}); 5452526SN/A } 5463587Sgblack@eecs.umich.edu 0x32: decode RD { 5475094Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc( 5485094Sgblack@eecs.umich.edu {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5495094Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc( 5505094Sgblack@eecs.umich.edu {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5515094Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate( 5525094Sgblack@eecs.umich.edu {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5535094Sgblack@eecs.umich.edu 0x03: Priv::wrprtt( 5545094Sgblack@eecs.umich.edu {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5553823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 5563587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 5573587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 5583587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 5597741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 5603587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5613587Sgblack@eecs.umich.edu else 5623587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5633587Sgblack@eecs.umich.edu }}); 5643587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5653587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5663587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5673587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5683587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5693587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5703587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5717741Sgblack@eecs.umich.edu // 0x0F should cause an illegal instruction exception 5723587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5737741Sgblack@eecs.umich.edu if (Pstate<2:> && !Hpstate<2:>) 5743587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5753587Sgblack@eecs.umich.edu else 5763587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5773587Sgblack@eecs.umich.edu }}); 5787741Sgblack@eecs.umich.edu // 0x11-0x1F should cause an illegal instruction exception 5793587Sgblack@eecs.umich.edu } 5803587Sgblack@eecs.umich.edu 0x33: decode RD { 5813587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5825094Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate( 5835094Sgblack@eecs.umich.edu {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5847741Sgblack@eecs.umich.edu // 0x02 should cause an illegal instruction exception 5853587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 5867741Sgblack@eecs.umich.edu // 0x04 should cause an illegal instruction exception 5873587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 5887741Sgblack@eecs.umich.edu // 0x06-0x01D should cause an illegal instruction exception 5893823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5903587Sgblack@eecs.umich.edu } 5912954Sgblack@eecs.umich.edu 0x34: decode OPF{ 5924008Ssaidi@eecs.umich.edu format FpBasic{ 5935095Sgblack@eecs.umich.edu 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 5945095Sgblack@eecs.umich.edu 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 5953995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 5965095Sgblack@eecs.umich.edu 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 5975095Sgblack@eecs.umich.edu 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 5983995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 5995095Sgblack@eecs.umich.edu 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 6005095Sgblack@eecs.umich.edu 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 6013995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 6023918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 6033918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 6043995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 6053279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 6062963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 6073995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 6083279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 6094008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 6103995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 6113279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 6122963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 6133995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 6143279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 6152963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 6163995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 6173279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 6183995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 6195095Sgblack@eecs.umich.edu 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 6205095Sgblack@eecs.umich.edu 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 6213995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 6225095Sgblack@eecs.umich.edu 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 6235095Sgblack@eecs.umich.edu 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 6243995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 6255095Sgblack@eecs.umich.edu 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 6263279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 6273995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 6285095Sgblack@eecs.umich.edu 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 6293279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 6303995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 6313995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 6323995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 6333995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6342963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6354008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6364008Ssaidi@eecs.umich.edu float t = Frds.sw; 6374008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6384008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6392963Sgblack@eecs.umich.edu }}); 6402963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 6414008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 6424008Ssaidi@eecs.umich.edu double t = Frds.sw; 6434008Ssaidi@eecs.umich.edu if (t != Frs2.df) 6444008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6452963Sgblack@eecs.umich.edu }}); 6463995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 6473941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 6482963Sgblack@eecs.umich.edu } 6492954Sgblack@eecs.umich.edu } 6503992Sgblack@eecs.umich.edu 0x35: decode OPF{ 6514008Ssaidi@eecs.umich.edu format FpBasic{ 6524204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 6537741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<11:10>, COND4)) 6544204Sgblack@eecs.umich.edu Frds = Frs2s; 6554204Sgblack@eecs.umich.edu else 6564204Sgblack@eecs.umich.edu Frds = Frds; 6574204Sgblack@eecs.umich.edu }}); 6584204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 6597741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<11:10>, COND4)) 6604204Sgblack@eecs.umich.edu Frd = Frs2; 6614204Sgblack@eecs.umich.edu else 6624204Sgblack@eecs.umich.edu Frd = Frd; 6634204Sgblack@eecs.umich.edu }}); 6644204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 6654204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 6667741Sgblack@eecs.umich.edu if (Rs1 == 0) 6674204Sgblack@eecs.umich.edu Frds = Frs2s; 6684204Sgblack@eecs.umich.edu else 6694204Sgblack@eecs.umich.edu Frds = Frds; 6704204Sgblack@eecs.umich.edu }}); 6714204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 6727741Sgblack@eecs.umich.edu if (Rs1 == 0) 6734204Sgblack@eecs.umich.edu Frd = Frs2; 6744204Sgblack@eecs.umich.edu else 6754204Sgblack@eecs.umich.edu Frd = Frd; 6764204Sgblack@eecs.umich.edu }}); 6774204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 6784204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 6797741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<33:32>, COND4)) 6804204Sgblack@eecs.umich.edu Frds = Frs2s; 6814204Sgblack@eecs.umich.edu else 6824204Sgblack@eecs.umich.edu Frds = Frds; 6834204Sgblack@eecs.umich.edu }}); 6844204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 6857741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<33:32>, COND4)) 6864204Sgblack@eecs.umich.edu Frd = Frs2; 6874204Sgblack@eecs.umich.edu else 6884204Sgblack@eecs.umich.edu Frd = Frd; 6894204Sgblack@eecs.umich.edu }}); 6904204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 6914204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 6927741Sgblack@eecs.umich.edu if (Rs1 <= 0) 6934204Sgblack@eecs.umich.edu Frds = Frs2s; 6944204Sgblack@eecs.umich.edu else 6954204Sgblack@eecs.umich.edu Frds = Frds; 6964204Sgblack@eecs.umich.edu }}); 6974204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 6987741Sgblack@eecs.umich.edu if (Rs1 <= 0) 6994204Sgblack@eecs.umich.edu Frd = Frs2; 7004204Sgblack@eecs.umich.edu else 7014204Sgblack@eecs.umich.edu Frd = Frd; 7024204Sgblack@eecs.umich.edu }}); 7034204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 7043992Sgblack@eecs.umich.edu 0x51: fcmps({{ 7053992Sgblack@eecs.umich.edu uint8_t fcc; 7067741Sgblack@eecs.umich.edu if (isnan(Frs1s) || isnan(Frs2s)) 7073992Sgblack@eecs.umich.edu fcc = 3; 7087741Sgblack@eecs.umich.edu else if (Frs1s < Frs2s) 7093992Sgblack@eecs.umich.edu fcc = 1; 7107741Sgblack@eecs.umich.edu else if (Frs1s > Frs2s) 7113992Sgblack@eecs.umich.edu fcc = 2; 7123992Sgblack@eecs.umich.edu else 7133992Sgblack@eecs.umich.edu fcc = 0; 7143992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7157741Sgblack@eecs.umich.edu if (FCMPCC) 7163992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7173992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7183992Sgblack@eecs.umich.edu }}); 7193992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 7203992Sgblack@eecs.umich.edu uint8_t fcc; 7217741Sgblack@eecs.umich.edu if (isnan(Frs1) || isnan(Frs2)) 7223992Sgblack@eecs.umich.edu fcc = 3; 7237741Sgblack@eecs.umich.edu else if (Frs1 < Frs2) 7243992Sgblack@eecs.umich.edu fcc = 1; 7257741Sgblack@eecs.umich.edu else if (Frs1 > Frs2) 7263992Sgblack@eecs.umich.edu fcc = 2; 7273992Sgblack@eecs.umich.edu else 7283992Sgblack@eecs.umich.edu fcc = 0; 7293992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7307741Sgblack@eecs.umich.edu if (FCMPCC) 7313992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7323992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7333992Sgblack@eecs.umich.edu }}); 7343995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7353997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7363992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7377741Sgblack@eecs.umich.edu if (isnan(Frs1s) || isnan(Frs2s)) 7383992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7397741Sgblack@eecs.umich.edu if (Frs1s < Frs2s) 7403992Sgblack@eecs.umich.edu fcc = 1; 7417741Sgblack@eecs.umich.edu else if (Frs1s > Frs2s) 7423992Sgblack@eecs.umich.edu fcc = 2; 7433992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7447741Sgblack@eecs.umich.edu if (FCMPCC) 7453992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7463992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7473992Sgblack@eecs.umich.edu }}); 7483997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 7493992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7507741Sgblack@eecs.umich.edu if (isnan(Frs1) || isnan(Frs2)) 7513992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7527741Sgblack@eecs.umich.edu if (Frs1 < Frs2) 7533992Sgblack@eecs.umich.edu fcc = 1; 7547741Sgblack@eecs.umich.edu else if (Frs1 > Frs2) 7553992Sgblack@eecs.umich.edu fcc = 2; 7563992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7577741Sgblack@eecs.umich.edu if (FCMPCC) 7583992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7593992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7603992Sgblack@eecs.umich.edu }}); 7613997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 7624204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 7637741Sgblack@eecs.umich.edu if (Rs1 < 0) 7644204Sgblack@eecs.umich.edu Frds = Frs2s; 7654204Sgblack@eecs.umich.edu else 7664204Sgblack@eecs.umich.edu Frds = Frds; 7674204Sgblack@eecs.umich.edu }}); 7684204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 7697741Sgblack@eecs.umich.edu if (Rs1 < 0) 7704204Sgblack@eecs.umich.edu Frd = Frs2; 7714204Sgblack@eecs.umich.edu else 7724204Sgblack@eecs.umich.edu Frd = Frd; 7734204Sgblack@eecs.umich.edu }}); 7744204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 7754204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 7767741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<35:34>, COND4)) 7774204Sgblack@eecs.umich.edu Frds = Frs2s; 7784204Sgblack@eecs.umich.edu else 7794204Sgblack@eecs.umich.edu Frds = Frds; 7804204Sgblack@eecs.umich.edu }}); 7814204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 7827741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<35:34>, COND4)) 7834204Sgblack@eecs.umich.edu Frd = Frs2; 7844204Sgblack@eecs.umich.edu else 7854204Sgblack@eecs.umich.edu Frd = Frd; 7864204Sgblack@eecs.umich.edu }}); 7874204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 7884204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 7897741Sgblack@eecs.umich.edu if (Rs1 != 0) 7904204Sgblack@eecs.umich.edu Frds = Frs2s; 7914204Sgblack@eecs.umich.edu else 7924204Sgblack@eecs.umich.edu Frds = Frds; 7934204Sgblack@eecs.umich.edu }}); 7944204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 7957741Sgblack@eecs.umich.edu if (Rs1 != 0) 7964204Sgblack@eecs.umich.edu Frd = Frs2; 7974204Sgblack@eecs.umich.edu else 7984204Sgblack@eecs.umich.edu Frd = Frd; 7994204Sgblack@eecs.umich.edu }}); 8004204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 8014204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 8027741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<37:36>, COND4)) 8034204Sgblack@eecs.umich.edu Frds = Frs2s; 8044204Sgblack@eecs.umich.edu else 8054204Sgblack@eecs.umich.edu Frds = Frds; 8064204Sgblack@eecs.umich.edu }}); 8074204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 8087741Sgblack@eecs.umich.edu if (passesFpCondition(Fsr<37:36>, COND4)) 8094204Sgblack@eecs.umich.edu Frd = Frs2; 8104204Sgblack@eecs.umich.edu else 8114204Sgblack@eecs.umich.edu Frd = Frd; 8124204Sgblack@eecs.umich.edu }}); 8134204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 8144204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 8157741Sgblack@eecs.umich.edu if (Rs1 > 0) 8164204Sgblack@eecs.umich.edu Frds = Frs2s; 8174204Sgblack@eecs.umich.edu else 8184204Sgblack@eecs.umich.edu Frds = Frds; 8194204Sgblack@eecs.umich.edu }}); 8204204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 8217741Sgblack@eecs.umich.edu if (Rs1 > 0) 8224204Sgblack@eecs.umich.edu Frd = Frs2; 8234204Sgblack@eecs.umich.edu else 8244204Sgblack@eecs.umich.edu Frd = Frd; 8254204Sgblack@eecs.umich.edu }}); 8264204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 8274204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 8287741Sgblack@eecs.umich.edu if (Rs1 >= 0) 8294204Sgblack@eecs.umich.edu Frds = Frs2s; 8304204Sgblack@eecs.umich.edu else 8314204Sgblack@eecs.umich.edu Frds = Frds; 8324204Sgblack@eecs.umich.edu }}); 8334204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8347741Sgblack@eecs.umich.edu if (Rs1 >= 0) 8354204Sgblack@eecs.umich.edu Frd = Frs2; 8364204Sgblack@eecs.umich.edu else 8374204Sgblack@eecs.umich.edu Frd = Frd; 8384204Sgblack@eecs.umich.edu }}); 8394204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 8404204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 8417741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 8424204Sgblack@eecs.umich.edu Frds = Frs2s; 8434204Sgblack@eecs.umich.edu else 8444204Sgblack@eecs.umich.edu Frds = Frds; 8454204Sgblack@eecs.umich.edu }}); 8464204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 8477741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND4)) 8484204Sgblack@eecs.umich.edu Frd = Frs2; 8494204Sgblack@eecs.umich.edu else 8504204Sgblack@eecs.umich.edu Frd = Frd; 8514204Sgblack@eecs.umich.edu }}); 8524204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 8534204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 8547741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 8554204Sgblack@eecs.umich.edu Frds = Frs2s; 8564204Sgblack@eecs.umich.edu else 8574204Sgblack@eecs.umich.edu Frds = Frds; 8584204Sgblack@eecs.umich.edu }}); 8594204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 8607741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND4)) 8614204Sgblack@eecs.umich.edu Frd = Frs2; 8624204Sgblack@eecs.umich.edu else 8634204Sgblack@eecs.umich.edu Frd = Frd; 8644204Sgblack@eecs.umich.edu }}); 8654204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 8663992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 8673992Sgblack@eecs.umich.edu } 8683992Sgblack@eecs.umich.edu } 8697741Sgblack@eecs.umich.edu // This used to be just impdep1, but now it's a whole bunch 8707741Sgblack@eecs.umich.edu // of instructions 8712954Sgblack@eecs.umich.edu 0x36: decode OPF{ 8723941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 8733941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 8743941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 8753941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 8763941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 8773941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 8783941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 8793941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 8803941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 8813941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 8823941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 8833941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 8843941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 8853941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 8863941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 8873042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 8882963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8893042Sgblack@eecs.umich.edu Rd = sum & ~7; 8902963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 8912963Sgblack@eecs.umich.edu }}); 8923941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 8932963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 8942963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8953042Sgblack@eecs.umich.edu Rd = sum & ~7; 8962963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 8972963Sgblack@eecs.umich.edu }}); 8983941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 8993941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 9003941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 9013941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 9023941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 9033941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 9043941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 9053941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 9063941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 9073941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 9083941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 9093941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 9103941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 9113941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 9123941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 9132954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 9142954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 9152954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 9162954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 9172963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 9183057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 9193057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 9207741Sgblack@eecs.umich.edu // Some special cases need to be split out, first 9217741Sgblack@eecs.umich.edu // because they're the most likely to be used, and 9227741Sgblack@eecs.umich.edu // second because otherwise, we end up shifting by 9237741Sgblack@eecs.umich.edu // greater than the width of the type being shifted, 9247741Sgblack@eecs.umich.edu // namely 64, which produces undefined results 9257741Sgblack@eecs.umich.edu // according to the C standard. 9267741Sgblack@eecs.umich.edu switch (Gsr<2:0>) { 9277741Sgblack@eecs.umich.edu case 0: 9287741Sgblack@eecs.umich.edu Frd.udw = msbX; 9297741Sgblack@eecs.umich.edu break; 9307741Sgblack@eecs.umich.edu case 8: 9317741Sgblack@eecs.umich.edu Frd.udw = lsbX; 9327741Sgblack@eecs.umich.edu break; 9337741Sgblack@eecs.umich.edu default: 9347741Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9357741Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9367741Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9377741Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 9387741Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 9397741Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 9403057Sgblack@eecs.umich.edu } 9412963Sgblack@eecs.umich.edu }}); 9422954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 9433941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 9443941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 9453941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 9463941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 9473941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 9483941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 9493941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 9503941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 9513941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 9523941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 9534008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 9544008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 9553941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 9563941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 9573941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 9583941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 9594008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 9602963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 9612963Sgblack@eecs.umich.edu }}); 9624008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 9633279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 9642963Sgblack@eecs.umich.edu }}); 9653941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 9663941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 9674008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 9682963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 9692963Sgblack@eecs.umich.edu }}); 9704008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 9713279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 9722963Sgblack@eecs.umich.edu }}); 9733941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 9743941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 9753941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 9763941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 9773941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 9783941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 9793941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 9803941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 9814008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 9824008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 9833941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 9843941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 9854008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 9864008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 9873941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 9883941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 9893941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 9903941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 9914008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 9924008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 9932954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 9943941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 9952954Sgblack@eecs.umich.edu } 9964090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 9974090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 9984096Sgblack@eecs.umich.edu#if FULL_SYSTEM 9994113Sgblack@eecs.umich.edu format BasicOperate { 10004113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 10014113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 10024113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10034113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 10044113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 10054113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10064113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 10074113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10084113Sgblack@eecs.umich.edu 0x54: m5panic({{ 10097720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10107720Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", pc.pc()); 10114113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10124113Sgblack@eecs.umich.edu } 10134096Sgblack@eecs.umich.edu#endif 10144096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 10154090Ssaidi@eecs.umich.edu } 10162526SN/A 0x38: Branch::jmpl({{ 10172526SN/A Addr target = Rs1 + Rs2_or_imm13; 10187741Sgblack@eecs.umich.edu if (target & 0x3) { 10192526SN/A fault = new MemAddressNotAligned; 10207741Sgblack@eecs.umich.edu } else { 10217720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10223928Ssaidi@eecs.umich.edu if (Pstate<3:>) 10237720Sgblack@eecs.umich.edu Rd = (pc.pc())<31:0>; 10243928Ssaidi@eecs.umich.edu else 10257720Sgblack@eecs.umich.edu Rd = pc.pc(); 10267720Sgblack@eecs.umich.edu pc.nnpc(target); 10277720Sgblack@eecs.umich.edu PCS = pc; 10282526SN/A } 10292526SN/A }}); 10302526SN/A 0x39: Branch::return({{ 10312526SN/A Addr target = Rs1 + Rs2_or_imm13; 10327741Sgblack@eecs.umich.edu if (fault == NoFault) { 10337741Sgblack@eecs.umich.edu // Check for fills which are higher priority than alignment 10347741Sgblack@eecs.umich.edu // faults. 10357741Sgblack@eecs.umich.edu if (Canrestore == 0) { 10367741Sgblack@eecs.umich.edu if (Otherwin) 10373909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10382561SN/A else 10393909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10407741Sgblack@eecs.umich.edu } else if (target & 0x3) { // Check for alignment faults 10413765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 10427741Sgblack@eecs.umich.edu } else { 10437720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 10447720Sgblack@eecs.umich.edu pc.nnpc(target); 10457720Sgblack@eecs.umich.edu PCS = pc; 10463417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10472561SN/A Cansave = Cansave + 1; 10482561SN/A Canrestore = Canrestore - 1; 10492561SN/A } 10502561SN/A } 10512526SN/A }}); 10522526SN/A 0x3A: decode CC 10532526SN/A { 10542526SN/A 0x0: Trap::tcci({{ 10557741Sgblack@eecs.umich.edu if (passesCondition(Ccr<3:0>, COND2)) { 10562561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10572561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10583531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10592561SN/A } 10604828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10612526SN/A 0x2: Trap::tccx({{ 10627741Sgblack@eecs.umich.edu if (passesCondition(Ccr<7:4>, COND2)) { 10632561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10642561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10653531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10662526SN/A } 10674828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10682526SN/A } 10694090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 10704090Ssaidi@eecs.umich.edu MemWriteOp); 10712526SN/A 0x3C: save({{ 10727741Sgblack@eecs.umich.edu if (Cansave == 0) { 10737741Sgblack@eecs.umich.edu if (Otherwin) 10743909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 10752526SN/A else 10763909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 10777741Sgblack@eecs.umich.edu } else if (Cleanwin - Canrestore == 0) { 10782526SN/A fault = new CleanWindow; 10797741Sgblack@eecs.umich.edu } else { 10802526SN/A Cwp = (Cwp + 1) % NWindows; 10813765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 10822561SN/A Cansave = Cansave - 1; 10832561SN/A Canrestore = Canrestore + 1; 10842526SN/A } 10852526SN/A }}); 10862526SN/A 0x3D: restore({{ 10877741Sgblack@eecs.umich.edu if (Canrestore == 0) { 10887741Sgblack@eecs.umich.edu if (Otherwin) 10893909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10902526SN/A else 10913909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10927741Sgblack@eecs.umich.edu } else { 10933417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10943765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 10952561SN/A Cansave = Cansave + 1; 10962561SN/A Canrestore = Canrestore - 1; 10972526SN/A } 10982526SN/A }}); 10992526SN/A 0x3E: decode FCN { 11002526SN/A 0x0: Priv::done({{ 11012646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11022646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11032646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11042646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11052646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11063825Ssaidi@eecs.umich.edu Hpstate = Htstate; 11077720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 11087720Sgblack@eecs.umich.edu pc.npc(Tnpc); 11097720Sgblack@eecs.umich.edu pc.nnpc(Tnpc + 4); 11107720Sgblack@eecs.umich.edu PCS = pc; 11112526SN/A Tl = Tl - 1; 11125094Sgblack@eecs.umich.edu }}, checkTl=true); 11132938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 11142646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11152646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11162646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11172646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11182646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11193826Ssaidi@eecs.umich.edu Hpstate = Htstate; 11207720Sgblack@eecs.umich.edu SparcISA::PCState pc = PCS; 11217720Sgblack@eecs.umich.edu pc.npc(Tpc); 11227720Sgblack@eecs.umich.edu pc.nnpc(Tnpc); 11237720Sgblack@eecs.umich.edu PCS = pc; 11242526SN/A Tl = Tl - 1; 11255094Sgblack@eecs.umich.edu }}, checkTl=true); 11262526SN/A } 11272526SN/A } 11282469SN/A } 11292469SN/A 0x3: decode OP3 { 11302526SN/A format Load { 11313272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 11323272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 11333272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 11343835Sgblack@eecs.umich.edu 0x03: ldtw({{ 11354115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 11364115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 11373272Sgblack@eecs.umich.edu }}); 11382526SN/A } 11392526SN/A format Store { 11403272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 11413272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 11423272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 11434224Sgblack@eecs.umich.edu 0x07: sttw({{ 11447741Sgblack@eecs.umich.edu // This temporary needs to be here so that the parser 11457741Sgblack@eecs.umich.edu // will correctly identify this instruction as a store. 11467741Sgblack@eecs.umich.edu // It's probably either the parenthesis or referencing 11477741Sgblack@eecs.umich.edu // the member variable that throws confuses it. 11484256Sgblack@eecs.umich.edu Twin32_t temp; 11494256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 11504256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 11514256Sgblack@eecs.umich.edu Mem.tuw = temp; 11524224Sgblack@eecs.umich.edu }}); 11532526SN/A } 11542526SN/A format Load { 11553272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 11563272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 11573272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 11583272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 11592526SN/A } 11604040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 11614040Ssaidi@eecs.umich.edu {{ 11624040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 11634040Ssaidi@eecs.umich.edu Rd.ub = tmp; 11644040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11653272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 11664040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 11674040Ssaidi@eecs.umich.edu {{ 11684040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 11694040Ssaidi@eecs.umich.edu Rd.uw = tmp; 11704040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11713810Sgblack@eecs.umich.edu format LoadAlt { 11725096Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}); 11735096Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}); 11745096Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}); 11753856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 11767741Sgblack@eecs.umich.edu // ASI_LDTD_AIUP 11773926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 11784040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11795096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11807741Sgblack@eecs.umich.edu // ASI_LDTD_AIUS 11813926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 11824040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11835096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11847741Sgblack@eecs.umich.edu // ASI_QUAD_LDD 11853856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 11864040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11875096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11887741Sgblack@eecs.umich.edu // ASI_LDTX_REAL 11893856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 11904040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11915096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11927741Sgblack@eecs.umich.edu // ASI_LDTX_N 11934040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 11944040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11955096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11967741Sgblack@eecs.umich.edu // ASI_LDTX_AIUP_L 11974040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 11984040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11995096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12007741Sgblack@eecs.umich.edu // ASI_LDTX_AIUS_L 12014040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 12024040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12035096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12047741Sgblack@eecs.umich.edu // ASI_LDTX_L 12054040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 12064040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12075096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12087741Sgblack@eecs.umich.edu // ASI_LDTX_REAL_L 12093856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 12104040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12115096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12127741Sgblack@eecs.umich.edu // ASI_LDTX_N_L 12133856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 12144040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12155096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12167741Sgblack@eecs.umich.edu // ASI_LDTX_P 12173901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 12184040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12195096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12207741Sgblack@eecs.umich.edu // ASI_LDTX_S 12213926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 12224040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12235096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12247741Sgblack@eecs.umich.edu // ASI_LDTX_PL 12254040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 12264040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12275096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12287741Sgblack@eecs.umich.edu // ASI_LDTX_SL 12294040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 12304040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12315096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12323856Ssaidi@eecs.umich.edu default: ldtwa({{ 12334115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12345096Sgblack@eecs.umich.edu RdHigh = (Mem.tuw).b;}}); 12353856Ssaidi@eecs.umich.edu } 12362526SN/A } 12373810Sgblack@eecs.umich.edu format StoreAlt { 12385096Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}); 12395096Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}); 12405096Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}); 12414224Sgblack@eecs.umich.edu 0x17: sttwa({{ 12427741Sgblack@eecs.umich.edu // This temporary needs to be here so that the parser 12437741Sgblack@eecs.umich.edu // will correctly identify this instruction as a store. 12447741Sgblack@eecs.umich.edu // It's probably either the parenthesis or referencing 12457741Sgblack@eecs.umich.edu // the member variable that throws confuses it. 12464256Sgblack@eecs.umich.edu Twin32_t temp; 12474256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12484256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12494256Sgblack@eecs.umich.edu Mem.tuw = temp; 12505096Sgblack@eecs.umich.edu }}); 12512526SN/A } 12523810Sgblack@eecs.umich.edu format LoadAlt { 12535096Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 12545096Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 12555096Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 12565096Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 12572526SN/A } 12584040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 12594040Ssaidi@eecs.umich.edu {{ 12604040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12614040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12625096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12635096Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 12644040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 12654040Ssaidi@eecs.umich.edu {{ 12664040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12674040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12685096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12694040Ssaidi@eecs.umich.edu 12702526SN/A format Trap { 12713931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 12724008Ssaidi@eecs.umich.edu 0x21: decode RD { 12734011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 12744011Ssaidi@eecs.umich.edu if (fault) 12754011Ssaidi@eecs.umich.edu return fault; 12764011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 12774011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 12784011Ssaidi@eecs.umich.edu if (fault) 12794011Ssaidi@eecs.umich.edu return fault; 12804011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 12814008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 12822469SN/A } 12832526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 12843272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 12853931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 12864008Ssaidi@eecs.umich.edu 0x25: decode RD { 12875893Sgblack@eecs.umich.edu 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 12885893Sgblack@eecs.umich.edu if (fault) 12895893Sgblack@eecs.umich.edu return fault; 12905893Sgblack@eecs.umich.edu Mem.uw = Fsr<31:0>;}}); 12915893Sgblack@eecs.umich.edu 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 12925893Sgblack@eecs.umich.edu if (fault) 12935893Sgblack@eecs.umich.edu return fault; 12945893Sgblack@eecs.umich.edu Mem.udw = Fsr;}}); 12954008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 12962526SN/A } 12972526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 12983272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 12992526SN/A 0x2D: Nop::prefetch({{ }}); 13005096Sgblack@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 13012526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 13023272Sgblack@eecs.umich.edu format LoadAlt { 13033272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 13047741Sgblack@eecs.umich.edu // ASI_NUCLEUS 13053272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 13067741Sgblack@eecs.umich.edu // ASI_NUCLEUS_LITTLE 13073272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 13087741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY 13093272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 13107741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY_LITTLE 13113272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 13127741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY 13133272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 13147741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY_LITTLE 13153272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 13167741Sgblack@eecs.umich.edu // ASI_REAL 13173272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 13187741Sgblack@eecs.umich.edu // ASI_REAL_LITTLE 13193272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 13207741Sgblack@eecs.umich.edu // ASI_REAL_IO 13213272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 13227741Sgblack@eecs.umich.edu // ASI_REAL_IO_LITTLE 13233272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 13247741Sgblack@eecs.umich.edu // ASI_PRIMARY 13253272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 13267741Sgblack@eecs.umich.edu // ASI_PRIMARY_LITTLE 13273272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 13287741Sgblack@eecs.umich.edu // ASI_SECONDARY 13293272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 13307741Sgblack@eecs.umich.edu // ASI_SECONDARY_LITTLE 13313272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 13327741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT 13333272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 13347741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT_LITTLE 13353272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 13367741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT 13373272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 13387741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT_LITTLE 13393272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 13403272Sgblack@eecs.umich.edu 13413272Sgblack@eecs.umich.edu format BlockLoad { 13423272Sgblack@eecs.umich.edu // LDBLOCKF 13437741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY 13443272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 13457741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY 13463272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 13477741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 13483272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 13497741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 13503272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 13517741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY 13525096Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 13537741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY 13543272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 13557741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY_LITTLE 13563272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 13577741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY_LITTLE 13583272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 13593272Sgblack@eecs.umich.edu } 13603272Sgblack@eecs.umich.edu 13617741Sgblack@eecs.umich.edu // LDSHORTF 13627741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY 13633272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 13647741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY 13653272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 13667741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY_LITTLE 13673272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 13687741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY_LITTLE 13693272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 13707741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY 13713272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 13727741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY 13733272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 13747741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY_LITTLE 13753272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 13767741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY_LITTLE 13773272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 13787741Sgblack@eecs.umich.edu // Not an ASI which is legal with lddfa 13793378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 13803378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 13813272Sgblack@eecs.umich.edu } 13823272Sgblack@eecs.umich.edu } 13833931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 13842954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 13853378Sgblack@eecs.umich.edu format StoreAlt { 13863378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 13877741Sgblack@eecs.umich.edu // ASI_NUCLEUS 13883378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 13897741Sgblack@eecs.umich.edu // ASI_NUCLEUS_LITTLE 13903378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 13917741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY 13923378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 13937741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_PRIMARY_LITTLE 13943378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 13957741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY 13963378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 13977741Sgblack@eecs.umich.edu // ASI_AS_IF_USER_SECONDARY_LITTLE 13983378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 13997741Sgblack@eecs.umich.edu // ASI_REAL 14003378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 14017741Sgblack@eecs.umich.edu // ASI_REAL_LITTLE 14023378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 14037741Sgblack@eecs.umich.edu // ASI_REAL_IO 14043378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 14057741Sgblack@eecs.umich.edu // ASI_REAL_IO_LITTLE 14063378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 14077741Sgblack@eecs.umich.edu // ASI_PRIMARY 14083378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 14097741Sgblack@eecs.umich.edu // ASI_PRIMARY_LITTLE 14103378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 14117741Sgblack@eecs.umich.edu // ASI_SECONDARY 14123378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 14137741Sgblack@eecs.umich.edu // ASI_SECONDARY_LITTLE 14143378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 14157741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT 14163378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 14177741Sgblack@eecs.umich.edu // ASI_PRIMARY_NO_FAULT_LITTLE 14183378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 14197741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT 14203378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 14217741Sgblack@eecs.umich.edu // ASI_SECONDARY_NO_FAULT_LITTLE 14223378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 14233378Sgblack@eecs.umich.edu 14243378Sgblack@eecs.umich.edu format BlockStore { 14253378Sgblack@eecs.umich.edu // STBLOCKF 14267741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY 14273378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 14287741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY 14293378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 14307741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14313378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 14327741Sgblack@eecs.umich.edu // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14333378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 14347741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY 14355096Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 14367741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY 14373378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 14387741Sgblack@eecs.umich.edu // ASI_BLOCK_PRIMARY_LITTLE 14393378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 14407741Sgblack@eecs.umich.edu // ASI_BLOCK_SECONDARY_LITTLE 14413378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 14423378Sgblack@eecs.umich.edu } 14433378Sgblack@eecs.umich.edu 14447741Sgblack@eecs.umich.edu // STSHORTF 14457741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY 14463378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 14477741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY 14483378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 14497741Sgblack@eecs.umich.edu // ASI_FL8_PRIMARY_LITTLE 14503378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 14517741Sgblack@eecs.umich.edu // ASI_FL8_SECONDARY_LITTLE 14523378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 14537741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY 14543378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 14557741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY 14563378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 14577741Sgblack@eecs.umich.edu // ASI_FL16_PRIMARY_LITTLE 14583378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 14597741Sgblack@eecs.umich.edu // ASI_FL16_SECONDARY_LITTLE 14603378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 14617741Sgblack@eecs.umich.edu // Not an ASI which is legal with lddfa 14623378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 14633378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14643378Sgblack@eecs.umich.edu } 14653378Sgblack@eecs.umich.edu } 14664040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 14674040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 14684040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 14694040Ssaidi@eecs.umich.edu {{ 14704040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 14714040Ssaidi@eecs.umich.edu Rd.uw = tmp; 14725096Sgblack@eecs.umich.edu }}, MEM_SWAP_COND); 14732526SN/A 0x3D: Nop::prefetcha({{ }}); 14744040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 14754040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 14765096Sgblack@eecs.umich.edu {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 14772526SN/A } 14782469SN/A } 14792022SN/A} 1480