decoder.isa revision 7085
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443598Sgblack@eecs.umich.edu //bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 473056Sgblack@eecs.umich.edu //Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 495091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 505091Sgblack@eecs.umich.edu NNPC = NPC + 4; 515091Sgblack@eecs.umich.edu }}); 523056Sgblack@eecs.umich.edu //Branch Never 535091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 545091Sgblack@eecs.umich.edu annul_code={{ 555091Sgblack@eecs.umich.edu NNPC = NPC + 8; 565091Sgblack@eecs.umich.edu NPC = NPC + 4; 575091Sgblack@eecs.umich.edu }}); 583056Sgblack@eecs.umich.edu default: decode BPCC 593056Sgblack@eecs.umich.edu { 605091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 615091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 623056Sgblack@eecs.umich.edu } 632482SN/A } 643598Sgblack@eecs.umich.edu //bicc 653598Sgblack@eecs.umich.edu 0x2: decode COND2 663598Sgblack@eecs.umich.edu { 673598Sgblack@eecs.umich.edu //Branch Always 685091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 695091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 705091Sgblack@eecs.umich.edu NNPC = NPC + 4; 715091Sgblack@eecs.umich.edu }}); 723598Sgblack@eecs.umich.edu //Branch Never 735091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 745091Sgblack@eecs.umich.edu annul_code={{ 755091Sgblack@eecs.umich.edu NNPC = NPC + 8; 765091Sgblack@eecs.umich.edu NPC = NPC + 4; 775091Sgblack@eecs.umich.edu }}); 785091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 793598Sgblack@eecs.umich.edu } 802516SN/A } 812516SN/A 0x3: decode RCOND2 822516SN/A { 832516SN/A format BranchSplit 842482SN/A { 855091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 865091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 875091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 885091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 895091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 905091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 912469SN/A } 922482SN/A } 932516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 943042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 954004Sgblack@eecs.umich.edu //fbpfcc 964004Sgblack@eecs.umich.edu 0x5: decode COND2 { 974004Sgblack@eecs.umich.edu format BranchN { 984004Sgblack@eecs.umich.edu //Branch Always 995091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1005091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1015091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1025091Sgblack@eecs.umich.edu }}); 1034004Sgblack@eecs.umich.edu //Branch Never 1045091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1055091Sgblack@eecs.umich.edu annul_code={{ 1065091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1075091Sgblack@eecs.umich.edu NPC = NPC + 4; 1085091Sgblack@eecs.umich.edu }}); 1094004Sgblack@eecs.umich.edu default: decode BPCC { 1105091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1115091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1125091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1135091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1145091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1155091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1165091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1175091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1184004Sgblack@eecs.umich.edu } 1194004Sgblack@eecs.umich.edu } 1204004Sgblack@eecs.umich.edu } 1214004Sgblack@eecs.umich.edu //fbfcc 1224004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1234004Sgblack@eecs.umich.edu format BranchN { 1244004Sgblack@eecs.umich.edu //Branch Always 1255091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1265091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1275091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1285091Sgblack@eecs.umich.edu }}); 1294004Sgblack@eecs.umich.edu //Branch Never 1305091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1315091Sgblack@eecs.umich.edu annul_code={{ 1325091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1335091Sgblack@eecs.umich.edu NPC = NPC + 4; 1345091Sgblack@eecs.umich.edu }}); 1355091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1365091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1374004Sgblack@eecs.umich.edu } 1384004Sgblack@eecs.umich.edu } 1392469SN/A } 1402944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1413928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1423928Ssaidi@eecs.umich.edu R15 = (xc->readPC())<31:0>; 1433928Ssaidi@eecs.umich.edu else 1443928Ssaidi@eecs.umich.edu R15 = xc->readPC(); 1452516SN/A NNPC = R15 + disp; 1462469SN/A }}); 1472469SN/A 0x2: decode OP3 { 1482482SN/A format IntOp { 1492482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1502974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1512974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1522974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1532526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1542974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1552974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1562974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1572646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1582974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1592469SN/A 0x0A: umul({{ 1602516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1612646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1622482SN/A }}); 1632469SN/A 0x0B: smul({{ 1643931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1653900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1662482SN/A }}); 1672954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1682469SN/A 0x0D: udivx({{ 1692516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1702516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1712482SN/A }}); 1722469SN/A 0x0E: udiv({{ 1732516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1742482SN/A else 1752482SN/A { 1762646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1772482SN/A if(Rd.udw >> 32 != 0) 1782482SN/A Rd.udw = 0xFFFFFFFF; 1792482SN/A } 1802482SN/A }}); 1812482SN/A 0x0F: sdiv({{ 1822615SN/A if(Rs2_or_imm13.sdw == 0) 1832469SN/A fault = new DivisionByZero; 1842469SN/A else 1852482SN/A { 1862646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1873929Ssaidi@eecs.umich.edu if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 1882482SN/A Rd.udw = 0x7FFFFFFF; 1893929Ssaidi@eecs.umich.edu else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 1903929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 1912482SN/A } 1922526SN/A }}); 1932469SN/A } 1942482SN/A format IntOpCc { 1952469SN/A 0x10: addcc({{ 1965093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 1975093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 1985093Sgblack@eecs.umich.edu }}); 1992482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2002482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2012482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2022469SN/A 0x14: subcc({{ 2035093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2045093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2055093Sgblack@eecs.umich.edu }}, sub=True); 2062482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2072482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2082482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2092469SN/A 0x18: addccc({{ 2105093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2115093Sgblack@eecs.umich.edu Rd = res = op1 + op2 + Ccr<0:>; 2125093Sgblack@eecs.umich.edu }}); 2133765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2142615SN/A uint64_t resTemp; 2152615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2163765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2173765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2182615SN/A int64_t resTemp; 2193931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2203765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2212469SN/A 0x1C: subccc({{ 2225093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2235093Sgblack@eecs.umich.edu Rd = res = op1 - op2 - Ccr<0:>; 2245093Sgblack@eecs.umich.edu }}, sub=True); 2253765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2262615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2273765Sgblack@eecs.umich.edu else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2285093Sgblack@eecs.umich.edu 0x1E: IntOpCcRes::udivcc({{ 2296639Svince@csl.cornell.edu uint64_t resTemp; 2306639Svince@csl.cornell.edu uint32_t val2 = Rs2_or_imm13.udw; 2315093Sgblack@eecs.umich.edu int32_t overflow = 0; 2325093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2335093Sgblack@eecs.umich.edu else 2345093Sgblack@eecs.umich.edu { 2355093Sgblack@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2365093Sgblack@eecs.umich.edu overflow = (resTemp<63:32> != 0); 2375093Sgblack@eecs.umich.edu if(overflow) Rd = resTemp = 0xFFFFFFFF; 2385093Sgblack@eecs.umich.edu else Rd = resTemp; 2395093Sgblack@eecs.umich.edu } 2405093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2415093Sgblack@eecs.umich.edu 0x1F: IntOpCcRes::sdivcc({{ 2425093Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2435093Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2445093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2455093Sgblack@eecs.umich.edu else 2465093Sgblack@eecs.umich.edu { 2475093Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2485093Sgblack@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2495093Sgblack@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2505093Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 2515093Sgblack@eecs.umich.edu else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 2525093Sgblack@eecs.umich.edu } 2535093Sgblack@eecs.umich.edu }}, iv={{overflow || underflow}}); 2542469SN/A 0x20: taddcc({{ 2555093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2565093Sgblack@eecs.umich.edu Rd = res = Rs1 + op2; 2575093Sgblack@eecs.umich.edu }}, iv={{ 2585093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2595093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2) 2605093Sgblack@eecs.umich.edu }}); 2612469SN/A 0x21: tsubcc({{ 2625093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2635093Sgblack@eecs.umich.edu Rd = res = Rs1 - op2; 2645093Sgblack@eecs.umich.edu }}, iv={{ 2655093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2665093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2) 2675093Sgblack@eecs.umich.edu }}, sub=True); 2682469SN/A 0x22: taddcctv({{ 2695093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2705093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 2715093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2725093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2); 2735093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2745093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2752469SN/A 0x23: tsubcctv({{ 2765093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2775093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2785093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2795093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2); 2805093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2815093Sgblack@eecs.umich.edu }}, iv={{overflow}}, sub=True); 2822469SN/A 0x24: mulscc({{ 2835093Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 2844237Sgblack@eecs.umich.edu 2855093Sgblack@eecs.umich.edu //Step 1 2865093Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 2875093Sgblack@eecs.umich.edu //Step 2 2885093Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 2895093Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 2905093Sgblack@eecs.umich.edu //Step 3 2915093Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 2925093Sgblack@eecs.umich.edu int64_t res, op1 = partialP, op2 = added; 2935093Sgblack@eecs.umich.edu Rd = res = partialP + added; 2945093Sgblack@eecs.umich.edu //Steps 4 & 5 2955093Sgblack@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31); 2965093Sgblack@eecs.umich.edu }}); 2972526SN/A } 2982526SN/A format IntOp 2992526SN/A { 3002526SN/A 0x25: decode X { 3012526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3022526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3032469SN/A } 3042526SN/A 0x26: decode X { 3052526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3062526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3072526SN/A } 3082526SN/A 0x27: decode X { 3092526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3102526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3112526SN/A } 3122954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3133929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3143587Sgblack@eecs.umich.edu //1 should cause an illegal instruction exception 3153587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3163587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3175094Sgblack@eecs.umich.edu 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3183587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3193587Sgblack@eecs.umich.edu if(Pstate<3:>) 3203587Sgblack@eecs.umich.edu Rd = (xc->readPC())<31:0>; 3213587Sgblack@eecs.umich.edu else 3223587Sgblack@eecs.umich.edu Rd = xc->readPC();}}); 3233587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3243587Sgblack@eecs.umich.edu //Wait for all fpops to finish. 3253587Sgblack@eecs.umich.edu Rd = Fprs; 3263587Sgblack@eecs.umich.edu }}); 3273587Sgblack@eecs.umich.edu //7-14 should cause an illegal instruction exception 3283587Sgblack@eecs.umich.edu 0x0F: decode I { 3294040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3304040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3312954Sgblack@eecs.umich.edu } 3323587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3335094Sgblack@eecs.umich.edu 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3343587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 3353587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3364010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3374010Ssaidi@eecs.umich.edu if (fault) 3384010Ssaidi@eecs.umich.edu return fault; 3394010Ssaidi@eecs.umich.edu Rd = Gsr; 3402954Sgblack@eecs.umich.edu }}); 3413587Sgblack@eecs.umich.edu //0x14-0x15 should cause an illegal instruction exception 3423587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3433823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3445094Sgblack@eecs.umich.edu 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3453823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3463598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3473598Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 3483598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3493598Sgblack@eecs.umich.edu else 3503598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3513598Sgblack@eecs.umich.edu }}); 3523598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it reads the strand 3533598Sgblack@eecs.umich.edu //status register. 3543598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 3552954Sgblack@eecs.umich.edu } 3563587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3573587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3585094Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 3593587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 3603587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 3613587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 3623587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 3633587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 3643587Sgblack@eecs.umich.edu //0x07-0x1E should cause an illegal instruction exception 3653823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 3663587Sgblack@eecs.umich.edu } 3673587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 3685094Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 3695094Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 3705094Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 3715094Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 3723823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 3733587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 3743587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 3753587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 3763587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 3773587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 3783587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 3793587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 3803587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 3813587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 3823587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 3833587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 3843587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 3853587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 3863587Sgblack@eecs.umich.edu } 3872526SN/A 0x2B: BasicOperate::flushw({{ 3883911Ssaidi@eecs.umich.edu if(NWindows - 2 - Cansave != 0) 3892526SN/A { 3902526SN/A if(Otherwin) 3913909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 3922526SN/A else 3933909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 3942526SN/A } 3952526SN/A }}); 3962526SN/A 0x2C: decode MOVCC3 3972469SN/A { 3987085Sgblack@eecs.umich.edu 0x0: decode CC 3997085Sgblack@eecs.umich.edu { 4007085Sgblack@eecs.umich.edu 0x0: movccfcc0({{ 4017085Sgblack@eecs.umich.edu if(passesCondition(Fsr<11:10>, COND4)) 4027085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4037085Sgblack@eecs.umich.edu else 4047085Sgblack@eecs.umich.edu Rd = Rd; 4057085Sgblack@eecs.umich.edu }}); 4067085Sgblack@eecs.umich.edu 0x1: movccfcc1({{ 4077085Sgblack@eecs.umich.edu if(passesCondition(Fsr<33:32>, COND4)) 4087085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4097085Sgblack@eecs.umich.edu else 4107085Sgblack@eecs.umich.edu Rd = Rd; 4117085Sgblack@eecs.umich.edu }}); 4127085Sgblack@eecs.umich.edu 0x2: movccfcc2({{ 4137085Sgblack@eecs.umich.edu if(passesCondition(Fsr<35:34>, COND4)) 4147085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4157085Sgblack@eecs.umich.edu else 4167085Sgblack@eecs.umich.edu Rd = Rd; 4177085Sgblack@eecs.umich.edu }}); 4187085Sgblack@eecs.umich.edu 0x3: movccfcc3({{ 4197085Sgblack@eecs.umich.edu if(passesCondition(Fsr<37:36>, COND4)) 4207085Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 4217085Sgblack@eecs.umich.edu else 4227085Sgblack@eecs.umich.edu Rd = Rd; 4237085Sgblack@eecs.umich.edu }}); 4247085Sgblack@eecs.umich.edu } 4252526SN/A 0x1: decode CC 4262526SN/A { 4272526SN/A 0x0: movcci({{ 4282646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 4292591SN/A Rd = Rs2_or_imm11; 4302591SN/A else 4312591SN/A Rd = Rd; 4322526SN/A }}); 4332526SN/A 0x2: movccx({{ 4342646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 4352591SN/A Rd = Rs2_or_imm11; 4362591SN/A else 4372591SN/A Rd = Rd; 4382526SN/A }}); 4392224SN/A } 4402526SN/A } 4412526SN/A 0x2D: sdivx({{ 4422615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 4432615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4442526SN/A }}); 4453941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4462526SN/A 0x2F: decode RCOND3 4472526SN/A { 4482615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4492615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4502615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4512615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4522615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4532615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4542526SN/A } 4553587Sgblack@eecs.umich.edu 0x30: decode RD { 4563929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4573587Sgblack@eecs.umich.edu //0x01 should cause an illegal instruction exception 4583587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4593826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 4603587Sgblack@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 4613587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4623587Sgblack@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 4633587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4643587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 4655094Sgblack@eecs.umich.edu 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 4663587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 4673587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 4683587Sgblack@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 4693587Sgblack@eecs.umich.edu return new FpDisabled; 4703587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 4713587Sgblack@eecs.umich.edu }}); 4723587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 4733587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 4743587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 4753823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4763587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 4773587Sgblack@eecs.umich.edu if(!Hpstate<2:>) 4783587Sgblack@eecs.umich.edu return new IllegalInstruction; 4793823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 4803587Sgblack@eecs.umich.edu }}); 4813823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4823598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 4833598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 4843598Sgblack@eecs.umich.edu }}); 4853598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it writes the strand 4863598Sgblack@eecs.umich.edu //status register. 4873598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 4883587Sgblack@eecs.umich.edu } 4892526SN/A 0x31: decode FCN { 4903417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 4913417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 4923417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 4933417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 4943417Sgblack@eecs.umich.edu if(Otherwin == 0) 4953417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 4963417Sgblack@eecs.umich.edu else 4973417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 4983417Sgblack@eecs.umich.edu }}); 4993598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 5003417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 5013417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 5023417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 5033417Sgblack@eecs.umich.edu if(Otherwin == 0) 5043417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 5053417Sgblack@eecs.umich.edu else 5063417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5073928Ssaidi@eecs.umich.edu 5083928Ssaidi@eecs.umich.edu if(Cleanwin < NWindows - 1) 5093928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 5103417Sgblack@eecs.umich.edu }}); 5112526SN/A } 5123587Sgblack@eecs.umich.edu 0x32: decode RD { 5135094Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc( 5145094Sgblack@eecs.umich.edu {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5155094Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc( 5165094Sgblack@eecs.umich.edu {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5175094Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate( 5185094Sgblack@eecs.umich.edu {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5195094Sgblack@eecs.umich.edu 0x03: Priv::wrprtt( 5205094Sgblack@eecs.umich.edu {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5213823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 5223587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 5233587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 5243587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 5253587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5263587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5273587Sgblack@eecs.umich.edu else 5283587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5293587Sgblack@eecs.umich.edu }}); 5303587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5313587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5323587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5333587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5343587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5353587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5363587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5373587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 5383587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5393587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5403587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5413587Sgblack@eecs.umich.edu else 5423587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5433587Sgblack@eecs.umich.edu }}); 5443587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 5453587Sgblack@eecs.umich.edu } 5463587Sgblack@eecs.umich.edu 0x33: decode RD { 5473587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5485094Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate( 5495094Sgblack@eecs.umich.edu {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5503587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 5513587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 5523587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 5533587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 5543587Sgblack@eecs.umich.edu //0x06-0x01D should cause an illegal instruction exception 5553823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5563587Sgblack@eecs.umich.edu } 5572954Sgblack@eecs.umich.edu 0x34: decode OPF{ 5584008Ssaidi@eecs.umich.edu format FpBasic{ 5595095Sgblack@eecs.umich.edu 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 5605095Sgblack@eecs.umich.edu 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 5613995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 5625095Sgblack@eecs.umich.edu 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 5635095Sgblack@eecs.umich.edu 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 5643995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 5655095Sgblack@eecs.umich.edu 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 5665095Sgblack@eecs.umich.edu 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 5673995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 5683918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 5693918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 5703995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 5713279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 5722963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 5733995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 5743279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 5754008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 5763995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 5773279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 5782963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 5793995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 5803279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 5812963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 5823995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 5833279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 5843995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 5855095Sgblack@eecs.umich.edu 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 5865095Sgblack@eecs.umich.edu 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 5873995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 5885095Sgblack@eecs.umich.edu 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 5895095Sgblack@eecs.umich.edu 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 5903995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 5915095Sgblack@eecs.umich.edu 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 5923279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 5933995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 5945095Sgblack@eecs.umich.edu 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 5953279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 5963995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 5973995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 5983995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 5993995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6002963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6014008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6024008Ssaidi@eecs.umich.edu float t = Frds.sw; 6034008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6044008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6052963Sgblack@eecs.umich.edu }}); 6062963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 6074008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 6084008Ssaidi@eecs.umich.edu double t = Frds.sw; 6094008Ssaidi@eecs.umich.edu if (t != Frs2.df) 6104008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6112963Sgblack@eecs.umich.edu }}); 6123995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 6133941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 6142963Sgblack@eecs.umich.edu } 6152954Sgblack@eecs.umich.edu } 6163992Sgblack@eecs.umich.edu 0x35: decode OPF{ 6174008Ssaidi@eecs.umich.edu format FpBasic{ 6184204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 6194204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6204204Sgblack@eecs.umich.edu Frds = Frs2s; 6214204Sgblack@eecs.umich.edu else 6224204Sgblack@eecs.umich.edu Frds = Frds; 6234204Sgblack@eecs.umich.edu }}); 6244204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 6254204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6264204Sgblack@eecs.umich.edu Frd = Frs2; 6274204Sgblack@eecs.umich.edu else 6284204Sgblack@eecs.umich.edu Frd = Frd; 6294204Sgblack@eecs.umich.edu }}); 6304204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 6314204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 6324204Sgblack@eecs.umich.edu if(Rs1 == 0) 6334204Sgblack@eecs.umich.edu Frds = Frs2s; 6344204Sgblack@eecs.umich.edu else 6354204Sgblack@eecs.umich.edu Frds = Frds; 6364204Sgblack@eecs.umich.edu }}); 6374204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 6384204Sgblack@eecs.umich.edu if(Rs1 == 0) 6394204Sgblack@eecs.umich.edu Frd = Frs2; 6404204Sgblack@eecs.umich.edu else 6414204Sgblack@eecs.umich.edu Frd = Frd; 6424204Sgblack@eecs.umich.edu }}); 6434204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 6444204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 6454204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 6464204Sgblack@eecs.umich.edu Frds = Frs2s; 6474204Sgblack@eecs.umich.edu else 6484204Sgblack@eecs.umich.edu Frds = Frds; 6494204Sgblack@eecs.umich.edu }}); 6504204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 6514204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 6524204Sgblack@eecs.umich.edu Frd = Frs2; 6534204Sgblack@eecs.umich.edu else 6544204Sgblack@eecs.umich.edu Frd = Frd; 6554204Sgblack@eecs.umich.edu }}); 6564204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 6574204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 6584204Sgblack@eecs.umich.edu if(Rs1 <= 0) 6594204Sgblack@eecs.umich.edu Frds = Frs2s; 6604204Sgblack@eecs.umich.edu else 6614204Sgblack@eecs.umich.edu Frds = Frds; 6624204Sgblack@eecs.umich.edu }}); 6634204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 6644204Sgblack@eecs.umich.edu if(Rs1 <= 0) 6654204Sgblack@eecs.umich.edu Frd = Frs2; 6664204Sgblack@eecs.umich.edu else 6674204Sgblack@eecs.umich.edu Frd = Frd; 6684204Sgblack@eecs.umich.edu }}); 6694204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 6703992Sgblack@eecs.umich.edu 0x51: fcmps({{ 6713992Sgblack@eecs.umich.edu uint8_t fcc; 6723998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 6733992Sgblack@eecs.umich.edu fcc = 3; 6743992Sgblack@eecs.umich.edu else if(Frs1s < Frs2s) 6753992Sgblack@eecs.umich.edu fcc = 1; 6763992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 6773992Sgblack@eecs.umich.edu fcc = 2; 6783992Sgblack@eecs.umich.edu else 6793992Sgblack@eecs.umich.edu fcc = 0; 6803992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 6813992Sgblack@eecs.umich.edu if(FCMPCC) 6823992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 6833992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 6843992Sgblack@eecs.umich.edu }}); 6853992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 6863992Sgblack@eecs.umich.edu uint8_t fcc; 6874008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 6883992Sgblack@eecs.umich.edu fcc = 3; 6894008Ssaidi@eecs.umich.edu else if(Frs1 < Frs2) 6903992Sgblack@eecs.umich.edu fcc = 1; 6914008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 6923992Sgblack@eecs.umich.edu fcc = 2; 6933992Sgblack@eecs.umich.edu else 6943992Sgblack@eecs.umich.edu fcc = 0; 6953992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 6963992Sgblack@eecs.umich.edu if(FCMPCC) 6973992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 6983992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 6993992Sgblack@eecs.umich.edu }}); 7003995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7013997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7023992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7033998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7043992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7053992Sgblack@eecs.umich.edu if(Frs1s < Frs2s) 7063992Sgblack@eecs.umich.edu fcc = 1; 7073992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 7083992Sgblack@eecs.umich.edu fcc = 2; 7093992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7103992Sgblack@eecs.umich.edu if(FCMPCC) 7113992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7123992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7133992Sgblack@eecs.umich.edu }}); 7143997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 7153992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7164008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7173992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7184008Ssaidi@eecs.umich.edu if(Frs1 < Frs2) 7193992Sgblack@eecs.umich.edu fcc = 1; 7204008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7213992Sgblack@eecs.umich.edu fcc = 2; 7223992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7233992Sgblack@eecs.umich.edu if(FCMPCC) 7243992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7253992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7263992Sgblack@eecs.umich.edu }}); 7273997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 7284204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 7294204Sgblack@eecs.umich.edu if(Rs1 < 0) 7304204Sgblack@eecs.umich.edu Frds = Frs2s; 7314204Sgblack@eecs.umich.edu else 7324204Sgblack@eecs.umich.edu Frds = Frds; 7334204Sgblack@eecs.umich.edu }}); 7344204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 7354204Sgblack@eecs.umich.edu if(Rs1 < 0) 7364204Sgblack@eecs.umich.edu Frd = Frs2; 7374204Sgblack@eecs.umich.edu else 7384204Sgblack@eecs.umich.edu Frd = Frd; 7394204Sgblack@eecs.umich.edu }}); 7404204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 7414204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 7424204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 7434204Sgblack@eecs.umich.edu Frds = Frs2s; 7444204Sgblack@eecs.umich.edu else 7454204Sgblack@eecs.umich.edu Frds = Frds; 7464204Sgblack@eecs.umich.edu }}); 7474204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 7484204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 7494204Sgblack@eecs.umich.edu Frd = Frs2; 7504204Sgblack@eecs.umich.edu else 7514204Sgblack@eecs.umich.edu Frd = Frd; 7524204Sgblack@eecs.umich.edu }}); 7534204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 7544204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 7554204Sgblack@eecs.umich.edu if(Rs1 != 0) 7564204Sgblack@eecs.umich.edu Frds = Frs2s; 7574204Sgblack@eecs.umich.edu else 7584204Sgblack@eecs.umich.edu Frds = Frds; 7594204Sgblack@eecs.umich.edu }}); 7604204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 7614204Sgblack@eecs.umich.edu if(Rs1 != 0) 7624204Sgblack@eecs.umich.edu Frd = Frs2; 7634204Sgblack@eecs.umich.edu else 7644204Sgblack@eecs.umich.edu Frd = Frd; 7654204Sgblack@eecs.umich.edu }}); 7664204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 7674204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 7684204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 7694204Sgblack@eecs.umich.edu Frds = Frs2s; 7704204Sgblack@eecs.umich.edu else 7714204Sgblack@eecs.umich.edu Frds = Frds; 7724204Sgblack@eecs.umich.edu }}); 7734204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 7744204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 7754204Sgblack@eecs.umich.edu Frd = Frs2; 7764204Sgblack@eecs.umich.edu else 7774204Sgblack@eecs.umich.edu Frd = Frd; 7784204Sgblack@eecs.umich.edu }}); 7794204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 7804204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 7814204Sgblack@eecs.umich.edu if(Rs1 > 0) 7824204Sgblack@eecs.umich.edu Frds = Frs2s; 7834204Sgblack@eecs.umich.edu else 7844204Sgblack@eecs.umich.edu Frds = Frds; 7854204Sgblack@eecs.umich.edu }}); 7864204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 7874204Sgblack@eecs.umich.edu if(Rs1 > 0) 7884204Sgblack@eecs.umich.edu Frd = Frs2; 7894204Sgblack@eecs.umich.edu else 7904204Sgblack@eecs.umich.edu Frd = Frd; 7914204Sgblack@eecs.umich.edu }}); 7924204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 7934204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 7944204Sgblack@eecs.umich.edu if(Rs1 >= 0) 7954204Sgblack@eecs.umich.edu Frds = Frs2s; 7964204Sgblack@eecs.umich.edu else 7974204Sgblack@eecs.umich.edu Frds = Frds; 7984204Sgblack@eecs.umich.edu }}); 7994204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8004204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8014204Sgblack@eecs.umich.edu Frd = Frs2; 8024204Sgblack@eecs.umich.edu else 8034204Sgblack@eecs.umich.edu Frd = Frd; 8044204Sgblack@eecs.umich.edu }}); 8054204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 8064204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 8074204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8084204Sgblack@eecs.umich.edu Frds = Frs2s; 8094204Sgblack@eecs.umich.edu else 8104204Sgblack@eecs.umich.edu Frds = Frds; 8114204Sgblack@eecs.umich.edu }}); 8124204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 8134204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8144204Sgblack@eecs.umich.edu Frd = Frs2; 8154204Sgblack@eecs.umich.edu else 8164204Sgblack@eecs.umich.edu Frd = Frd; 8174204Sgblack@eecs.umich.edu }}); 8184204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 8194204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 8204204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8214204Sgblack@eecs.umich.edu Frds = Frs2s; 8224204Sgblack@eecs.umich.edu else 8234204Sgblack@eecs.umich.edu Frds = Frds; 8244204Sgblack@eecs.umich.edu }}); 8254204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 8264204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8274204Sgblack@eecs.umich.edu Frd = Frs2; 8284204Sgblack@eecs.umich.edu else 8294204Sgblack@eecs.umich.edu Frd = Frd; 8304204Sgblack@eecs.umich.edu }}); 8314204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 8323992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 8333992Sgblack@eecs.umich.edu } 8343992Sgblack@eecs.umich.edu } 8352954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 8362954Sgblack@eecs.umich.edu //of instructions 8372954Sgblack@eecs.umich.edu 0x36: decode OPF{ 8383941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 8393941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 8403941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 8413941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 8423941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 8433941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 8443941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 8453941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 8463941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 8473941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 8483941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 8493941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 8503941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 8513941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 8523941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 8533042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 8542963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8553042Sgblack@eecs.umich.edu Rd = sum & ~7; 8562963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 8572963Sgblack@eecs.umich.edu }}); 8583941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 8592963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 8602963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8613042Sgblack@eecs.umich.edu Rd = sum & ~7; 8622963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 8632963Sgblack@eecs.umich.edu }}); 8643941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 8653941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 8663941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 8673941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 8683941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 8693941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 8703941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 8713941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 8723941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 8733941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 8743941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 8753941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 8763941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 8773941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 8783941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 8792954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 8802954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 8812954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 8822954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 8832963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 8843057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 8853057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 8863057Sgblack@eecs.umich.edu //Some special cases need to be split out, first 8873057Sgblack@eecs.umich.edu //because they're the most likely to be used, and 8883057Sgblack@eecs.umich.edu //second because otherwise, we end up shifting by 8893057Sgblack@eecs.umich.edu //greater than the width of the type being shifted, 8903057Sgblack@eecs.umich.edu //namely 64, which produces undefined results according 8913057Sgblack@eecs.umich.edu //to the C standard. 8923057Sgblack@eecs.umich.edu switch(Gsr<2:0>) 8933057Sgblack@eecs.umich.edu { 8943057Sgblack@eecs.umich.edu case 0: 8953057Sgblack@eecs.umich.edu Frd.udw = msbX; 8963057Sgblack@eecs.umich.edu break; 8973057Sgblack@eecs.umich.edu case 8: 8983057Sgblack@eecs.umich.edu Frd.udw = lsbX; 8993057Sgblack@eecs.umich.edu break; 9003057Sgblack@eecs.umich.edu default: 9013057Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9023057Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9033057Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9043057Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 9053057Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 9063057Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 9073057Sgblack@eecs.umich.edu } 9082963Sgblack@eecs.umich.edu }}); 9092954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 9103941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 9113941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 9123941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 9133941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 9143941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 9153941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 9163941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 9173941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 9183941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 9193941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 9204008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 9214008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 9223941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 9233941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 9243941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 9253941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 9264008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 9272963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 9282963Sgblack@eecs.umich.edu }}); 9294008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 9303279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 9312963Sgblack@eecs.umich.edu }}); 9323941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 9333941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 9344008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 9352963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 9362963Sgblack@eecs.umich.edu }}); 9374008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 9383279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 9392963Sgblack@eecs.umich.edu }}); 9403941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 9413941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 9423941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 9433941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 9443941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 9453941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 9463941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 9473941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 9484008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 9494008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 9503941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 9513941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 9524008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 9534008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 9543941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 9553941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 9563941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 9573941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 9584008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 9594008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 9602954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 9613941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 9622954Sgblack@eecs.umich.edu } 9634090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 9644090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 9654096Sgblack@eecs.umich.edu#if FULL_SYSTEM 9664113Sgblack@eecs.umich.edu format BasicOperate { 9674113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 9684113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 9694113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 9704113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 9714113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 9724113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 9734113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 9744113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 9754113Sgblack@eecs.umich.edu 0x54: m5panic({{ 9764113Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 9774113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 9784113Sgblack@eecs.umich.edu } 9794096Sgblack@eecs.umich.edu#endif 9804096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 9814090Ssaidi@eecs.umich.edu } 9822526SN/A 0x38: Branch::jmpl({{ 9832526SN/A Addr target = Rs1 + Rs2_or_imm13; 9842526SN/A if(target & 0x3) 9852526SN/A fault = new MemAddressNotAligned; 9862526SN/A else 9872526SN/A { 9883928Ssaidi@eecs.umich.edu if (Pstate<3:>) 9893929Ssaidi@eecs.umich.edu Rd = (xc->readPC())<31:0>; 9903928Ssaidi@eecs.umich.edu else 9913928Ssaidi@eecs.umich.edu Rd = xc->readPC(); 9922526SN/A NNPC = target; 9932526SN/A } 9942526SN/A }}); 9952526SN/A 0x39: Branch::return({{ 9962526SN/A Addr target = Rs1 + Rs2_or_imm13; 9972561SN/A if(fault == NoFault) 9982561SN/A { 9993765Sgblack@eecs.umich.edu //Check for fills which are higher priority than alignment 10003765Sgblack@eecs.umich.edu //faults. 10012561SN/A if(Canrestore == 0) 10022561SN/A { 10032561SN/A if(Otherwin) 10043909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10052561SN/A else 10063909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10072561SN/A } 10083765Sgblack@eecs.umich.edu //Check for alignment faults 10093765Sgblack@eecs.umich.edu else if(target & 0x3) 10103765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 10112561SN/A else 10122561SN/A { 10133765Sgblack@eecs.umich.edu NNPC = target; 10143417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10152561SN/A Cansave = Cansave + 1; 10162561SN/A Canrestore = Canrestore - 1; 10172561SN/A } 10182561SN/A } 10192526SN/A }}); 10202526SN/A 0x3A: decode CC 10212526SN/A { 10222526SN/A 0x0: Trap::tcci({{ 10232646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 10242561SN/A { 10252561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10262561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10273531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10282561SN/A } 10294828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10302526SN/A 0x2: Trap::tccx({{ 10312646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 10322561SN/A { 10332561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10342561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10353531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10362526SN/A } 10374828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10382526SN/A } 10394090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 10404090Ssaidi@eecs.umich.edu MemWriteOp); 10412526SN/A 0x3C: save({{ 10422526SN/A if(Cansave == 0) 10432526SN/A { 10442526SN/A if(Otherwin) 10453909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 10462526SN/A else 10473909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 10482526SN/A } 10492526SN/A else if(Cleanwin - Canrestore == 0) 10502526SN/A { 10512526SN/A fault = new CleanWindow; 10522526SN/A } 10532526SN/A else 10542526SN/A { 10552526SN/A Cwp = (Cwp + 1) % NWindows; 10563765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 10572561SN/A Cansave = Cansave - 1; 10582561SN/A Canrestore = Canrestore + 1; 10592526SN/A } 10602526SN/A }}); 10612526SN/A 0x3D: restore({{ 10622526SN/A if(Canrestore == 0) 10632526SN/A { 10642526SN/A if(Otherwin) 10653909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10662526SN/A else 10673909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10682526SN/A } 10692526SN/A else 10702526SN/A { 10713417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10723765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 10732561SN/A Cansave = Cansave + 1; 10742561SN/A Canrestore = Canrestore - 1; 10752526SN/A } 10762526SN/A }}); 10772526SN/A 0x3E: decode FCN { 10782526SN/A 0x0: Priv::done({{ 10792646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 10802646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 10812646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 10822646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 10832646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 10843825Ssaidi@eecs.umich.edu Hpstate = Htstate; 10852646Ssaidi@eecs.umich.edu NPC = Tnpc; 10862646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 10872526SN/A Tl = Tl - 1; 10885094Sgblack@eecs.umich.edu }}, checkTl=true); 10892938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 10902646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 10912646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 10922646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 10932646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 10942646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 10953826Ssaidi@eecs.umich.edu Hpstate = Htstate; 10962646Ssaidi@eecs.umich.edu NPC = Tpc; 10973417Sgblack@eecs.umich.edu NNPC = Tnpc; 10982526SN/A Tl = Tl - 1; 10995094Sgblack@eecs.umich.edu }}, checkTl=true); 11002526SN/A } 11012526SN/A } 11022469SN/A } 11032469SN/A 0x3: decode OP3 { 11042526SN/A format Load { 11053272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 11063272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 11073272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 11083835Sgblack@eecs.umich.edu 0x03: ldtw({{ 11094115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 11104115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 11113272Sgblack@eecs.umich.edu }}); 11122526SN/A } 11132526SN/A format Store { 11143272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 11153272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 11163272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 11174224Sgblack@eecs.umich.edu 0x07: sttw({{ 11184256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 11194256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 11204256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 11214256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 11224256Sgblack@eecs.umich.edu Twin32_t temp; 11234256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 11244256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 11254256Sgblack@eecs.umich.edu Mem.tuw = temp; 11264224Sgblack@eecs.umich.edu }}); 11272526SN/A } 11282526SN/A format Load { 11293272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 11303272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 11313272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 11323272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 11332526SN/A } 11344040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 11354040Ssaidi@eecs.umich.edu {{ 11364040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 11374040Ssaidi@eecs.umich.edu Rd.ub = tmp; 11384040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11393272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 11404040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 11414040Ssaidi@eecs.umich.edu {{ 11424040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 11434040Ssaidi@eecs.umich.edu Rd.uw = tmp; 11444040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11453810Sgblack@eecs.umich.edu format LoadAlt { 11465096Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}); 11475096Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}); 11485096Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}); 11493856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 11503926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUP 11513926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 11524040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11535096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11543926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUS 11553926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 11564040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11575096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11583856Ssaidi@eecs.umich.edu //ASI_QUAD_LDD 11593856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 11604040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11615096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11623856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL 11633856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 11644040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11655096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11664040Ssaidi@eecs.umich.edu //ASI_LDTX_N 11674040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 11684040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11695096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11704040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUP_L 11714040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 11724040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11735096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11744040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUS_L 11754040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 11764040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11775096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11784040Ssaidi@eecs.umich.edu //ASI_LDTX_L 11794040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 11804040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11815096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11823856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL_L 11833856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 11844040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11855096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11863856Ssaidi@eecs.umich.edu //ASI_LDTX_N_L 11873856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 11884040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11895096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11903901Ssaidi@eecs.umich.edu //ASI_LDTX_P 11913901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 11924040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11935096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11943926Ssaidi@eecs.umich.edu //ASI_LDTX_S 11953926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 11964040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11975096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 11984040Ssaidi@eecs.umich.edu //ASI_LDTX_PL 11994040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 12004040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12015096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12024040Ssaidi@eecs.umich.edu //ASI_LDTX_SL 12034040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 12044040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12055096Sgblack@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}); 12063856Ssaidi@eecs.umich.edu default: ldtwa({{ 12074115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12085096Sgblack@eecs.umich.edu RdHigh = (Mem.tuw).b;}}); 12093856Ssaidi@eecs.umich.edu } 12102526SN/A } 12113810Sgblack@eecs.umich.edu format StoreAlt { 12125096Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}); 12135096Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}); 12145096Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}); 12154224Sgblack@eecs.umich.edu 0x17: sttwa({{ 12164256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 12174256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 12184256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 12194256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 12204256Sgblack@eecs.umich.edu Twin32_t temp; 12214256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12224256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12234256Sgblack@eecs.umich.edu Mem.tuw = temp; 12245096Sgblack@eecs.umich.edu }}); 12252526SN/A } 12263810Sgblack@eecs.umich.edu format LoadAlt { 12275096Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 12285096Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 12295096Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 12305096Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 12312526SN/A } 12324040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 12334040Ssaidi@eecs.umich.edu {{ 12344040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12354040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12365096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12375096Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 12384040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 12394040Ssaidi@eecs.umich.edu {{ 12404040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12414040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12425096Sgblack@eecs.umich.edu }}, MEM_SWAP); 12434040Ssaidi@eecs.umich.edu 12442526SN/A format Trap { 12453931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 12464008Ssaidi@eecs.umich.edu 0x21: decode RD { 12474011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 12484011Ssaidi@eecs.umich.edu if (fault) 12494011Ssaidi@eecs.umich.edu return fault; 12504011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 12514011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 12524011Ssaidi@eecs.umich.edu if (fault) 12534011Ssaidi@eecs.umich.edu return fault; 12544011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 12554008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 12562469SN/A } 12572526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 12583272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 12593931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 12604008Ssaidi@eecs.umich.edu 0x25: decode RD { 12615893Sgblack@eecs.umich.edu 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 12625893Sgblack@eecs.umich.edu if (fault) 12635893Sgblack@eecs.umich.edu return fault; 12645893Sgblack@eecs.umich.edu Mem.uw = Fsr<31:0>;}}); 12655893Sgblack@eecs.umich.edu 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 12665893Sgblack@eecs.umich.edu if (fault) 12675893Sgblack@eecs.umich.edu return fault; 12685893Sgblack@eecs.umich.edu Mem.udw = Fsr;}}); 12694008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 12702526SN/A } 12712526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 12723272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 12732526SN/A 0x2D: Nop::prefetch({{ }}); 12745096Sgblack@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 12752526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 12763272Sgblack@eecs.umich.edu format LoadAlt { 12773272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 12783272Sgblack@eecs.umich.edu //ASI_NUCLEUS 12793272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 12803272Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 12813272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 12823272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 12833272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 12843272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 12853272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 12863272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 12873272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 12883272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 12893272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 12903272Sgblack@eecs.umich.edu //ASI_REAL 12913272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 12923272Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 12933272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 12943272Sgblack@eecs.umich.edu //ASI_REAL_IO 12953272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 12963272Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 12973272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 12983272Sgblack@eecs.umich.edu //ASI_PRIMARY 12993272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 13003272Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 13013272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 13023272Sgblack@eecs.umich.edu //ASI_SECONDARY 13033272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 13043272Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 13053272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 13063272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 13073272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 13083272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 13093272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 13103272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 13113272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 13123272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 13133272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 13143272Sgblack@eecs.umich.edu 13153272Sgblack@eecs.umich.edu format BlockLoad { 13163272Sgblack@eecs.umich.edu // LDBLOCKF 13173272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 13183272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 13193272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 13203272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 13213272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 13223272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 13233272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 13243272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 13253272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 13265096Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 13273272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 13283272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 13293272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 13303272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 13313272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 13323272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 13333272Sgblack@eecs.umich.edu } 13343272Sgblack@eecs.umich.edu 13353272Sgblack@eecs.umich.edu //LDSHORTF 13363272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 13373272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 13383272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 13393272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 13403272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 13413272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 13423272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 13433272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 13443272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 13453272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 13463272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 13473272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 13483272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 13493272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 13503272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 13513272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 13523272Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 13533378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 13543378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 13553272Sgblack@eecs.umich.edu } 13563272Sgblack@eecs.umich.edu } 13573931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 13582954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 13593378Sgblack@eecs.umich.edu format StoreAlt { 13603378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 13613378Sgblack@eecs.umich.edu //ASI_NUCLEUS 13623378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 13633378Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 13643378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 13653378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 13663378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 13673378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 13683378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 13693378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 13703378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 13713378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 13723378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 13733378Sgblack@eecs.umich.edu //ASI_REAL 13743378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 13753378Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 13763378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 13773378Sgblack@eecs.umich.edu //ASI_REAL_IO 13783378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 13793378Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 13803378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 13813378Sgblack@eecs.umich.edu //ASI_PRIMARY 13823378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 13833378Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 13843378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 13853378Sgblack@eecs.umich.edu //ASI_SECONDARY 13863378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 13873378Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 13883378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 13893378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 13903378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 13913378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 13923378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 13933378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 13943378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 13953378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 13963378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 13973378Sgblack@eecs.umich.edu 13983378Sgblack@eecs.umich.edu format BlockStore { 13993378Sgblack@eecs.umich.edu // STBLOCKF 14003378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 14013378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 14023378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 14033378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 14043378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14053378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 14063378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14073378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 14083378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 14095096Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 14103378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 14113378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 14123378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 14133378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 14143378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 14153378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 14163378Sgblack@eecs.umich.edu } 14173378Sgblack@eecs.umich.edu 14183378Sgblack@eecs.umich.edu //STSHORTF 14193378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 14203378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 14213378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 14223378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 14233378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 14243378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 14253378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 14263378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 14273378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 14283378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 14293378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 14303378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 14313378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 14323378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 14333378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 14343378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 14353378Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 14363378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 14373378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14383378Sgblack@eecs.umich.edu } 14393378Sgblack@eecs.umich.edu } 14404040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 14414040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 14424040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 14434040Ssaidi@eecs.umich.edu {{ 14444040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 14454040Ssaidi@eecs.umich.edu Rd.uw = tmp; 14465096Sgblack@eecs.umich.edu }}, MEM_SWAP_COND); 14472526SN/A 0x3D: Nop::prefetcha({{ }}); 14484040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 14494040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 14505096Sgblack@eecs.umich.edu {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); 14512526SN/A } 14522469SN/A } 14532022SN/A} 1454