decoder.isa revision 5093
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443598Sgblack@eecs.umich.edu //bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 473056Sgblack@eecs.umich.edu //Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 495091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 505091Sgblack@eecs.umich.edu NNPC = NPC + 4; 515091Sgblack@eecs.umich.edu }}); 523056Sgblack@eecs.umich.edu //Branch Never 535091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 545091Sgblack@eecs.umich.edu annul_code={{ 555091Sgblack@eecs.umich.edu NNPC = NPC + 8; 565091Sgblack@eecs.umich.edu NPC = NPC + 4; 575091Sgblack@eecs.umich.edu }}); 583056Sgblack@eecs.umich.edu default: decode BPCC 593056Sgblack@eecs.umich.edu { 605091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 615091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 623056Sgblack@eecs.umich.edu } 632482SN/A } 643598Sgblack@eecs.umich.edu //bicc 653598Sgblack@eecs.umich.edu 0x2: decode COND2 663598Sgblack@eecs.umich.edu { 673598Sgblack@eecs.umich.edu //Branch Always 685091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 695091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 705091Sgblack@eecs.umich.edu NNPC = NPC + 4; 715091Sgblack@eecs.umich.edu }}); 723598Sgblack@eecs.umich.edu //Branch Never 735091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 745091Sgblack@eecs.umich.edu annul_code={{ 755091Sgblack@eecs.umich.edu NNPC = NPC + 8; 765091Sgblack@eecs.umich.edu NPC = NPC + 4; 775091Sgblack@eecs.umich.edu }}); 785091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 793598Sgblack@eecs.umich.edu } 802516SN/A } 812516SN/A 0x3: decode RCOND2 822516SN/A { 832516SN/A format BranchSplit 842482SN/A { 855091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 865091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 875091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 885091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 895091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 905091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 912469SN/A } 922482SN/A } 932516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 943042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 954004Sgblack@eecs.umich.edu //fbpfcc 964004Sgblack@eecs.umich.edu 0x5: decode COND2 { 974004Sgblack@eecs.umich.edu format BranchN { 984004Sgblack@eecs.umich.edu //Branch Always 995091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1005091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1015091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1025091Sgblack@eecs.umich.edu }}); 1034004Sgblack@eecs.umich.edu //Branch Never 1045091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1055091Sgblack@eecs.umich.edu annul_code={{ 1065091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1075091Sgblack@eecs.umich.edu NPC = NPC + 4; 1085091Sgblack@eecs.umich.edu }}); 1094004Sgblack@eecs.umich.edu default: decode BPCC { 1105091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1115091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1125091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1135091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1145091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1155091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1165091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1175091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1184004Sgblack@eecs.umich.edu } 1194004Sgblack@eecs.umich.edu } 1204004Sgblack@eecs.umich.edu } 1214004Sgblack@eecs.umich.edu //fbfcc 1224004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1234004Sgblack@eecs.umich.edu format BranchN { 1244004Sgblack@eecs.umich.edu //Branch Always 1255091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1265091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1275091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1285091Sgblack@eecs.umich.edu }}); 1294004Sgblack@eecs.umich.edu //Branch Never 1305091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1315091Sgblack@eecs.umich.edu annul_code={{ 1325091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1335091Sgblack@eecs.umich.edu NPC = NPC + 4; 1345091Sgblack@eecs.umich.edu }}); 1355091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1365091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1374004Sgblack@eecs.umich.edu } 1384004Sgblack@eecs.umich.edu } 1392469SN/A } 1402944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1413928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1423928Ssaidi@eecs.umich.edu R15 = (xc->readPC())<31:0>; 1433928Ssaidi@eecs.umich.edu else 1443928Ssaidi@eecs.umich.edu R15 = xc->readPC(); 1452516SN/A NNPC = R15 + disp; 1462469SN/A }}); 1472469SN/A 0x2: decode OP3 { 1482482SN/A format IntOp { 1492482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1502974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1512974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1522974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1532526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1542974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1552974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1562974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1572646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1582974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1592469SN/A 0x0A: umul({{ 1602516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1612646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1622482SN/A }}); 1632469SN/A 0x0B: smul({{ 1643931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1653900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1662482SN/A }}); 1672954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1682469SN/A 0x0D: udivx({{ 1692516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1702516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1712482SN/A }}); 1722469SN/A 0x0E: udiv({{ 1732516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1742482SN/A else 1752482SN/A { 1762646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1772482SN/A if(Rd.udw >> 32 != 0) 1782482SN/A Rd.udw = 0xFFFFFFFF; 1792482SN/A } 1802482SN/A }}); 1812482SN/A 0x0F: sdiv({{ 1822615SN/A if(Rs2_or_imm13.sdw == 0) 1832469SN/A fault = new DivisionByZero; 1842469SN/A else 1852482SN/A { 1862646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1873929Ssaidi@eecs.umich.edu if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 1882482SN/A Rd.udw = 0x7FFFFFFF; 1893929Ssaidi@eecs.umich.edu else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 1903929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 1912482SN/A } 1922526SN/A }}); 1932469SN/A } 1942482SN/A format IntOpCc { 1952469SN/A 0x10: addcc({{ 1965093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 1975093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 1985093Sgblack@eecs.umich.edu }}); 1992482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2002482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2012482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2022469SN/A 0x14: subcc({{ 2035093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2045093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2055093Sgblack@eecs.umich.edu }}, sub=True); 2062482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2072482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2082482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2092469SN/A 0x18: addccc({{ 2105093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2115093Sgblack@eecs.umich.edu Rd = res = op1 + op2 + Ccr<0:>; 2125093Sgblack@eecs.umich.edu }}); 2133765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2142615SN/A uint64_t resTemp; 2152615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2163765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2173765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2182615SN/A int64_t resTemp; 2193931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2203765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2212469SN/A 0x1C: subccc({{ 2225093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2235093Sgblack@eecs.umich.edu Rd = res = op1 - op2 - Ccr<0:>; 2245093Sgblack@eecs.umich.edu }}, sub=True); 2253765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2262615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2273765Sgblack@eecs.umich.edu else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2285093Sgblack@eecs.umich.edu 0x1E: IntOpCcRes::udivcc({{ 2295093Sgblack@eecs.umich.edu uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2305093Sgblack@eecs.umich.edu int32_t overflow = 0; 2315093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2325093Sgblack@eecs.umich.edu else 2335093Sgblack@eecs.umich.edu { 2345093Sgblack@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2355093Sgblack@eecs.umich.edu overflow = (resTemp<63:32> != 0); 2365093Sgblack@eecs.umich.edu if(overflow) Rd = resTemp = 0xFFFFFFFF; 2375093Sgblack@eecs.umich.edu else Rd = resTemp; 2385093Sgblack@eecs.umich.edu } 2395093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2405093Sgblack@eecs.umich.edu 0x1F: IntOpCcRes::sdivcc({{ 2415093Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2425093Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2435093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2445093Sgblack@eecs.umich.edu else 2455093Sgblack@eecs.umich.edu { 2465093Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2475093Sgblack@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2485093Sgblack@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2495093Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 2505093Sgblack@eecs.umich.edu else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 2515093Sgblack@eecs.umich.edu } 2525093Sgblack@eecs.umich.edu }}, iv={{overflow || underflow}}); 2532469SN/A 0x20: taddcc({{ 2545093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2555093Sgblack@eecs.umich.edu Rd = res = Rs1 + op2; 2565093Sgblack@eecs.umich.edu }}, iv={{ 2575093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2585093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2) 2595093Sgblack@eecs.umich.edu }}); 2602469SN/A 0x21: tsubcc({{ 2615093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2625093Sgblack@eecs.umich.edu Rd = res = Rs1 - op2; 2635093Sgblack@eecs.umich.edu }}, iv={{ 2645093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2655093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2) 2665093Sgblack@eecs.umich.edu }}, sub=True); 2672469SN/A 0x22: taddcctv({{ 2685093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2695093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 2705093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2715093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2); 2725093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2735093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2742469SN/A 0x23: tsubcctv({{ 2755093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2765093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2775093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2785093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2); 2795093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2805093Sgblack@eecs.umich.edu }}, iv={{overflow}}, sub=True); 2812469SN/A 0x24: mulscc({{ 2825093Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 2834237Sgblack@eecs.umich.edu 2845093Sgblack@eecs.umich.edu //Step 1 2855093Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 2865093Sgblack@eecs.umich.edu //Step 2 2875093Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 2885093Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 2895093Sgblack@eecs.umich.edu //Step 3 2905093Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 2915093Sgblack@eecs.umich.edu int64_t res, op1 = partialP, op2 = added; 2925093Sgblack@eecs.umich.edu Rd = res = partialP + added; 2935093Sgblack@eecs.umich.edu //Steps 4 & 5 2945093Sgblack@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31); 2955093Sgblack@eecs.umich.edu }}); 2962526SN/A } 2972526SN/A format IntOp 2982526SN/A { 2992526SN/A 0x25: decode X { 3002526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3012526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3022469SN/A } 3032526SN/A 0x26: decode X { 3042526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3052526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3062526SN/A } 3072526SN/A 0x27: decode X { 3082526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3092526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3102526SN/A } 3112954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3123929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3133587Sgblack@eecs.umich.edu //1 should cause an illegal instruction exception 3143587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3153587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3163823Ssaidi@eecs.umich.edu 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3173587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3183587Sgblack@eecs.umich.edu if(Pstate<3:>) 3193587Sgblack@eecs.umich.edu Rd = (xc->readPC())<31:0>; 3203587Sgblack@eecs.umich.edu else 3213587Sgblack@eecs.umich.edu Rd = xc->readPC();}}); 3223587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3233587Sgblack@eecs.umich.edu //Wait for all fpops to finish. 3243587Sgblack@eecs.umich.edu Rd = Fprs; 3253587Sgblack@eecs.umich.edu }}); 3263587Sgblack@eecs.umich.edu //7-14 should cause an illegal instruction exception 3273587Sgblack@eecs.umich.edu 0x0F: decode I { 3284040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3294040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3302954Sgblack@eecs.umich.edu } 3313587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3323587Sgblack@eecs.umich.edu 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3333587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 3343587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3354010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3364010Ssaidi@eecs.umich.edu if (fault) 3374010Ssaidi@eecs.umich.edu return fault; 3384010Ssaidi@eecs.umich.edu Rd = Gsr; 3392954Sgblack@eecs.umich.edu }}); 3403587Sgblack@eecs.umich.edu //0x14-0x15 should cause an illegal instruction exception 3413587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3423823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3433823Ssaidi@eecs.umich.edu 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3443823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3453598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3463598Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 3473598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3483598Sgblack@eecs.umich.edu else 3493598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3503598Sgblack@eecs.umich.edu }}); 3513598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it reads the strand 3523598Sgblack@eecs.umich.edu //status register. 3533598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 3542954Sgblack@eecs.umich.edu } 3553587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3563587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3573587Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{ 3583587Sgblack@eecs.umich.edu if(Tl == 0) 3593587Sgblack@eecs.umich.edu return new IllegalInstruction; 3603587Sgblack@eecs.umich.edu Rd = Htstate; 3613587Sgblack@eecs.umich.edu }}); 3623587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 3633587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 3643587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 3653587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 3663587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 3673587Sgblack@eecs.umich.edu //0x07-0x1E should cause an illegal instruction exception 3683823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 3693587Sgblack@eecs.umich.edu } 3703587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 3713587Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{ 3723587Sgblack@eecs.umich.edu if(Tl == 0) 3733587Sgblack@eecs.umich.edu return new IllegalInstruction; 3743587Sgblack@eecs.umich.edu Rd = Tpc; 3753587Sgblack@eecs.umich.edu }}); 3763587Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{ 3773587Sgblack@eecs.umich.edu if(Tl == 0) 3783587Sgblack@eecs.umich.edu return new IllegalInstruction; 3793587Sgblack@eecs.umich.edu Rd = Tnpc; 3803587Sgblack@eecs.umich.edu }}); 3813587Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{ 3823587Sgblack@eecs.umich.edu if(Tl == 0) 3833587Sgblack@eecs.umich.edu return new IllegalInstruction; 3843587Sgblack@eecs.umich.edu Rd = Tstate; 3853587Sgblack@eecs.umich.edu }}); 3863587Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{ 3873587Sgblack@eecs.umich.edu if(Tl == 0) 3883587Sgblack@eecs.umich.edu return new IllegalInstruction; 3893587Sgblack@eecs.umich.edu Rd = Tt; 3903587Sgblack@eecs.umich.edu }}); 3913823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 3923587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 3933587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 3943587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 3953587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 3963587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 3973587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 3983587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 3993587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 4003587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 4013587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 4023587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 4033587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 4043587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 4053587Sgblack@eecs.umich.edu } 4062526SN/A 0x2B: BasicOperate::flushw({{ 4073911Ssaidi@eecs.umich.edu if(NWindows - 2 - Cansave != 0) 4082526SN/A { 4092526SN/A if(Otherwin) 4103909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 4112526SN/A else 4123909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 4132526SN/A } 4142526SN/A }}); 4152526SN/A 0x2C: decode MOVCC3 4162469SN/A { 4172526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 4182526SN/A 0x1: decode CC 4192526SN/A { 4202526SN/A 0x0: movcci({{ 4212646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 4222591SN/A Rd = Rs2_or_imm11; 4232591SN/A else 4242591SN/A Rd = Rd; 4252526SN/A }}); 4262526SN/A 0x2: movccx({{ 4272646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 4282591SN/A Rd = Rs2_or_imm11; 4292591SN/A else 4302591SN/A Rd = Rd; 4312526SN/A }}); 4322224SN/A } 4332526SN/A } 4342526SN/A 0x2D: sdivx({{ 4352615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 4362615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4372526SN/A }}); 4383941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4392526SN/A 0x2F: decode RCOND3 4402526SN/A { 4412615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4422615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4432615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4442615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4452615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4462615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4472526SN/A } 4483587Sgblack@eecs.umich.edu 0x30: decode RD { 4493929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4503587Sgblack@eecs.umich.edu //0x01 should cause an illegal instruction exception 4513587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4523826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 4533587Sgblack@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 4543587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4553587Sgblack@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 4563587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4573587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 4583587Sgblack@eecs.umich.edu 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 4593587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 4603587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 4613587Sgblack@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 4623587Sgblack@eecs.umich.edu return new FpDisabled; 4633587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 4643587Sgblack@eecs.umich.edu }}); 4653587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 4663587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 4673587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 4683823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4693587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 4703587Sgblack@eecs.umich.edu if(!Hpstate<2:>) 4713587Sgblack@eecs.umich.edu return new IllegalInstruction; 4723823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 4733587Sgblack@eecs.umich.edu }}); 4743823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4753598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 4763598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 4773598Sgblack@eecs.umich.edu }}); 4783598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it writes the strand 4793598Sgblack@eecs.umich.edu //status register. 4803598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 4813587Sgblack@eecs.umich.edu } 4822526SN/A 0x31: decode FCN { 4833417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 4843417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 4853417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 4863417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 4873417Sgblack@eecs.umich.edu if(Otherwin == 0) 4883417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 4893417Sgblack@eecs.umich.edu else 4903417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 4913417Sgblack@eecs.umich.edu }}); 4923598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 4933417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 4943417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 4953417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 4963417Sgblack@eecs.umich.edu if(Otherwin == 0) 4973417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 4983417Sgblack@eecs.umich.edu else 4993417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5003928Ssaidi@eecs.umich.edu 5013928Ssaidi@eecs.umich.edu if(Cleanwin < NWindows - 1) 5023928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 5033417Sgblack@eecs.umich.edu }}); 5042526SN/A } 5053587Sgblack@eecs.umich.edu 0x32: decode RD { 5063587Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc({{ 5073587Sgblack@eecs.umich.edu if(Tl == 0) 5083587Sgblack@eecs.umich.edu return new IllegalInstruction; 5093587Sgblack@eecs.umich.edu else 5103587Sgblack@eecs.umich.edu Tpc = Rs1 ^ Rs2_or_imm13; 5113587Sgblack@eecs.umich.edu }}); 5123587Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc({{ 5133587Sgblack@eecs.umich.edu if(Tl == 0) 5143587Sgblack@eecs.umich.edu return new IllegalInstruction; 5153587Sgblack@eecs.umich.edu else 5163587Sgblack@eecs.umich.edu Tnpc = Rs1 ^ Rs2_or_imm13; 5173587Sgblack@eecs.umich.edu }}); 5183587Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate({{ 5193587Sgblack@eecs.umich.edu if(Tl == 0) 5203587Sgblack@eecs.umich.edu return new IllegalInstruction; 5213587Sgblack@eecs.umich.edu else 5223587Sgblack@eecs.umich.edu Tstate = Rs1 ^ Rs2_or_imm13; 5233587Sgblack@eecs.umich.edu }}); 5243587Sgblack@eecs.umich.edu 0x03: Priv::wrprtt({{ 5253587Sgblack@eecs.umich.edu if(Tl == 0) 5263587Sgblack@eecs.umich.edu return new IllegalInstruction; 5273587Sgblack@eecs.umich.edu else 5283587Sgblack@eecs.umich.edu Tt = Rs1 ^ Rs2_or_imm13; 5293587Sgblack@eecs.umich.edu }}); 5303823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 5313587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 5323587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 5333587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 5343587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5353587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5363587Sgblack@eecs.umich.edu else 5373587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5383587Sgblack@eecs.umich.edu }}); 5393587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5403587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5413587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5423587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5433587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5443587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5453587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5463587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 5473587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5483587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5493587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5503587Sgblack@eecs.umich.edu else 5513587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5523587Sgblack@eecs.umich.edu }}); 5533587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 5543587Sgblack@eecs.umich.edu } 5553587Sgblack@eecs.umich.edu 0x33: decode RD { 5563587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5573587Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate({{ 5583587Sgblack@eecs.umich.edu if(Tl == 0) 5593587Sgblack@eecs.umich.edu return new IllegalInstruction; 5603587Sgblack@eecs.umich.edu Htstate = Rs1 ^ Rs2_or_imm13; 5613587Sgblack@eecs.umich.edu }}); 5623587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 5633587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 5643587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 5653587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 5663587Sgblack@eecs.umich.edu //0x06-0x01D should cause an illegal instruction exception 5673823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5683587Sgblack@eecs.umich.edu } 5692954Sgblack@eecs.umich.edu 0x34: decode OPF{ 5704008Ssaidi@eecs.umich.edu format FpBasic{ 5712963Sgblack@eecs.umich.edu 0x01: fmovs({{ 5723279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw; 5732963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5742963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5752963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5762963Sgblack@eecs.umich.edu }}); 5772963Sgblack@eecs.umich.edu 0x02: fmovd({{ 5783057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw; 5792963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5802963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5812963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5822963Sgblack@eecs.umich.edu }}); 5833995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 5842963Sgblack@eecs.umich.edu 0x05: fnegs({{ 5853279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw ^ (1UL << 31); 5862963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5872963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5882963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5892963Sgblack@eecs.umich.edu }}); 5902963Sgblack@eecs.umich.edu 0x06: fnegd({{ 5913057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw ^ (1ULL << 63); 5922963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5932963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5942963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5952963Sgblack@eecs.umich.edu }}); 5963995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 5972963Sgblack@eecs.umich.edu 0x09: fabss({{ 5983279Sgblack@eecs.umich.edu Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 5992963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6002963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6012963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6022963Sgblack@eecs.umich.edu }}); 6032963Sgblack@eecs.umich.edu 0x0A: fabsd({{ 6043057Sgblack@eecs.umich.edu Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 6052963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6062963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6072963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6082963Sgblack@eecs.umich.edu }}); 6093995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 6103918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 6113918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 6123995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 6133279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 6142963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 6153995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 6163279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 6174008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 6183995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 6193279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 6202963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 6213995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 6223279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 6232963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 6243995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 6253279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 6263995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 6272963Sgblack@eecs.umich.edu 0x81: fstox({{ 6284008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2s.sf); 6292963Sgblack@eecs.umich.edu }}); 6302963Sgblack@eecs.umich.edu 0x82: fdtox({{ 6314008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2.df); 6322963Sgblack@eecs.umich.edu }}); 6333995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 6342963Sgblack@eecs.umich.edu 0x84: fxtos({{ 6354008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2.sdw); 6362963Sgblack@eecs.umich.edu }}); 6372963Sgblack@eecs.umich.edu 0x88: fxtod({{ 6384008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2.sdw); 6392963Sgblack@eecs.umich.edu }}); 6403995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 6412963Sgblack@eecs.umich.edu 0xC4: fitos({{ 6424008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2s.sw); 6432963Sgblack@eecs.umich.edu }}); 6443279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 6453995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 6462963Sgblack@eecs.umich.edu 0xC8: fitod({{ 6474008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2s.sw); 6482963Sgblack@eecs.umich.edu }}); 6493279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 6503995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 6513995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 6523995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 6533995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6542963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6554008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6564008Ssaidi@eecs.umich.edu float t = Frds.sw; 6574008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6584008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6592963Sgblack@eecs.umich.edu }}); 6602963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 6614008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 6624008Ssaidi@eecs.umich.edu double t = Frds.sw; 6634008Ssaidi@eecs.umich.edu if (t != Frs2.df) 6644008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6652963Sgblack@eecs.umich.edu }}); 6663995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 6673941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 6682963Sgblack@eecs.umich.edu } 6692954Sgblack@eecs.umich.edu } 6703992Sgblack@eecs.umich.edu 0x35: decode OPF{ 6714008Ssaidi@eecs.umich.edu format FpBasic{ 6724204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 6734204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6744204Sgblack@eecs.umich.edu Frds = Frs2s; 6754204Sgblack@eecs.umich.edu else 6764204Sgblack@eecs.umich.edu Frds = Frds; 6774204Sgblack@eecs.umich.edu }}); 6784204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 6794204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6804204Sgblack@eecs.umich.edu Frd = Frs2; 6814204Sgblack@eecs.umich.edu else 6824204Sgblack@eecs.umich.edu Frd = Frd; 6834204Sgblack@eecs.umich.edu }}); 6844204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 6854204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 6864204Sgblack@eecs.umich.edu if(Rs1 == 0) 6874204Sgblack@eecs.umich.edu Frds = Frs2s; 6884204Sgblack@eecs.umich.edu else 6894204Sgblack@eecs.umich.edu Frds = Frds; 6904204Sgblack@eecs.umich.edu }}); 6914204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 6924204Sgblack@eecs.umich.edu if(Rs1 == 0) 6934204Sgblack@eecs.umich.edu Frd = Frs2; 6944204Sgblack@eecs.umich.edu else 6954204Sgblack@eecs.umich.edu Frd = Frd; 6964204Sgblack@eecs.umich.edu }}); 6974204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 6984204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 6994204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 7004204Sgblack@eecs.umich.edu Frds = Frs2s; 7014204Sgblack@eecs.umich.edu else 7024204Sgblack@eecs.umich.edu Frds = Frds; 7034204Sgblack@eecs.umich.edu }}); 7044204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 7054204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 7064204Sgblack@eecs.umich.edu Frd = Frs2; 7074204Sgblack@eecs.umich.edu else 7084204Sgblack@eecs.umich.edu Frd = Frd; 7094204Sgblack@eecs.umich.edu }}); 7104204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 7114204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 7124204Sgblack@eecs.umich.edu if(Rs1 <= 0) 7134204Sgblack@eecs.umich.edu Frds = Frs2s; 7144204Sgblack@eecs.umich.edu else 7154204Sgblack@eecs.umich.edu Frds = Frds; 7164204Sgblack@eecs.umich.edu }}); 7174204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 7184204Sgblack@eecs.umich.edu if(Rs1 <= 0) 7194204Sgblack@eecs.umich.edu Frd = Frs2; 7204204Sgblack@eecs.umich.edu else 7214204Sgblack@eecs.umich.edu Frd = Frd; 7224204Sgblack@eecs.umich.edu }}); 7234204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 7243992Sgblack@eecs.umich.edu 0x51: fcmps({{ 7253992Sgblack@eecs.umich.edu uint8_t fcc; 7263998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7273992Sgblack@eecs.umich.edu fcc = 3; 7283992Sgblack@eecs.umich.edu else if(Frs1s < Frs2s) 7293992Sgblack@eecs.umich.edu fcc = 1; 7303992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 7313992Sgblack@eecs.umich.edu fcc = 2; 7323992Sgblack@eecs.umich.edu else 7333992Sgblack@eecs.umich.edu fcc = 0; 7343992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7353992Sgblack@eecs.umich.edu if(FCMPCC) 7363992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7373992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7383992Sgblack@eecs.umich.edu }}); 7393992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 7403992Sgblack@eecs.umich.edu uint8_t fcc; 7414008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7423992Sgblack@eecs.umich.edu fcc = 3; 7434008Ssaidi@eecs.umich.edu else if(Frs1 < Frs2) 7443992Sgblack@eecs.umich.edu fcc = 1; 7454008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7463992Sgblack@eecs.umich.edu fcc = 2; 7473992Sgblack@eecs.umich.edu else 7483992Sgblack@eecs.umich.edu fcc = 0; 7493992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7503992Sgblack@eecs.umich.edu if(FCMPCC) 7513992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7523992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7533992Sgblack@eecs.umich.edu }}); 7543995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7553997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7563992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7573998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7583992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7593992Sgblack@eecs.umich.edu if(Frs1s < Frs2s) 7603992Sgblack@eecs.umich.edu fcc = 1; 7613992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 7623992Sgblack@eecs.umich.edu fcc = 2; 7633992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7643992Sgblack@eecs.umich.edu if(FCMPCC) 7653992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7663992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7673992Sgblack@eecs.umich.edu }}); 7683997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 7693992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7704008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7713992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7724008Ssaidi@eecs.umich.edu if(Frs1 < Frs2) 7733992Sgblack@eecs.umich.edu fcc = 1; 7744008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7753992Sgblack@eecs.umich.edu fcc = 2; 7763992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7773992Sgblack@eecs.umich.edu if(FCMPCC) 7783992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7793992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7803992Sgblack@eecs.umich.edu }}); 7813997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 7824204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 7834204Sgblack@eecs.umich.edu if(Rs1 < 0) 7844204Sgblack@eecs.umich.edu Frds = Frs2s; 7854204Sgblack@eecs.umich.edu else 7864204Sgblack@eecs.umich.edu Frds = Frds; 7874204Sgblack@eecs.umich.edu }}); 7884204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 7894204Sgblack@eecs.umich.edu if(Rs1 < 0) 7904204Sgblack@eecs.umich.edu Frd = Frs2; 7914204Sgblack@eecs.umich.edu else 7924204Sgblack@eecs.umich.edu Frd = Frd; 7934204Sgblack@eecs.umich.edu }}); 7944204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 7954204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 7964204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 7974204Sgblack@eecs.umich.edu Frds = Frs2s; 7984204Sgblack@eecs.umich.edu else 7994204Sgblack@eecs.umich.edu Frds = Frds; 8004204Sgblack@eecs.umich.edu }}); 8014204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 8024204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 8034204Sgblack@eecs.umich.edu Frd = Frs2; 8044204Sgblack@eecs.umich.edu else 8054204Sgblack@eecs.umich.edu Frd = Frd; 8064204Sgblack@eecs.umich.edu }}); 8074204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 8084204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 8094204Sgblack@eecs.umich.edu if(Rs1 != 0) 8104204Sgblack@eecs.umich.edu Frds = Frs2s; 8114204Sgblack@eecs.umich.edu else 8124204Sgblack@eecs.umich.edu Frds = Frds; 8134204Sgblack@eecs.umich.edu }}); 8144204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 8154204Sgblack@eecs.umich.edu if(Rs1 != 0) 8164204Sgblack@eecs.umich.edu Frd = Frs2; 8174204Sgblack@eecs.umich.edu else 8184204Sgblack@eecs.umich.edu Frd = Frd; 8194204Sgblack@eecs.umich.edu }}); 8204204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 8214204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 8224204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 8234204Sgblack@eecs.umich.edu Frds = Frs2s; 8244204Sgblack@eecs.umich.edu else 8254204Sgblack@eecs.umich.edu Frds = Frds; 8264204Sgblack@eecs.umich.edu }}); 8274204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 8284204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 8294204Sgblack@eecs.umich.edu Frd = Frs2; 8304204Sgblack@eecs.umich.edu else 8314204Sgblack@eecs.umich.edu Frd = Frd; 8324204Sgblack@eecs.umich.edu }}); 8334204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 8344204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 8354204Sgblack@eecs.umich.edu if(Rs1 > 0) 8364204Sgblack@eecs.umich.edu Frds = Frs2s; 8374204Sgblack@eecs.umich.edu else 8384204Sgblack@eecs.umich.edu Frds = Frds; 8394204Sgblack@eecs.umich.edu }}); 8404204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 8414204Sgblack@eecs.umich.edu if(Rs1 > 0) 8424204Sgblack@eecs.umich.edu Frd = Frs2; 8434204Sgblack@eecs.umich.edu else 8444204Sgblack@eecs.umich.edu Frd = Frd; 8454204Sgblack@eecs.umich.edu }}); 8464204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 8474204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 8484204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8494204Sgblack@eecs.umich.edu Frds = Frs2s; 8504204Sgblack@eecs.umich.edu else 8514204Sgblack@eecs.umich.edu Frds = Frds; 8524204Sgblack@eecs.umich.edu }}); 8534204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8544204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8554204Sgblack@eecs.umich.edu Frd = Frs2; 8564204Sgblack@eecs.umich.edu else 8574204Sgblack@eecs.umich.edu Frd = Frd; 8584204Sgblack@eecs.umich.edu }}); 8594204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 8604204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 8614204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8624204Sgblack@eecs.umich.edu Frds = Frs2s; 8634204Sgblack@eecs.umich.edu else 8644204Sgblack@eecs.umich.edu Frds = Frds; 8654204Sgblack@eecs.umich.edu }}); 8664204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 8674204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8684204Sgblack@eecs.umich.edu Frd = Frs2; 8694204Sgblack@eecs.umich.edu else 8704204Sgblack@eecs.umich.edu Frd = Frd; 8714204Sgblack@eecs.umich.edu }}); 8724204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 8734204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 8744204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8754204Sgblack@eecs.umich.edu Frds = Frs2s; 8764204Sgblack@eecs.umich.edu else 8774204Sgblack@eecs.umich.edu Frds = Frds; 8784204Sgblack@eecs.umich.edu }}); 8794204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 8804204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8814204Sgblack@eecs.umich.edu Frd = Frs2; 8824204Sgblack@eecs.umich.edu else 8834204Sgblack@eecs.umich.edu Frd = Frd; 8844204Sgblack@eecs.umich.edu }}); 8854204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 8863992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 8873992Sgblack@eecs.umich.edu } 8883992Sgblack@eecs.umich.edu } 8892954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 8902954Sgblack@eecs.umich.edu //of instructions 8912954Sgblack@eecs.umich.edu 0x36: decode OPF{ 8923941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 8933941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 8943941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 8953941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 8963941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 8973941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 8983941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 8993941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 9003941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 9013941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 9023941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 9033941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 9043941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 9053941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 9063941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 9073042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 9082963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 9093042Sgblack@eecs.umich.edu Rd = sum & ~7; 9102963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 9112963Sgblack@eecs.umich.edu }}); 9123941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 9132963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 9142963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 9153042Sgblack@eecs.umich.edu Rd = sum & ~7; 9162963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 9172963Sgblack@eecs.umich.edu }}); 9183941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 9193941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 9203941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 9213941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 9223941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 9233941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 9243941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 9253941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 9263941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 9273941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 9283941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 9293941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 9303941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 9313941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 9323941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 9332954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 9342954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 9352954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 9362954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 9372963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 9383057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 9393057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 9403057Sgblack@eecs.umich.edu //Some special cases need to be split out, first 9413057Sgblack@eecs.umich.edu //because they're the most likely to be used, and 9423057Sgblack@eecs.umich.edu //second because otherwise, we end up shifting by 9433057Sgblack@eecs.umich.edu //greater than the width of the type being shifted, 9443057Sgblack@eecs.umich.edu //namely 64, which produces undefined results according 9453057Sgblack@eecs.umich.edu //to the C standard. 9463057Sgblack@eecs.umich.edu switch(Gsr<2:0>) 9473057Sgblack@eecs.umich.edu { 9483057Sgblack@eecs.umich.edu case 0: 9493057Sgblack@eecs.umich.edu Frd.udw = msbX; 9503057Sgblack@eecs.umich.edu break; 9513057Sgblack@eecs.umich.edu case 8: 9523057Sgblack@eecs.umich.edu Frd.udw = lsbX; 9533057Sgblack@eecs.umich.edu break; 9543057Sgblack@eecs.umich.edu default: 9553057Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9563057Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9573057Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9583057Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 9593057Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 9603057Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 9613057Sgblack@eecs.umich.edu } 9622963Sgblack@eecs.umich.edu }}); 9632954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 9643941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 9653941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 9663941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 9673941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 9683941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 9693941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 9703941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 9713941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 9723941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 9733941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 9744008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 9754008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 9763941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 9773941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 9783941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 9793941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 9804008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 9812963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 9822963Sgblack@eecs.umich.edu }}); 9834008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 9843279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 9852963Sgblack@eecs.umich.edu }}); 9863941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 9873941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 9884008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 9892963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 9902963Sgblack@eecs.umich.edu }}); 9914008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 9923279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 9932963Sgblack@eecs.umich.edu }}); 9943941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 9953941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 9963941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 9973941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 9983941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 9993941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 10003941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 10013941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 10024008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 10034008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 10043941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 10053941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 10064008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 10074008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 10083941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 10093941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 10103941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 10113941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 10124008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 10134008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 10142954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 10153941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 10162954Sgblack@eecs.umich.edu } 10174090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 10184090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 10194096Sgblack@eecs.umich.edu#if FULL_SYSTEM 10204113Sgblack@eecs.umich.edu format BasicOperate { 10214113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 10224113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 10234113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10244113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 10254113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 10264113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10274113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 10284113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10294113Sgblack@eecs.umich.edu 0x54: m5panic({{ 10304113Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 10314113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10324113Sgblack@eecs.umich.edu } 10334096Sgblack@eecs.umich.edu#endif 10344096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 10354090Ssaidi@eecs.umich.edu } 10362526SN/A 0x38: Branch::jmpl({{ 10372526SN/A Addr target = Rs1 + Rs2_or_imm13; 10382526SN/A if(target & 0x3) 10392526SN/A fault = new MemAddressNotAligned; 10402526SN/A else 10412526SN/A { 10423928Ssaidi@eecs.umich.edu if (Pstate<3:>) 10433929Ssaidi@eecs.umich.edu Rd = (xc->readPC())<31:0>; 10443928Ssaidi@eecs.umich.edu else 10453928Ssaidi@eecs.umich.edu Rd = xc->readPC(); 10462526SN/A NNPC = target; 10472526SN/A } 10482526SN/A }}); 10492526SN/A 0x39: Branch::return({{ 10502526SN/A Addr target = Rs1 + Rs2_or_imm13; 10512561SN/A if(fault == NoFault) 10522561SN/A { 10533765Sgblack@eecs.umich.edu //Check for fills which are higher priority than alignment 10543765Sgblack@eecs.umich.edu //faults. 10552561SN/A if(Canrestore == 0) 10562561SN/A { 10572561SN/A if(Otherwin) 10583909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10592561SN/A else 10603909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10612561SN/A } 10623765Sgblack@eecs.umich.edu //Check for alignment faults 10633765Sgblack@eecs.umich.edu else if(target & 0x3) 10643765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 10652561SN/A else 10662561SN/A { 10673765Sgblack@eecs.umich.edu NNPC = target; 10683417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10692561SN/A Cansave = Cansave + 1; 10702561SN/A Canrestore = Canrestore - 1; 10712561SN/A } 10722561SN/A } 10732526SN/A }}); 10742526SN/A 0x3A: decode CC 10752526SN/A { 10762526SN/A 0x0: Trap::tcci({{ 10772646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 10782561SN/A { 10792561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10802561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10813531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10822561SN/A } 10834828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10842526SN/A 0x2: Trap::tccx({{ 10852646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 10862561SN/A { 10872561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10882561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10893531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10902526SN/A } 10914828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10922526SN/A } 10934090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 10944090Ssaidi@eecs.umich.edu MemWriteOp); 10952526SN/A 0x3C: save({{ 10962526SN/A if(Cansave == 0) 10972526SN/A { 10982526SN/A if(Otherwin) 10993909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 11002526SN/A else 11013909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 11022526SN/A } 11032526SN/A else if(Cleanwin - Canrestore == 0) 11042526SN/A { 11052526SN/A fault = new CleanWindow; 11062526SN/A } 11072526SN/A else 11082526SN/A { 11092526SN/A Cwp = (Cwp + 1) % NWindows; 11103765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 11112561SN/A Cansave = Cansave - 1; 11122561SN/A Canrestore = Canrestore + 1; 11132526SN/A } 11142526SN/A }}); 11152526SN/A 0x3D: restore({{ 11162526SN/A if(Canrestore == 0) 11172526SN/A { 11182526SN/A if(Otherwin) 11193909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 11202526SN/A else 11213909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 11222526SN/A } 11232526SN/A else 11242526SN/A { 11253417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 11263765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 11272561SN/A Cansave = Cansave + 1; 11282561SN/A Canrestore = Canrestore - 1; 11292526SN/A } 11302526SN/A }}); 11312526SN/A 0x3E: decode FCN { 11322526SN/A 0x0: Priv::done({{ 11332526SN/A if(Tl == 0) 11342526SN/A return new IllegalInstruction; 11352646Ssaidi@eecs.umich.edu 11362646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11372646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11382646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11392646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11402646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11413825Ssaidi@eecs.umich.edu Hpstate = Htstate; 11422646Ssaidi@eecs.umich.edu NPC = Tnpc; 11432646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 11442526SN/A Tl = Tl - 1; 11452526SN/A }}); 11462938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 11472526SN/A if(Tl == 0) 11482526SN/A return new IllegalInstruction; 11492646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11502646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11512646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11522646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11532646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11543826Ssaidi@eecs.umich.edu Hpstate = Htstate; 11552646Ssaidi@eecs.umich.edu NPC = Tpc; 11563417Sgblack@eecs.umich.edu NNPC = Tnpc; 11572526SN/A Tl = Tl - 1; 11582526SN/A }}); 11592526SN/A } 11602526SN/A } 11612469SN/A } 11622469SN/A 0x3: decode OP3 { 11632526SN/A format Load { 11643272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 11653272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 11663272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 11673835Sgblack@eecs.umich.edu 0x03: ldtw({{ 11684115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 11694115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 11703272Sgblack@eecs.umich.edu }}); 11712526SN/A } 11722526SN/A format Store { 11733272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 11743272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 11753272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 11764224Sgblack@eecs.umich.edu 0x07: sttw({{ 11774256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 11784256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 11794256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 11804256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 11814256Sgblack@eecs.umich.edu Twin32_t temp; 11824256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 11834256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 11844256Sgblack@eecs.umich.edu Mem.tuw = temp; 11854224Sgblack@eecs.umich.edu }}); 11862526SN/A } 11872526SN/A format Load { 11883272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 11893272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 11903272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 11913272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 11922526SN/A } 11934040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 11944040Ssaidi@eecs.umich.edu {{ 11954040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 11964040Ssaidi@eecs.umich.edu Rd.ub = tmp; 11974040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11983272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 11994040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 12004040Ssaidi@eecs.umich.edu {{ 12014040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12024040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12034040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 12043810Sgblack@eecs.umich.edu format LoadAlt { 12053810Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 12063810Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 12073810Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 12083856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 12093926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUP 12103926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 12114040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12124040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12133926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUS 12143926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 12154040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12164040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12173856Ssaidi@eecs.umich.edu //ASI_QUAD_LDD 12183856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 12194040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12204040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12213856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL 12223856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 12234040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12244040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12254040Ssaidi@eecs.umich.edu //ASI_LDTX_N 12264040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 12274040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12284040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12294040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUP_L 12304040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 12314040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12324040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12334040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUS_L 12344040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 12354040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12364040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12374040Ssaidi@eecs.umich.edu //ASI_LDTX_L 12384040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 12394040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12404040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12413856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL_L 12423856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 12434040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12444040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12453856Ssaidi@eecs.umich.edu //ASI_LDTX_N_L 12463856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 12474040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12484040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12493901Ssaidi@eecs.umich.edu //ASI_LDTX_P 12503901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 12514040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12524040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12533926Ssaidi@eecs.umich.edu //ASI_LDTX_S 12543926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 12554040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12564040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12574040Ssaidi@eecs.umich.edu //ASI_LDTX_PL 12584040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 12594040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12604040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12614040Ssaidi@eecs.umich.edu //ASI_LDTX_SL 12624040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 12634040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12644040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12653856Ssaidi@eecs.umich.edu default: ldtwa({{ 12664115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12674115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 12683856Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}); 12693856Ssaidi@eecs.umich.edu } 12702526SN/A } 12713810Sgblack@eecs.umich.edu format StoreAlt { 12723810Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 12733810Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 12743810Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 12754224Sgblack@eecs.umich.edu 0x17: sttwa({{ 12764256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 12774256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 12784256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 12794256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 12804256Sgblack@eecs.umich.edu Twin32_t temp; 12814256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12824256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12834256Sgblack@eecs.umich.edu Mem.tuw = temp; 12844224Sgblack@eecs.umich.edu }}, {{EXT_ASI}}); 12852526SN/A } 12863810Sgblack@eecs.umich.edu format LoadAlt { 12873810Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 12883810Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 12893810Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 12903810Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 12912526SN/A } 12924040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 12934040Ssaidi@eecs.umich.edu {{ 12944040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12954040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12964040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 12973810Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 12984040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 12994040Ssaidi@eecs.umich.edu {{ 13004040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 13014040Ssaidi@eecs.umich.edu Rd.uw = tmp; 13024040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 13034040Ssaidi@eecs.umich.edu 13042526SN/A format Trap { 13053931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 13064008Ssaidi@eecs.umich.edu 0x21: decode RD { 13074011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 13084011Ssaidi@eecs.umich.edu if (fault) 13094011Ssaidi@eecs.umich.edu return fault; 13104011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 13114011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 13124011Ssaidi@eecs.umich.edu if (fault) 13134011Ssaidi@eecs.umich.edu return fault; 13144011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 13154008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 13162469SN/A } 13172526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 13183272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 13193931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 13204008Ssaidi@eecs.umich.edu 0x25: decode RD { 13214011Ssaidi@eecs.umich.edu 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 13224011Ssaidi@eecs.umich.edu if (fault) 13234011Ssaidi@eecs.umich.edu return fault; 13244011Ssaidi@eecs.umich.edu Mem.uw = Fsr<31:0>; 13254008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 13264011Ssaidi@eecs.umich.edu 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 13274011Ssaidi@eecs.umich.edu if (fault) 13284011Ssaidi@eecs.umich.edu return fault; 13294011Ssaidi@eecs.umich.edu Mem.udw = Fsr; 13304011Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 13314008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 13322526SN/A } 13332526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 13343272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 13352526SN/A 0x2D: Nop::prefetch({{ }}); 13363931Ssaidi@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 13372526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 13383272Sgblack@eecs.umich.edu format LoadAlt { 13393272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 13403272Sgblack@eecs.umich.edu //ASI_NUCLEUS 13413272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 13423272Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 13433272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 13443272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 13453272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 13463272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 13473272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 13483272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 13493272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 13503272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 13513272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 13523272Sgblack@eecs.umich.edu //ASI_REAL 13533272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 13543272Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 13553272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 13563272Sgblack@eecs.umich.edu //ASI_REAL_IO 13573272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 13583272Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 13593272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 13603272Sgblack@eecs.umich.edu //ASI_PRIMARY 13613272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 13623272Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 13633272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 13643272Sgblack@eecs.umich.edu //ASI_SECONDARY 13653272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 13663272Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 13673272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 13683272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 13693272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 13703272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 13713272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 13723272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 13733272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 13743272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 13753272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 13763272Sgblack@eecs.umich.edu 13773272Sgblack@eecs.umich.edu format BlockLoad { 13783272Sgblack@eecs.umich.edu // LDBLOCKF 13793272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 13803272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 13813272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 13823272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 13833272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 13843272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 13853272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 13863272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 13873272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 13883810Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 13893272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 13903272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 13913272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 13923272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 13933272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 13943272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 13953272Sgblack@eecs.umich.edu } 13963272Sgblack@eecs.umich.edu 13973272Sgblack@eecs.umich.edu //LDSHORTF 13983272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 13993272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 14003272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 14013272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 14023272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 14033272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 14043272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 14053272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 14063272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 14073272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 14083272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 14093272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 14103272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 14113272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 14123272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 14133272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 14143272Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 14153378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 14163378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14173272Sgblack@eecs.umich.edu } 14183272Sgblack@eecs.umich.edu } 14193931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 14202954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 14213378Sgblack@eecs.umich.edu format StoreAlt { 14223378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 14233378Sgblack@eecs.umich.edu //ASI_NUCLEUS 14243378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 14253378Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 14263378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 14273378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 14283378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 14293378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 14303378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 14313378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 14323378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 14333378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 14343378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 14353378Sgblack@eecs.umich.edu //ASI_REAL 14363378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 14373378Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 14383378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 14393378Sgblack@eecs.umich.edu //ASI_REAL_IO 14403378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 14413378Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 14423378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 14433378Sgblack@eecs.umich.edu //ASI_PRIMARY 14443378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 14453378Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 14463378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 14473378Sgblack@eecs.umich.edu //ASI_SECONDARY 14483378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 14493378Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 14503378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 14513378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 14523378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 14533378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 14543378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 14553378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 14563378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 14573378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 14583378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 14593378Sgblack@eecs.umich.edu 14603378Sgblack@eecs.umich.edu format BlockStore { 14613378Sgblack@eecs.umich.edu // STBLOCKF 14623378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 14633378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 14643378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 14653378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 14663378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14673378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 14683378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14693378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 14703378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 14713810Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 14723378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 14733378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 14743378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 14753378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 14763378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 14773378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 14783378Sgblack@eecs.umich.edu } 14793378Sgblack@eecs.umich.edu 14803378Sgblack@eecs.umich.edu //STSHORTF 14813378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 14823378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 14833378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 14843378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 14853378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 14863378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 14873378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 14883378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 14893378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 14903378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 14913378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 14923378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 14933378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 14943378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 14953378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 14963378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 14973378Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 14983378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 14993378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 15003378Sgblack@eecs.umich.edu } 15013378Sgblack@eecs.umich.edu } 15024040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 15034040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 15044040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 15054040Ssaidi@eecs.umich.edu {{ 15064040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 15074040Ssaidi@eecs.umich.edu Rd.uw = tmp; 15084040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP_COND); 15092526SN/A 0x3D: Nop::prefetcha({{ }}); 15104040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 15114040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 15124040Ssaidi@eecs.umich.edu {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 15132526SN/A } 15142469SN/A } 15152022SN/A} 1516