decoder.isa revision 5091
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443598Sgblack@eecs.umich.edu //bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 473056Sgblack@eecs.umich.edu //Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 495091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 505091Sgblack@eecs.umich.edu NNPC = NPC + 4; 515091Sgblack@eecs.umich.edu }}); 523056Sgblack@eecs.umich.edu //Branch Never 535091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 545091Sgblack@eecs.umich.edu annul_code={{ 555091Sgblack@eecs.umich.edu NNPC = NPC + 8; 565091Sgblack@eecs.umich.edu NPC = NPC + 4; 575091Sgblack@eecs.umich.edu }}); 583056Sgblack@eecs.umich.edu default: decode BPCC 593056Sgblack@eecs.umich.edu { 605091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 615091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 623056Sgblack@eecs.umich.edu } 632482SN/A } 643598Sgblack@eecs.umich.edu //bicc 653598Sgblack@eecs.umich.edu 0x2: decode COND2 663598Sgblack@eecs.umich.edu { 673598Sgblack@eecs.umich.edu //Branch Always 685091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 695091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 705091Sgblack@eecs.umich.edu NNPC = NPC + 4; 715091Sgblack@eecs.umich.edu }}); 723598Sgblack@eecs.umich.edu //Branch Never 735091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 745091Sgblack@eecs.umich.edu annul_code={{ 755091Sgblack@eecs.umich.edu NNPC = NPC + 8; 765091Sgblack@eecs.umich.edu NPC = NPC + 4; 775091Sgblack@eecs.umich.edu }}); 785091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 793598Sgblack@eecs.umich.edu } 802516SN/A } 812516SN/A 0x3: decode RCOND2 822516SN/A { 832516SN/A format BranchSplit 842482SN/A { 855091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 865091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 875091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 885091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 895091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 905091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 912469SN/A } 922482SN/A } 932516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 943042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 954004Sgblack@eecs.umich.edu //fbpfcc 964004Sgblack@eecs.umich.edu 0x5: decode COND2 { 974004Sgblack@eecs.umich.edu format BranchN { 984004Sgblack@eecs.umich.edu //Branch Always 995091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1005091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1015091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1025091Sgblack@eecs.umich.edu }}); 1034004Sgblack@eecs.umich.edu //Branch Never 1045091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1055091Sgblack@eecs.umich.edu annul_code={{ 1065091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1075091Sgblack@eecs.umich.edu NPC = NPC + 4; 1085091Sgblack@eecs.umich.edu }}); 1094004Sgblack@eecs.umich.edu default: decode BPCC { 1105091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1115091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1125091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1135091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1145091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1155091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1165091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1175091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1184004Sgblack@eecs.umich.edu } 1194004Sgblack@eecs.umich.edu } 1204004Sgblack@eecs.umich.edu } 1214004Sgblack@eecs.umich.edu //fbfcc 1224004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1234004Sgblack@eecs.umich.edu format BranchN { 1244004Sgblack@eecs.umich.edu //Branch Always 1255091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1265091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1275091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1285091Sgblack@eecs.umich.edu }}); 1294004Sgblack@eecs.umich.edu //Branch Never 1305091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1315091Sgblack@eecs.umich.edu annul_code={{ 1325091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1335091Sgblack@eecs.umich.edu NPC = NPC + 4; 1345091Sgblack@eecs.umich.edu }}); 1355091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1365091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1374004Sgblack@eecs.umich.edu } 1384004Sgblack@eecs.umich.edu } 1392469SN/A } 1402944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1413928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1423928Ssaidi@eecs.umich.edu R15 = (xc->readPC())<31:0>; 1433928Ssaidi@eecs.umich.edu else 1443928Ssaidi@eecs.umich.edu R15 = xc->readPC(); 1452516SN/A NNPC = R15 + disp; 1462469SN/A }}); 1472469SN/A 0x2: decode OP3 { 1482482SN/A format IntOp { 1492482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1502974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1512974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1522974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1532526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1542974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1552974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1562974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1572646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1582974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1592469SN/A 0x0A: umul({{ 1602516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1612646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1622482SN/A }}); 1632469SN/A 0x0B: smul({{ 1643931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1653900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1662482SN/A }}); 1672954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1682469SN/A 0x0D: udivx({{ 1692516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1702516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1712482SN/A }}); 1722469SN/A 0x0E: udiv({{ 1732516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1742482SN/A else 1752482SN/A { 1762646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1772482SN/A if(Rd.udw >> 32 != 0) 1782482SN/A Rd.udw = 0xFFFFFFFF; 1792482SN/A } 1802482SN/A }}); 1812482SN/A 0x0F: sdiv({{ 1822615SN/A if(Rs2_or_imm13.sdw == 0) 1832469SN/A fault = new DivisionByZero; 1842469SN/A else 1852482SN/A { 1862646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1873929Ssaidi@eecs.umich.edu if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 1882482SN/A Rd.udw = 0x7FFFFFFF; 1893929Ssaidi@eecs.umich.edu else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 1903929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 1912482SN/A } 1922526SN/A }}); 1932469SN/A } 1942482SN/A format IntOpCc { 1952469SN/A 0x10: addcc({{ 1962516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1972469SN/A Rd = resTemp = Rs1 + val2;}}, 1982580SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 1992469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2002580SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 2012469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2022526SN/A ); 2032482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2042482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2052482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2062469SN/A 0x14: subcc({{ 2072580SN/A int64_t val2 = Rs2_or_imm13; 2082580SN/A Rd = Rs1 - val2;}}, 2092580SN/A {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 2102580SN/A {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 2112580SN/A {{(~(Rs1<63:1> + (~val2)<63:1> + 2122580SN/A (Rs1 | ~val2)<0:>))<63:>}}, 2132580SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 2142526SN/A ); 2152482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2162482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2172482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2182469SN/A 0x18: addccc({{ 2192516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2202646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2212469SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 2222580SN/A {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 2232469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2243931Ssaidi@eecs.umich.edu {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 2252469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2262526SN/A ); 2273765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2282615SN/A uint64_t resTemp; 2292615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2303765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2313765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2322615SN/A int64_t resTemp; 2333931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2343765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2352469SN/A 0x1C: subccc({{ 2362516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2372646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2382954Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 2393931Ssaidi@eecs.umich.edu {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 2402469SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2413931Ssaidi@eecs.umich.edu {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 2422469SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2432526SN/A ); 2443765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2452615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2463765Sgblack@eecs.umich.edu else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2472469SN/A 0x1E: udivcc({{ 2482615SN/A uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2492989Ssaidi@eecs.umich.edu int32_t overflow = 0; 2502469SN/A if(val2 == 0) fault = new DivisionByZero; 2512469SN/A else 2522224SN/A { 2532646Ssaidi@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2542516SN/A overflow = (resTemp<63:32> != 0); 2552516SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 2562516SN/A else Rd = resTemp; 2572469SN/A } }}, 2582469SN/A {{0}}, 2592469SN/A {{overflow}}, 2602469SN/A {{0}}, 2612469SN/A {{0}} 2622526SN/A ); 2632469SN/A 0x1F: sdivcc({{ 2642996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2652996Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2662469SN/A if(val2 == 0) fault = new DivisionByZero; 2672469SN/A else 2682469SN/A { 2692996Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2703929Ssaidi@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2713929Ssaidi@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2722996Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 2733929Ssaidi@eecs.umich.edu else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 2742469SN/A } }}, 2752469SN/A {{0}}, 2762469SN/A {{overflow || underflow}}, 2772469SN/A {{0}}, 2782469SN/A {{0}} 2792526SN/A ); 2802469SN/A 0x20: taddcc({{ 2812516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2822469SN/A Rd = resTemp = Rs1 + val2; 2832469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2843753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 2852469SN/A {{overflow}}, 2862469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2872469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2882526SN/A ); 2892469SN/A 0x21: tsubcc({{ 2902516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2912469SN/A Rd = resTemp = Rs1 + val2; 2922469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2933753Sgblack@eecs.umich.edu {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 2942469SN/A {{overflow}}, 2952469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2962469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2972526SN/A ); 2982469SN/A 0x22: taddcctv({{ 2992996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13; 3002996Sgblack@eecs.umich.edu Rd = Rs1 + val2; 3012954Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || 3022954Sgblack@eecs.umich.edu (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 3032469SN/A if(overflow) fault = new TagOverflow;}}, 3043753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3052469SN/A {{overflow}}, 3062469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3072996Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 3082526SN/A ); 3092469SN/A 0x23: tsubcctv({{ 3102516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3112469SN/A Rd = resTemp = Rs1 + val2; 3122469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 3132469SN/A if(overflow) fault = new TagOverflow;}}, 3143753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3152469SN/A {{overflow}}, 3162469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3172469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3182526SN/A ); 3192469SN/A 0x24: mulscc({{ 3202469SN/A int32_t savedLSB = Rs1<0:>; 3214237Sgblack@eecs.umich.edu 3224237Sgblack@eecs.umich.edu //Step 1 3234237Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 3244237Sgblack@eecs.umich.edu //Step 2 3254237Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 3264237Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 3274237Sgblack@eecs.umich.edu //Step 3 3284237Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 3294237Sgblack@eecs.umich.edu Rd = partialP + added; 3304237Sgblack@eecs.umich.edu //Steps 4 & 5 3312646Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 3324237Sgblack@eecs.umich.edu {{((partialP<31:0> + added<31:0>)<32:0>)}}, 3334237Sgblack@eecs.umich.edu {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}}, 3344237Sgblack@eecs.umich.edu {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}}, 3354237Sgblack@eecs.umich.edu {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}} 3362526SN/A ); 3372526SN/A } 3382526SN/A format IntOp 3392526SN/A { 3402526SN/A 0x25: decode X { 3412526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3422526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3432469SN/A } 3442526SN/A 0x26: decode X { 3452526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3462526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3472526SN/A } 3482526SN/A 0x27: decode X { 3492526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3502526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3512526SN/A } 3522954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3533929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3543587Sgblack@eecs.umich.edu //1 should cause an illegal instruction exception 3553587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3563587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3573823Ssaidi@eecs.umich.edu 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3583587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3593587Sgblack@eecs.umich.edu if(Pstate<3:>) 3603587Sgblack@eecs.umich.edu Rd = (xc->readPC())<31:0>; 3613587Sgblack@eecs.umich.edu else 3623587Sgblack@eecs.umich.edu Rd = xc->readPC();}}); 3633587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3643587Sgblack@eecs.umich.edu //Wait for all fpops to finish. 3653587Sgblack@eecs.umich.edu Rd = Fprs; 3663587Sgblack@eecs.umich.edu }}); 3673587Sgblack@eecs.umich.edu //7-14 should cause an illegal instruction exception 3683587Sgblack@eecs.umich.edu 0x0F: decode I { 3694040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3704040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3712954Sgblack@eecs.umich.edu } 3723587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3733587Sgblack@eecs.umich.edu 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3743587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 3753587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3764010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3774010Ssaidi@eecs.umich.edu if (fault) 3784010Ssaidi@eecs.umich.edu return fault; 3794010Ssaidi@eecs.umich.edu Rd = Gsr; 3802954Sgblack@eecs.umich.edu }}); 3813587Sgblack@eecs.umich.edu //0x14-0x15 should cause an illegal instruction exception 3823587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3833823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3843823Ssaidi@eecs.umich.edu 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3853823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3863598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3873598Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 3883598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3893598Sgblack@eecs.umich.edu else 3903598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3913598Sgblack@eecs.umich.edu }}); 3923598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it reads the strand 3933598Sgblack@eecs.umich.edu //status register. 3943598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 3952954Sgblack@eecs.umich.edu } 3963587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3973587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3983587Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{ 3993587Sgblack@eecs.umich.edu if(Tl == 0) 4003587Sgblack@eecs.umich.edu return new IllegalInstruction; 4013587Sgblack@eecs.umich.edu Rd = Htstate; 4023587Sgblack@eecs.umich.edu }}); 4033587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 4043587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 4053587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 4063587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 4073587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 4083587Sgblack@eecs.umich.edu //0x07-0x1E should cause an illegal instruction exception 4093823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 4103587Sgblack@eecs.umich.edu } 4113587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 4123587Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{ 4133587Sgblack@eecs.umich.edu if(Tl == 0) 4143587Sgblack@eecs.umich.edu return new IllegalInstruction; 4153587Sgblack@eecs.umich.edu Rd = Tpc; 4163587Sgblack@eecs.umich.edu }}); 4173587Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{ 4183587Sgblack@eecs.umich.edu if(Tl == 0) 4193587Sgblack@eecs.umich.edu return new IllegalInstruction; 4203587Sgblack@eecs.umich.edu Rd = Tnpc; 4213587Sgblack@eecs.umich.edu }}); 4223587Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{ 4233587Sgblack@eecs.umich.edu if(Tl == 0) 4243587Sgblack@eecs.umich.edu return new IllegalInstruction; 4253587Sgblack@eecs.umich.edu Rd = Tstate; 4263587Sgblack@eecs.umich.edu }}); 4273587Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{ 4283587Sgblack@eecs.umich.edu if(Tl == 0) 4293587Sgblack@eecs.umich.edu return new IllegalInstruction; 4303587Sgblack@eecs.umich.edu Rd = Tt; 4313587Sgblack@eecs.umich.edu }}); 4323823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 4333587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 4343587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 4353587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 4363587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 4373587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 4383587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 4393587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 4403587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 4413587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 4423587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 4433587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 4443587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 4453587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 4463587Sgblack@eecs.umich.edu } 4472526SN/A 0x2B: BasicOperate::flushw({{ 4483911Ssaidi@eecs.umich.edu if(NWindows - 2 - Cansave != 0) 4492526SN/A { 4502526SN/A if(Otherwin) 4513909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 4522526SN/A else 4533909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 4542526SN/A } 4552526SN/A }}); 4562526SN/A 0x2C: decode MOVCC3 4572469SN/A { 4582526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 4592526SN/A 0x1: decode CC 4602526SN/A { 4612526SN/A 0x0: movcci({{ 4622646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 4632591SN/A Rd = Rs2_or_imm11; 4642591SN/A else 4652591SN/A Rd = Rd; 4662526SN/A }}); 4672526SN/A 0x2: movccx({{ 4682646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 4692591SN/A Rd = Rs2_or_imm11; 4702591SN/A else 4712591SN/A Rd = Rd; 4722526SN/A }}); 4732224SN/A } 4742526SN/A } 4752526SN/A 0x2D: sdivx({{ 4762615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 4772615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4782526SN/A }}); 4793941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4802526SN/A 0x2F: decode RCOND3 4812526SN/A { 4822615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4832615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4842615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4852615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4862615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4872615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4882526SN/A } 4893587Sgblack@eecs.umich.edu 0x30: decode RD { 4903929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4913587Sgblack@eecs.umich.edu //0x01 should cause an illegal instruction exception 4923587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4933826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 4943587Sgblack@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 4953587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4963587Sgblack@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 4973587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4983587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 4993587Sgblack@eecs.umich.edu 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 5003587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 5013587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 5023587Sgblack@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 5033587Sgblack@eecs.umich.edu return new FpDisabled; 5043587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 5053587Sgblack@eecs.umich.edu }}); 5063587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 5073587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 5083587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 5093823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5103587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 5113587Sgblack@eecs.umich.edu if(!Hpstate<2:>) 5123587Sgblack@eecs.umich.edu return new IllegalInstruction; 5133823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 5143587Sgblack@eecs.umich.edu }}); 5153823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5163598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 5173598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 5183598Sgblack@eecs.umich.edu }}); 5193598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it writes the strand 5203598Sgblack@eecs.umich.edu //status register. 5213598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 5223587Sgblack@eecs.umich.edu } 5232526SN/A 0x31: decode FCN { 5243417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 5253417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 5263417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 5273417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 5283417Sgblack@eecs.umich.edu if(Otherwin == 0) 5293417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 5303417Sgblack@eecs.umich.edu else 5313417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5323417Sgblack@eecs.umich.edu }}); 5333598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 5343417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 5353417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 5363417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 5373417Sgblack@eecs.umich.edu if(Otherwin == 0) 5383417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 5393417Sgblack@eecs.umich.edu else 5403417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5413928Ssaidi@eecs.umich.edu 5423928Ssaidi@eecs.umich.edu if(Cleanwin < NWindows - 1) 5433928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 5443417Sgblack@eecs.umich.edu }}); 5452526SN/A } 5463587Sgblack@eecs.umich.edu 0x32: decode RD { 5473587Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc({{ 5483587Sgblack@eecs.umich.edu if(Tl == 0) 5493587Sgblack@eecs.umich.edu return new IllegalInstruction; 5503587Sgblack@eecs.umich.edu else 5513587Sgblack@eecs.umich.edu Tpc = Rs1 ^ Rs2_or_imm13; 5523587Sgblack@eecs.umich.edu }}); 5533587Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc({{ 5543587Sgblack@eecs.umich.edu if(Tl == 0) 5553587Sgblack@eecs.umich.edu return new IllegalInstruction; 5563587Sgblack@eecs.umich.edu else 5573587Sgblack@eecs.umich.edu Tnpc = Rs1 ^ Rs2_or_imm13; 5583587Sgblack@eecs.umich.edu }}); 5593587Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate({{ 5603587Sgblack@eecs.umich.edu if(Tl == 0) 5613587Sgblack@eecs.umich.edu return new IllegalInstruction; 5623587Sgblack@eecs.umich.edu else 5633587Sgblack@eecs.umich.edu Tstate = Rs1 ^ Rs2_or_imm13; 5643587Sgblack@eecs.umich.edu }}); 5653587Sgblack@eecs.umich.edu 0x03: Priv::wrprtt({{ 5663587Sgblack@eecs.umich.edu if(Tl == 0) 5673587Sgblack@eecs.umich.edu return new IllegalInstruction; 5683587Sgblack@eecs.umich.edu else 5693587Sgblack@eecs.umich.edu Tt = Rs1 ^ Rs2_or_imm13; 5703587Sgblack@eecs.umich.edu }}); 5713823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 5723587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 5733587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 5743587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 5753587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5763587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5773587Sgblack@eecs.umich.edu else 5783587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5793587Sgblack@eecs.umich.edu }}); 5803587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5813587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5823587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5833587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5843587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5853587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5863587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5873587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 5883587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5893587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5903587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5913587Sgblack@eecs.umich.edu else 5923587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5933587Sgblack@eecs.umich.edu }}); 5943587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 5953587Sgblack@eecs.umich.edu } 5963587Sgblack@eecs.umich.edu 0x33: decode RD { 5973587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5983587Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate({{ 5993587Sgblack@eecs.umich.edu if(Tl == 0) 6003587Sgblack@eecs.umich.edu return new IllegalInstruction; 6013587Sgblack@eecs.umich.edu Htstate = Rs1 ^ Rs2_or_imm13; 6023587Sgblack@eecs.umich.edu }}); 6033587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 6043587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 6053587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 6063587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 6073587Sgblack@eecs.umich.edu //0x06-0x01D should cause an illegal instruction exception 6083823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 6093587Sgblack@eecs.umich.edu } 6102954Sgblack@eecs.umich.edu 0x34: decode OPF{ 6114008Ssaidi@eecs.umich.edu format FpBasic{ 6122963Sgblack@eecs.umich.edu 0x01: fmovs({{ 6133279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw; 6142963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6152963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6162963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6172963Sgblack@eecs.umich.edu }}); 6182963Sgblack@eecs.umich.edu 0x02: fmovd({{ 6193057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw; 6202963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6212963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6222963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6232963Sgblack@eecs.umich.edu }}); 6243995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 6252963Sgblack@eecs.umich.edu 0x05: fnegs({{ 6263279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw ^ (1UL << 31); 6272963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6282963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6292963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6302963Sgblack@eecs.umich.edu }}); 6312963Sgblack@eecs.umich.edu 0x06: fnegd({{ 6323057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw ^ (1ULL << 63); 6332963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6342963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6352963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6362963Sgblack@eecs.umich.edu }}); 6373995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 6382963Sgblack@eecs.umich.edu 0x09: fabss({{ 6393279Sgblack@eecs.umich.edu Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 6402963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6412963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6422963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6432963Sgblack@eecs.umich.edu }}); 6442963Sgblack@eecs.umich.edu 0x0A: fabsd({{ 6453057Sgblack@eecs.umich.edu Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 6462963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6472963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6482963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6492963Sgblack@eecs.umich.edu }}); 6503995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 6513918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 6523918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 6533995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 6543279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 6552963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 6563995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 6573279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 6584008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 6593995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 6603279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 6612963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 6623995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 6633279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 6642963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 6653995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 6663279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 6673995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 6682963Sgblack@eecs.umich.edu 0x81: fstox({{ 6694008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2s.sf); 6702963Sgblack@eecs.umich.edu }}); 6712963Sgblack@eecs.umich.edu 0x82: fdtox({{ 6724008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2.df); 6732963Sgblack@eecs.umich.edu }}); 6743995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 6752963Sgblack@eecs.umich.edu 0x84: fxtos({{ 6764008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2.sdw); 6772963Sgblack@eecs.umich.edu }}); 6782963Sgblack@eecs.umich.edu 0x88: fxtod({{ 6794008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2.sdw); 6802963Sgblack@eecs.umich.edu }}); 6813995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 6822963Sgblack@eecs.umich.edu 0xC4: fitos({{ 6834008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2s.sw); 6842963Sgblack@eecs.umich.edu }}); 6853279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 6863995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 6872963Sgblack@eecs.umich.edu 0xC8: fitod({{ 6884008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2s.sw); 6892963Sgblack@eecs.umich.edu }}); 6903279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 6913995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 6923995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 6933995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 6943995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6952963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6964008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6974008Ssaidi@eecs.umich.edu float t = Frds.sw; 6984008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6994008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 7002963Sgblack@eecs.umich.edu }}); 7012963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 7024008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 7034008Ssaidi@eecs.umich.edu double t = Frds.sw; 7044008Ssaidi@eecs.umich.edu if (t != Frs2.df) 7054008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 7062963Sgblack@eecs.umich.edu }}); 7073995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 7083941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 7092963Sgblack@eecs.umich.edu } 7102954Sgblack@eecs.umich.edu } 7113992Sgblack@eecs.umich.edu 0x35: decode OPF{ 7124008Ssaidi@eecs.umich.edu format FpBasic{ 7134204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 7144204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 7154204Sgblack@eecs.umich.edu Frds = Frs2s; 7164204Sgblack@eecs.umich.edu else 7174204Sgblack@eecs.umich.edu Frds = Frds; 7184204Sgblack@eecs.umich.edu }}); 7194204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 7204204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 7214204Sgblack@eecs.umich.edu Frd = Frs2; 7224204Sgblack@eecs.umich.edu else 7234204Sgblack@eecs.umich.edu Frd = Frd; 7244204Sgblack@eecs.umich.edu }}); 7254204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 7264204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 7274204Sgblack@eecs.umich.edu if(Rs1 == 0) 7284204Sgblack@eecs.umich.edu Frds = Frs2s; 7294204Sgblack@eecs.umich.edu else 7304204Sgblack@eecs.umich.edu Frds = Frds; 7314204Sgblack@eecs.umich.edu }}); 7324204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 7334204Sgblack@eecs.umich.edu if(Rs1 == 0) 7344204Sgblack@eecs.umich.edu Frd = Frs2; 7354204Sgblack@eecs.umich.edu else 7364204Sgblack@eecs.umich.edu Frd = Frd; 7374204Sgblack@eecs.umich.edu }}); 7384204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 7394204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 7404204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 7414204Sgblack@eecs.umich.edu Frds = Frs2s; 7424204Sgblack@eecs.umich.edu else 7434204Sgblack@eecs.umich.edu Frds = Frds; 7444204Sgblack@eecs.umich.edu }}); 7454204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 7464204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 7474204Sgblack@eecs.umich.edu Frd = Frs2; 7484204Sgblack@eecs.umich.edu else 7494204Sgblack@eecs.umich.edu Frd = Frd; 7504204Sgblack@eecs.umich.edu }}); 7514204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 7524204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 7534204Sgblack@eecs.umich.edu if(Rs1 <= 0) 7544204Sgblack@eecs.umich.edu Frds = Frs2s; 7554204Sgblack@eecs.umich.edu else 7564204Sgblack@eecs.umich.edu Frds = Frds; 7574204Sgblack@eecs.umich.edu }}); 7584204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 7594204Sgblack@eecs.umich.edu if(Rs1 <= 0) 7604204Sgblack@eecs.umich.edu Frd = Frs2; 7614204Sgblack@eecs.umich.edu else 7624204Sgblack@eecs.umich.edu Frd = Frd; 7634204Sgblack@eecs.umich.edu }}); 7644204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 7653992Sgblack@eecs.umich.edu 0x51: fcmps({{ 7663992Sgblack@eecs.umich.edu uint8_t fcc; 7673998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7683992Sgblack@eecs.umich.edu fcc = 3; 7693992Sgblack@eecs.umich.edu else if(Frs1s < Frs2s) 7703992Sgblack@eecs.umich.edu fcc = 1; 7713992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 7723992Sgblack@eecs.umich.edu fcc = 2; 7733992Sgblack@eecs.umich.edu else 7743992Sgblack@eecs.umich.edu fcc = 0; 7753992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7763992Sgblack@eecs.umich.edu if(FCMPCC) 7773992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7783992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7793992Sgblack@eecs.umich.edu }}); 7803992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 7813992Sgblack@eecs.umich.edu uint8_t fcc; 7824008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7833992Sgblack@eecs.umich.edu fcc = 3; 7844008Ssaidi@eecs.umich.edu else if(Frs1 < Frs2) 7853992Sgblack@eecs.umich.edu fcc = 1; 7864008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7873992Sgblack@eecs.umich.edu fcc = 2; 7883992Sgblack@eecs.umich.edu else 7893992Sgblack@eecs.umich.edu fcc = 0; 7903992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7913992Sgblack@eecs.umich.edu if(FCMPCC) 7923992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7933992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7943992Sgblack@eecs.umich.edu }}); 7953995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7963997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7973992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7983998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7993992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 8003992Sgblack@eecs.umich.edu if(Frs1s < Frs2s) 8013992Sgblack@eecs.umich.edu fcc = 1; 8023992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 8033992Sgblack@eecs.umich.edu fcc = 2; 8043992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 8053992Sgblack@eecs.umich.edu if(FCMPCC) 8063992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 8073992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 8083992Sgblack@eecs.umich.edu }}); 8093997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 8103992Sgblack@eecs.umich.edu uint8_t fcc = 0; 8114008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 8123992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 8134008Ssaidi@eecs.umich.edu if(Frs1 < Frs2) 8143992Sgblack@eecs.umich.edu fcc = 1; 8154008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 8163992Sgblack@eecs.umich.edu fcc = 2; 8173992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 8183992Sgblack@eecs.umich.edu if(FCMPCC) 8193992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 8203992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 8213992Sgblack@eecs.umich.edu }}); 8223997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 8234204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 8244204Sgblack@eecs.umich.edu if(Rs1 < 0) 8254204Sgblack@eecs.umich.edu Frds = Frs2s; 8264204Sgblack@eecs.umich.edu else 8274204Sgblack@eecs.umich.edu Frds = Frds; 8284204Sgblack@eecs.umich.edu }}); 8294204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 8304204Sgblack@eecs.umich.edu if(Rs1 < 0) 8314204Sgblack@eecs.umich.edu Frd = Frs2; 8324204Sgblack@eecs.umich.edu else 8334204Sgblack@eecs.umich.edu Frd = Frd; 8344204Sgblack@eecs.umich.edu }}); 8354204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 8364204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 8374204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 8384204Sgblack@eecs.umich.edu Frds = Frs2s; 8394204Sgblack@eecs.umich.edu else 8404204Sgblack@eecs.umich.edu Frds = Frds; 8414204Sgblack@eecs.umich.edu }}); 8424204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 8434204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 8444204Sgblack@eecs.umich.edu Frd = Frs2; 8454204Sgblack@eecs.umich.edu else 8464204Sgblack@eecs.umich.edu Frd = Frd; 8474204Sgblack@eecs.umich.edu }}); 8484204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 8494204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 8504204Sgblack@eecs.umich.edu if(Rs1 != 0) 8514204Sgblack@eecs.umich.edu Frds = Frs2s; 8524204Sgblack@eecs.umich.edu else 8534204Sgblack@eecs.umich.edu Frds = Frds; 8544204Sgblack@eecs.umich.edu }}); 8554204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 8564204Sgblack@eecs.umich.edu if(Rs1 != 0) 8574204Sgblack@eecs.umich.edu Frd = Frs2; 8584204Sgblack@eecs.umich.edu else 8594204Sgblack@eecs.umich.edu Frd = Frd; 8604204Sgblack@eecs.umich.edu }}); 8614204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 8624204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 8634204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 8644204Sgblack@eecs.umich.edu Frds = Frs2s; 8654204Sgblack@eecs.umich.edu else 8664204Sgblack@eecs.umich.edu Frds = Frds; 8674204Sgblack@eecs.umich.edu }}); 8684204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 8694204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 8704204Sgblack@eecs.umich.edu Frd = Frs2; 8714204Sgblack@eecs.umich.edu else 8724204Sgblack@eecs.umich.edu Frd = Frd; 8734204Sgblack@eecs.umich.edu }}); 8744204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 8754204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 8764204Sgblack@eecs.umich.edu if(Rs1 > 0) 8774204Sgblack@eecs.umich.edu Frds = Frs2s; 8784204Sgblack@eecs.umich.edu else 8794204Sgblack@eecs.umich.edu Frds = Frds; 8804204Sgblack@eecs.umich.edu }}); 8814204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 8824204Sgblack@eecs.umich.edu if(Rs1 > 0) 8834204Sgblack@eecs.umich.edu Frd = Frs2; 8844204Sgblack@eecs.umich.edu else 8854204Sgblack@eecs.umich.edu Frd = Frd; 8864204Sgblack@eecs.umich.edu }}); 8874204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 8884204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 8894204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8904204Sgblack@eecs.umich.edu Frds = Frs2s; 8914204Sgblack@eecs.umich.edu else 8924204Sgblack@eecs.umich.edu Frds = Frds; 8934204Sgblack@eecs.umich.edu }}); 8944204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8954204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8964204Sgblack@eecs.umich.edu Frd = Frs2; 8974204Sgblack@eecs.umich.edu else 8984204Sgblack@eecs.umich.edu Frd = Frd; 8994204Sgblack@eecs.umich.edu }}); 9004204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 9014204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 9024204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 9034204Sgblack@eecs.umich.edu Frds = Frs2s; 9044204Sgblack@eecs.umich.edu else 9054204Sgblack@eecs.umich.edu Frds = Frds; 9064204Sgblack@eecs.umich.edu }}); 9074204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 9084204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 9094204Sgblack@eecs.umich.edu Frd = Frs2; 9104204Sgblack@eecs.umich.edu else 9114204Sgblack@eecs.umich.edu Frd = Frd; 9124204Sgblack@eecs.umich.edu }}); 9134204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 9144204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 9154204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 9164204Sgblack@eecs.umich.edu Frds = Frs2s; 9174204Sgblack@eecs.umich.edu else 9184204Sgblack@eecs.umich.edu Frds = Frds; 9194204Sgblack@eecs.umich.edu }}); 9204204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 9214204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 9224204Sgblack@eecs.umich.edu Frd = Frs2; 9234204Sgblack@eecs.umich.edu else 9244204Sgblack@eecs.umich.edu Frd = Frd; 9254204Sgblack@eecs.umich.edu }}); 9264204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 9273992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 9283992Sgblack@eecs.umich.edu } 9293992Sgblack@eecs.umich.edu } 9302954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 9312954Sgblack@eecs.umich.edu //of instructions 9322954Sgblack@eecs.umich.edu 0x36: decode OPF{ 9333941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 9343941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 9353941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 9363941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 9373941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 9383941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 9393941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 9403941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 9413941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 9423941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 9433941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 9443941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 9453941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 9463941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 9473941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 9483042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 9492963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 9503042Sgblack@eecs.umich.edu Rd = sum & ~7; 9512963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 9522963Sgblack@eecs.umich.edu }}); 9533941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 9542963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 9552963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 9563042Sgblack@eecs.umich.edu Rd = sum & ~7; 9572963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 9582963Sgblack@eecs.umich.edu }}); 9593941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 9603941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 9613941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 9623941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 9633941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 9643941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 9653941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 9663941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 9673941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 9683941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 9693941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 9703941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 9713941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 9723941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 9733941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 9742954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 9752954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 9762954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 9772954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 9782963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 9793057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 9803057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 9813057Sgblack@eecs.umich.edu //Some special cases need to be split out, first 9823057Sgblack@eecs.umich.edu //because they're the most likely to be used, and 9833057Sgblack@eecs.umich.edu //second because otherwise, we end up shifting by 9843057Sgblack@eecs.umich.edu //greater than the width of the type being shifted, 9853057Sgblack@eecs.umich.edu //namely 64, which produces undefined results according 9863057Sgblack@eecs.umich.edu //to the C standard. 9873057Sgblack@eecs.umich.edu switch(Gsr<2:0>) 9883057Sgblack@eecs.umich.edu { 9893057Sgblack@eecs.umich.edu case 0: 9903057Sgblack@eecs.umich.edu Frd.udw = msbX; 9913057Sgblack@eecs.umich.edu break; 9923057Sgblack@eecs.umich.edu case 8: 9933057Sgblack@eecs.umich.edu Frd.udw = lsbX; 9943057Sgblack@eecs.umich.edu break; 9953057Sgblack@eecs.umich.edu default: 9963057Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9973057Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9983057Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9993057Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 10003057Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 10013057Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 10023057Sgblack@eecs.umich.edu } 10032963Sgblack@eecs.umich.edu }}); 10042954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 10053941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 10063941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 10073941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 10083941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 10093941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 10103941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 10113941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 10123941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 10133941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 10143941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 10154008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 10164008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 10173941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 10183941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 10193941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 10203941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 10214008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 10222963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 10232963Sgblack@eecs.umich.edu }}); 10244008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 10253279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 10262963Sgblack@eecs.umich.edu }}); 10273941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 10283941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 10294008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 10302963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 10312963Sgblack@eecs.umich.edu }}); 10324008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 10333279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 10342963Sgblack@eecs.umich.edu }}); 10353941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 10363941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 10373941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 10383941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 10393941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 10403941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 10413941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 10423941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 10434008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 10444008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 10453941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 10463941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 10474008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 10484008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 10493941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 10503941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 10513941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 10523941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 10534008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 10544008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 10552954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 10563941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 10572954Sgblack@eecs.umich.edu } 10584090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 10594090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 10604096Sgblack@eecs.umich.edu#if FULL_SYSTEM 10614113Sgblack@eecs.umich.edu format BasicOperate { 10624113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 10634113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 10644113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10654113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 10664113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 10674113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10684113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 10694113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 10704113Sgblack@eecs.umich.edu 0x54: m5panic({{ 10714113Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 10724113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 10734113Sgblack@eecs.umich.edu } 10744096Sgblack@eecs.umich.edu#endif 10754096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 10764090Ssaidi@eecs.umich.edu } 10772526SN/A 0x38: Branch::jmpl({{ 10782526SN/A Addr target = Rs1 + Rs2_or_imm13; 10792526SN/A if(target & 0x3) 10802526SN/A fault = new MemAddressNotAligned; 10812526SN/A else 10822526SN/A { 10833928Ssaidi@eecs.umich.edu if (Pstate<3:>) 10843929Ssaidi@eecs.umich.edu Rd = (xc->readPC())<31:0>; 10853928Ssaidi@eecs.umich.edu else 10863928Ssaidi@eecs.umich.edu Rd = xc->readPC(); 10872526SN/A NNPC = target; 10882526SN/A } 10892526SN/A }}); 10902526SN/A 0x39: Branch::return({{ 10912526SN/A Addr target = Rs1 + Rs2_or_imm13; 10922561SN/A if(fault == NoFault) 10932561SN/A { 10943765Sgblack@eecs.umich.edu //Check for fills which are higher priority than alignment 10953765Sgblack@eecs.umich.edu //faults. 10962561SN/A if(Canrestore == 0) 10972561SN/A { 10982561SN/A if(Otherwin) 10993909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 11002561SN/A else 11013909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 11022561SN/A } 11033765Sgblack@eecs.umich.edu //Check for alignment faults 11043765Sgblack@eecs.umich.edu else if(target & 0x3) 11053765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 11062561SN/A else 11072561SN/A { 11083765Sgblack@eecs.umich.edu NNPC = target; 11093417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 11102561SN/A Cansave = Cansave + 1; 11112561SN/A Canrestore = Canrestore - 1; 11122561SN/A } 11132561SN/A } 11142526SN/A }}); 11152526SN/A 0x3A: decode CC 11162526SN/A { 11172526SN/A 0x0: Trap::tcci({{ 11182646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 11192561SN/A { 11202561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 11212561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 11223531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 11232561SN/A } 11244828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 11252526SN/A 0x2: Trap::tccx({{ 11262646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 11272561SN/A { 11282561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 11292561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 11303531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 11312526SN/A } 11324828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 11332526SN/A } 11344090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 11354090Ssaidi@eecs.umich.edu MemWriteOp); 11362526SN/A 0x3C: save({{ 11372526SN/A if(Cansave == 0) 11382526SN/A { 11392526SN/A if(Otherwin) 11403909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 11412526SN/A else 11423909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 11432526SN/A } 11442526SN/A else if(Cleanwin - Canrestore == 0) 11452526SN/A { 11462526SN/A fault = new CleanWindow; 11472526SN/A } 11482526SN/A else 11492526SN/A { 11502526SN/A Cwp = (Cwp + 1) % NWindows; 11513765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 11522561SN/A Cansave = Cansave - 1; 11532561SN/A Canrestore = Canrestore + 1; 11542526SN/A } 11552526SN/A }}); 11562526SN/A 0x3D: restore({{ 11572526SN/A if(Canrestore == 0) 11582526SN/A { 11592526SN/A if(Otherwin) 11603909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 11612526SN/A else 11623909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 11632526SN/A } 11642526SN/A else 11652526SN/A { 11663417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 11673765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 11682561SN/A Cansave = Cansave + 1; 11692561SN/A Canrestore = Canrestore - 1; 11702526SN/A } 11712526SN/A }}); 11722526SN/A 0x3E: decode FCN { 11732526SN/A 0x0: Priv::done({{ 11742526SN/A if(Tl == 0) 11752526SN/A return new IllegalInstruction; 11762646Ssaidi@eecs.umich.edu 11772646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11782646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11792646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11802646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11812646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11823825Ssaidi@eecs.umich.edu Hpstate = Htstate; 11832646Ssaidi@eecs.umich.edu NPC = Tnpc; 11842646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 11852526SN/A Tl = Tl - 1; 11862526SN/A }}); 11872938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 11882526SN/A if(Tl == 0) 11892526SN/A return new IllegalInstruction; 11902646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11912646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11922646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11932646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11942646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11953826Ssaidi@eecs.umich.edu Hpstate = Htstate; 11962646Ssaidi@eecs.umich.edu NPC = Tpc; 11973417Sgblack@eecs.umich.edu NNPC = Tnpc; 11982526SN/A Tl = Tl - 1; 11992526SN/A }}); 12002526SN/A } 12012526SN/A } 12022469SN/A } 12032469SN/A 0x3: decode OP3 { 12042526SN/A format Load { 12053272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 12063272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 12073272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 12083835Sgblack@eecs.umich.edu 0x03: ldtw({{ 12094115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12104115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 12113272Sgblack@eecs.umich.edu }}); 12122526SN/A } 12132526SN/A format Store { 12143272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 12153272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 12163272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 12174224Sgblack@eecs.umich.edu 0x07: sttw({{ 12184256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 12194256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 12204256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 12214256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 12224256Sgblack@eecs.umich.edu Twin32_t temp; 12234256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12244256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12254256Sgblack@eecs.umich.edu Mem.tuw = temp; 12264224Sgblack@eecs.umich.edu }}); 12272526SN/A } 12282526SN/A format Load { 12293272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 12303272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 12313272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 12323272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 12332526SN/A } 12344040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 12354040Ssaidi@eecs.umich.edu {{ 12364040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12374040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12384040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 12393272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 12404040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 12414040Ssaidi@eecs.umich.edu {{ 12424040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12434040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12444040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 12453810Sgblack@eecs.umich.edu format LoadAlt { 12463810Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 12473810Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 12483810Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 12493856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 12503926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUP 12513926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 12524040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12534040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12543926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUS 12553926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 12564040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12574040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12583856Ssaidi@eecs.umich.edu //ASI_QUAD_LDD 12593856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 12604040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12614040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12623856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL 12633856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 12644040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12654040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12664040Ssaidi@eecs.umich.edu //ASI_LDTX_N 12674040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 12684040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12694040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12704040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUP_L 12714040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 12724040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12734040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12744040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUS_L 12754040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 12764040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12774040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12784040Ssaidi@eecs.umich.edu //ASI_LDTX_L 12794040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 12804040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12814040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12823856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL_L 12833856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 12844040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12854040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12863856Ssaidi@eecs.umich.edu //ASI_LDTX_N_L 12873856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 12884040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12894040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12903901Ssaidi@eecs.umich.edu //ASI_LDTX_P 12913901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 12924040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12934040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12943926Ssaidi@eecs.umich.edu //ASI_LDTX_S 12953926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 12964040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12974040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12984040Ssaidi@eecs.umich.edu //ASI_LDTX_PL 12994040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 13004040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13014040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13024040Ssaidi@eecs.umich.edu //ASI_LDTX_SL 13034040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 13044040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13054040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13063856Ssaidi@eecs.umich.edu default: ldtwa({{ 13074115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 13084115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 13093856Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}); 13103856Ssaidi@eecs.umich.edu } 13112526SN/A } 13123810Sgblack@eecs.umich.edu format StoreAlt { 13133810Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 13143810Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 13153810Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 13164224Sgblack@eecs.umich.edu 0x17: sttwa({{ 13174256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 13184256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 13194256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 13204256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 13214256Sgblack@eecs.umich.edu Twin32_t temp; 13224256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 13234256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 13244256Sgblack@eecs.umich.edu Mem.tuw = temp; 13254224Sgblack@eecs.umich.edu }}, {{EXT_ASI}}); 13262526SN/A } 13273810Sgblack@eecs.umich.edu format LoadAlt { 13283810Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 13293810Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 13303810Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 13313810Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 13322526SN/A } 13334040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 13344040Ssaidi@eecs.umich.edu {{ 13354040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 13364040Ssaidi@eecs.umich.edu Rd.ub = tmp; 13374040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 13383810Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 13394040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 13404040Ssaidi@eecs.umich.edu {{ 13414040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 13424040Ssaidi@eecs.umich.edu Rd.uw = tmp; 13434040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 13444040Ssaidi@eecs.umich.edu 13452526SN/A format Trap { 13463931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 13474008Ssaidi@eecs.umich.edu 0x21: decode RD { 13484011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 13494011Ssaidi@eecs.umich.edu if (fault) 13504011Ssaidi@eecs.umich.edu return fault; 13514011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 13524011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 13534011Ssaidi@eecs.umich.edu if (fault) 13544011Ssaidi@eecs.umich.edu return fault; 13554011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 13564008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 13572469SN/A } 13582526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 13593272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 13603931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 13614008Ssaidi@eecs.umich.edu 0x25: decode RD { 13624011Ssaidi@eecs.umich.edu 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 13634011Ssaidi@eecs.umich.edu if (fault) 13644011Ssaidi@eecs.umich.edu return fault; 13654011Ssaidi@eecs.umich.edu Mem.uw = Fsr<31:0>; 13664008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 13674011Ssaidi@eecs.umich.edu 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 13684011Ssaidi@eecs.umich.edu if (fault) 13694011Ssaidi@eecs.umich.edu return fault; 13704011Ssaidi@eecs.umich.edu Mem.udw = Fsr; 13714011Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 13724008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 13732526SN/A } 13742526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 13753272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 13762526SN/A 0x2D: Nop::prefetch({{ }}); 13773931Ssaidi@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 13782526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 13793272Sgblack@eecs.umich.edu format LoadAlt { 13803272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 13813272Sgblack@eecs.umich.edu //ASI_NUCLEUS 13823272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 13833272Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 13843272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 13853272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 13863272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 13873272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 13883272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 13893272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 13903272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 13913272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 13923272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 13933272Sgblack@eecs.umich.edu //ASI_REAL 13943272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 13953272Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 13963272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 13973272Sgblack@eecs.umich.edu //ASI_REAL_IO 13983272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 13993272Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 14003272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 14013272Sgblack@eecs.umich.edu //ASI_PRIMARY 14023272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 14033272Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 14043272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 14053272Sgblack@eecs.umich.edu //ASI_SECONDARY 14063272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 14073272Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 14083272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 14093272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 14103272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 14113272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 14123272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 14133272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 14143272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 14153272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 14163272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 14173272Sgblack@eecs.umich.edu 14183272Sgblack@eecs.umich.edu format BlockLoad { 14193272Sgblack@eecs.umich.edu // LDBLOCKF 14203272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 14213272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 14223272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 14233272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 14243272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14253272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 14263272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14273272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 14283272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 14293810Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 14303272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 14313272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 14323272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 14333272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 14343272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 14353272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 14363272Sgblack@eecs.umich.edu } 14373272Sgblack@eecs.umich.edu 14383272Sgblack@eecs.umich.edu //LDSHORTF 14393272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 14403272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 14413272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 14423272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 14433272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 14443272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 14453272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 14463272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 14473272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 14483272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 14493272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 14503272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 14513272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 14523272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 14533272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 14543272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 14553272Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 14563378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 14573378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14583272Sgblack@eecs.umich.edu } 14593272Sgblack@eecs.umich.edu } 14603931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 14612954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 14623378Sgblack@eecs.umich.edu format StoreAlt { 14633378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 14643378Sgblack@eecs.umich.edu //ASI_NUCLEUS 14653378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 14663378Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 14673378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 14683378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 14693378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 14703378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 14713378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 14723378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 14733378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 14743378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 14753378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 14763378Sgblack@eecs.umich.edu //ASI_REAL 14773378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 14783378Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 14793378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 14803378Sgblack@eecs.umich.edu //ASI_REAL_IO 14813378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 14823378Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 14833378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 14843378Sgblack@eecs.umich.edu //ASI_PRIMARY 14853378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 14863378Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 14873378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 14883378Sgblack@eecs.umich.edu //ASI_SECONDARY 14893378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 14903378Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 14913378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 14923378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 14933378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 14943378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 14953378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 14963378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 14973378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 14983378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 14993378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 15003378Sgblack@eecs.umich.edu 15013378Sgblack@eecs.umich.edu format BlockStore { 15023378Sgblack@eecs.umich.edu // STBLOCKF 15033378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 15043378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 15053378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 15063378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 15073378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 15083378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 15093378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 15103378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 15113378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 15123810Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 15133378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 15143378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 15153378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 15163378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 15173378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 15183378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 15193378Sgblack@eecs.umich.edu } 15203378Sgblack@eecs.umich.edu 15213378Sgblack@eecs.umich.edu //STSHORTF 15223378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 15233378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 15243378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 15253378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 15263378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 15273378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 15283378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 15293378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 15303378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 15313378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 15323378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 15333378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 15343378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 15353378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 15363378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 15373378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 15383378Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 15393378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 15403378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 15413378Sgblack@eecs.umich.edu } 15423378Sgblack@eecs.umich.edu } 15434040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 15444040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 15454040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 15464040Ssaidi@eecs.umich.edu {{ 15474040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 15484040Ssaidi@eecs.umich.edu Rd.uw = tmp; 15494040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP_COND); 15502526SN/A 0x3D: Nop::prefetcha({{ }}); 15514040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 15524040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 15534040Ssaidi@eecs.umich.edu {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 15542526SN/A } 15552469SN/A } 15562022SN/A} 1557