decoder.isa revision 4828
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443598Sgblack@eecs.umich.edu //bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 473056Sgblack@eecs.umich.edu //Branch Always 483056Sgblack@eecs.umich.edu 0x8: decode A 493056Sgblack@eecs.umich.edu { 503598Sgblack@eecs.umich.edu 0x0: bpa(19, {{ 512516SN/A NNPC = xc->readPC() + disp; 523056Sgblack@eecs.umich.edu }}); 533598Sgblack@eecs.umich.edu 0x1: bpa(19, {{ 543056Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 553056Sgblack@eecs.umich.edu NNPC = NPC + 4; 563056Sgblack@eecs.umich.edu }}, ',a'); 573056Sgblack@eecs.umich.edu } 583056Sgblack@eecs.umich.edu //Branch Never 593056Sgblack@eecs.umich.edu 0x0: decode A 603056Sgblack@eecs.umich.edu { 613598Sgblack@eecs.umich.edu 0x0: bpn(19, {{ 623056Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 633056Sgblack@eecs.umich.edu }}); 643598Sgblack@eecs.umich.edu 0x1: bpn(19, {{ 654004Sgblack@eecs.umich.edu NNPC = NPC + 8; 664004Sgblack@eecs.umich.edu NPC = NPC + 4; 673056Sgblack@eecs.umich.edu }}, ',a'); 683056Sgblack@eecs.umich.edu } 693056Sgblack@eecs.umich.edu default: decode BPCC 703056Sgblack@eecs.umich.edu { 713056Sgblack@eecs.umich.edu 0x0: bpcci(19, {{ 723056Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 733056Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 743056Sgblack@eecs.umich.edu else 753056Sgblack@eecs.umich.edu handle_annul 763056Sgblack@eecs.umich.edu }}); 773056Sgblack@eecs.umich.edu 0x2: bpccx(19, {{ 783056Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 793056Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 803056Sgblack@eecs.umich.edu else 813056Sgblack@eecs.umich.edu handle_annul 823056Sgblack@eecs.umich.edu }}); 833056Sgblack@eecs.umich.edu } 842482SN/A } 853598Sgblack@eecs.umich.edu //bicc 863598Sgblack@eecs.umich.edu 0x2: decode COND2 873598Sgblack@eecs.umich.edu { 883598Sgblack@eecs.umich.edu //Branch Always 893598Sgblack@eecs.umich.edu 0x8: decode A 903598Sgblack@eecs.umich.edu { 913598Sgblack@eecs.umich.edu 0x0: ba(22, {{ 923598Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 933598Sgblack@eecs.umich.edu }}); 943598Sgblack@eecs.umich.edu 0x1: ba(22, {{ 953598Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 963598Sgblack@eecs.umich.edu NNPC = NPC + 4; 973598Sgblack@eecs.umich.edu }}, ',a'); 983598Sgblack@eecs.umich.edu } 993598Sgblack@eecs.umich.edu //Branch Never 1003598Sgblack@eecs.umich.edu 0x0: decode A 1013598Sgblack@eecs.umich.edu { 1023598Sgblack@eecs.umich.edu 0x0: bn(22, {{ 1033598Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 1043598Sgblack@eecs.umich.edu }}); 1053598Sgblack@eecs.umich.edu 0x1: bn(22, {{ 1064004Sgblack@eecs.umich.edu NNPC = NPC + 8; 1074004Sgblack@eecs.umich.edu NPC = NPC + 4; 1083598Sgblack@eecs.umich.edu }}, ',a'); 1093598Sgblack@eecs.umich.edu } 1103598Sgblack@eecs.umich.edu default: bicc(22, {{ 1113598Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 1123598Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1133598Sgblack@eecs.umich.edu else 1143598Sgblack@eecs.umich.edu handle_annul 1153598Sgblack@eecs.umich.edu }}); 1163598Sgblack@eecs.umich.edu } 1172516SN/A } 1182516SN/A 0x3: decode RCOND2 1192516SN/A { 1202516SN/A format BranchSplit 1212482SN/A { 1222482SN/A 0x1: bpreq({{ 1232591SN/A if(Rs1.sdw == 0) 1242516SN/A NNPC = xc->readPC() + disp; 1252580SN/A else 1262580SN/A handle_annul 1272482SN/A }}); 1282482SN/A 0x2: bprle({{ 1292591SN/A if(Rs1.sdw <= 0) 1302516SN/A NNPC = xc->readPC() + disp; 1312580SN/A else 1322580SN/A handle_annul 1332482SN/A }}); 1342482SN/A 0x3: bprl({{ 1352591SN/A if(Rs1.sdw < 0) 1362516SN/A NNPC = xc->readPC() + disp; 1372580SN/A else 1382580SN/A handle_annul 1392482SN/A }}); 1402482SN/A 0x5: bprne({{ 1412591SN/A if(Rs1.sdw != 0) 1422516SN/A NNPC = xc->readPC() + disp; 1432580SN/A else 1442580SN/A handle_annul 1452482SN/A }}); 1462482SN/A 0x6: bprg({{ 1472591SN/A if(Rs1.sdw > 0) 1482516SN/A NNPC = xc->readPC() + disp; 1492580SN/A else 1502580SN/A handle_annul 1512482SN/A }}); 1522482SN/A 0x7: bprge({{ 1532591SN/A if(Rs1.sdw >= 0) 1542516SN/A NNPC = xc->readPC() + disp; 1552580SN/A else 1562580SN/A handle_annul 1572482SN/A }}); 1582469SN/A } 1592482SN/A } 1602516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 1613042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1624004Sgblack@eecs.umich.edu //fbpfcc 1634004Sgblack@eecs.umich.edu 0x5: decode COND2 { 1644004Sgblack@eecs.umich.edu format BranchN { 1654004Sgblack@eecs.umich.edu //Branch Always 1664004Sgblack@eecs.umich.edu 0x8: decode A 1674004Sgblack@eecs.umich.edu { 1684004Sgblack@eecs.umich.edu 0x0: fbpa(22, {{ 1694004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1704004Sgblack@eecs.umich.edu }}); 1714004Sgblack@eecs.umich.edu 0x1: fbpa(22, {{ 1724004Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1734004Sgblack@eecs.umich.edu NNPC = NPC + 4; 1744004Sgblack@eecs.umich.edu }}, ',a'); 1754004Sgblack@eecs.umich.edu } 1764004Sgblack@eecs.umich.edu //Branch Never 1774004Sgblack@eecs.umich.edu 0x0: decode A 1784004Sgblack@eecs.umich.edu { 1794004Sgblack@eecs.umich.edu 0x0: fbpn(22, {{ 1804004Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 1814004Sgblack@eecs.umich.edu }}); 1824004Sgblack@eecs.umich.edu 0x1: fbpn(22, {{ 1834004Sgblack@eecs.umich.edu NNPC = NPC + 8; 1844004Sgblack@eecs.umich.edu NPC = NPC + 4; 1854004Sgblack@eecs.umich.edu }}, ',a'); 1864004Sgblack@eecs.umich.edu } 1874004Sgblack@eecs.umich.edu default: decode BPCC { 1884235Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, {{ 1894004Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND2)) 1904004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1914004Sgblack@eecs.umich.edu else 1924004Sgblack@eecs.umich.edu handle_annul 1934004Sgblack@eecs.umich.edu }}); 1944235Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, {{ 1954004Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND2)) 1964004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1974004Sgblack@eecs.umich.edu else 1984004Sgblack@eecs.umich.edu handle_annul 1994004Sgblack@eecs.umich.edu }}); 2004235Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, {{ 2014004Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND2)) 2024004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 2034004Sgblack@eecs.umich.edu else 2044004Sgblack@eecs.umich.edu handle_annul 2054004Sgblack@eecs.umich.edu }}); 2064235Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, {{ 2074004Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND2)) 2084004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 2094004Sgblack@eecs.umich.edu else 2104004Sgblack@eecs.umich.edu handle_annul 2114004Sgblack@eecs.umich.edu }}); 2124004Sgblack@eecs.umich.edu } 2134004Sgblack@eecs.umich.edu } 2144004Sgblack@eecs.umich.edu } 2154004Sgblack@eecs.umich.edu //fbfcc 2164004Sgblack@eecs.umich.edu 0x6: decode COND2 { 2174004Sgblack@eecs.umich.edu format BranchN { 2184004Sgblack@eecs.umich.edu //Branch Always 2194004Sgblack@eecs.umich.edu 0x8: decode A 2204004Sgblack@eecs.umich.edu { 2214004Sgblack@eecs.umich.edu 0x0: fba(22, {{ 2224004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 2234004Sgblack@eecs.umich.edu }}); 2244004Sgblack@eecs.umich.edu 0x1: fba(22, {{ 2254004Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 2264004Sgblack@eecs.umich.edu NNPC = NPC + 4; 2274004Sgblack@eecs.umich.edu }}, ',a'); 2284004Sgblack@eecs.umich.edu } 2294004Sgblack@eecs.umich.edu //Branch Never 2304004Sgblack@eecs.umich.edu 0x0: decode A 2314004Sgblack@eecs.umich.edu { 2324004Sgblack@eecs.umich.edu 0x0: fbn(22, {{ 2334004Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 2344004Sgblack@eecs.umich.edu }}); 2354004Sgblack@eecs.umich.edu 0x1: fbn(22, {{ 2364004Sgblack@eecs.umich.edu NNPC = NPC + 8; 2374004Sgblack@eecs.umich.edu NPC = NPC + 4; 2384004Sgblack@eecs.umich.edu }}, ',a'); 2394004Sgblack@eecs.umich.edu } 2404004Sgblack@eecs.umich.edu default: fbfcc(22, {{ 2414004Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND2)) 2424004Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 2434004Sgblack@eecs.umich.edu else 2444004Sgblack@eecs.umich.edu handle_annul 2454004Sgblack@eecs.umich.edu }}); 2464004Sgblack@eecs.umich.edu } 2474004Sgblack@eecs.umich.edu } 2482469SN/A } 2492944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 2503928Ssaidi@eecs.umich.edu if (Pstate<3:>) 2513928Ssaidi@eecs.umich.edu R15 = (xc->readPC())<31:0>; 2523928Ssaidi@eecs.umich.edu else 2533928Ssaidi@eecs.umich.edu R15 = xc->readPC(); 2542516SN/A NNPC = R15 + disp; 2552469SN/A }}); 2562469SN/A 0x2: decode OP3 { 2572482SN/A format IntOp { 2582482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 2592974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 2602974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 2612974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 2622526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 2632974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 2642974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 2652974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 2662646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 2672974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 2682469SN/A 0x0A: umul({{ 2692516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 2702646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 2712482SN/A }}); 2722469SN/A 0x0B: smul({{ 2733931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2743900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 2752482SN/A }}); 2762954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 2772469SN/A 0x0D: udivx({{ 2782516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 2792516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 2802482SN/A }}); 2812469SN/A 0x0E: udiv({{ 2822516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 2832482SN/A else 2842482SN/A { 2852646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 2862482SN/A if(Rd.udw >> 32 != 0) 2872482SN/A Rd.udw = 0xFFFFFFFF; 2882482SN/A } 2892482SN/A }}); 2902482SN/A 0x0F: sdiv({{ 2912615SN/A if(Rs2_or_imm13.sdw == 0) 2922469SN/A fault = new DivisionByZero; 2932469SN/A else 2942482SN/A { 2952646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 2963929Ssaidi@eecs.umich.edu if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 2972482SN/A Rd.udw = 0x7FFFFFFF; 2983929Ssaidi@eecs.umich.edu else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 2993929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 3002482SN/A } 3012526SN/A }}); 3022469SN/A } 3032482SN/A format IntOpCc { 3042469SN/A 0x10: addcc({{ 3052516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3062469SN/A Rd = resTemp = Rs1 + val2;}}, 3072580SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 3082469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 3092580SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 3102469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3112526SN/A ); 3122482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 3132482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 3142482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 3152469SN/A 0x14: subcc({{ 3162580SN/A int64_t val2 = Rs2_or_imm13; 3172580SN/A Rd = Rs1 - val2;}}, 3182580SN/A {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 3192580SN/A {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 3202580SN/A {{(~(Rs1<63:1> + (~val2)<63:1> + 3212580SN/A (Rs1 | ~val2)<0:>))<63:>}}, 3222580SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 3232526SN/A ); 3242482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 3252482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 3262482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 3272469SN/A 0x18: addccc({{ 3282516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3292646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 3302469SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 3312580SN/A {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 3322469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 3333931Ssaidi@eecs.umich.edu {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 3342469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3352526SN/A ); 3363765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 3372615SN/A uint64_t resTemp; 3382615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 3393765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 3403765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 3412615SN/A int64_t resTemp; 3423931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 3433765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 3442469SN/A 0x1C: subccc({{ 3452516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3462646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 3472954Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 3483931Ssaidi@eecs.umich.edu {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 3492469SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 3503931Ssaidi@eecs.umich.edu {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 3512469SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 3522526SN/A ); 3533765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 3542615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 3553765Sgblack@eecs.umich.edu else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 3562469SN/A 0x1E: udivcc({{ 3572615SN/A uint32_t resTemp, val2 = Rs2_or_imm13.udw; 3582989Ssaidi@eecs.umich.edu int32_t overflow = 0; 3592469SN/A if(val2 == 0) fault = new DivisionByZero; 3602469SN/A else 3612224SN/A { 3622646Ssaidi@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 3632516SN/A overflow = (resTemp<63:32> != 0); 3642516SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 3652516SN/A else Rd = resTemp; 3662469SN/A } }}, 3672469SN/A {{0}}, 3682469SN/A {{overflow}}, 3692469SN/A {{0}}, 3702469SN/A {{0}} 3712526SN/A ); 3722469SN/A 0x1F: sdivcc({{ 3732996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 3742996Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 3752469SN/A if(val2 == 0) fault = new DivisionByZero; 3762469SN/A else 3772469SN/A { 3782996Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 3793929Ssaidi@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 3803929Ssaidi@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 3812996Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 3823929Ssaidi@eecs.umich.edu else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 3832469SN/A } }}, 3842469SN/A {{0}}, 3852469SN/A {{overflow || underflow}}, 3862469SN/A {{0}}, 3872469SN/A {{0}} 3882526SN/A ); 3892469SN/A 0x20: taddcc({{ 3902516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3912469SN/A Rd = resTemp = Rs1 + val2; 3922469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 3933753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3942469SN/A {{overflow}}, 3952469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3962469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3972526SN/A ); 3982469SN/A 0x21: tsubcc({{ 3992516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 4002469SN/A Rd = resTemp = Rs1 + val2; 4012469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 4023753Sgblack@eecs.umich.edu {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 4032469SN/A {{overflow}}, 4042469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 4052469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 4062526SN/A ); 4072469SN/A 0x22: taddcctv({{ 4082996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13; 4092996Sgblack@eecs.umich.edu Rd = Rs1 + val2; 4102954Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || 4112954Sgblack@eecs.umich.edu (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 4122469SN/A if(overflow) fault = new TagOverflow;}}, 4133753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 4142469SN/A {{overflow}}, 4152469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 4162996Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 4172526SN/A ); 4182469SN/A 0x23: tsubcctv({{ 4192516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 4202469SN/A Rd = resTemp = Rs1 + val2; 4212469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 4222469SN/A if(overflow) fault = new TagOverflow;}}, 4233753Sgblack@eecs.umich.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 4242469SN/A {{overflow}}, 4252469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 4262469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 4272526SN/A ); 4282469SN/A 0x24: mulscc({{ 4292469SN/A int32_t savedLSB = Rs1<0:>; 4304237Sgblack@eecs.umich.edu 4314237Sgblack@eecs.umich.edu //Step 1 4324237Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 4334237Sgblack@eecs.umich.edu //Step 2 4344237Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 4354237Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 4364237Sgblack@eecs.umich.edu //Step 3 4374237Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 4384237Sgblack@eecs.umich.edu Rd = partialP + added; 4394237Sgblack@eecs.umich.edu //Steps 4 & 5 4402646Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 4414237Sgblack@eecs.umich.edu {{((partialP<31:0> + added<31:0>)<32:0>)}}, 4424237Sgblack@eecs.umich.edu {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}}, 4434237Sgblack@eecs.umich.edu {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}}, 4444237Sgblack@eecs.umich.edu {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}} 4452526SN/A ); 4462526SN/A } 4472526SN/A format IntOp 4482526SN/A { 4492526SN/A 0x25: decode X { 4502526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 4512526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 4522469SN/A } 4532526SN/A 0x26: decode X { 4542526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 4552526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 4562526SN/A } 4572526SN/A 0x27: decode X { 4582526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 4592526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 4602526SN/A } 4612954Sgblack@eecs.umich.edu 0x28: decode RS1 { 4623929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 4633587Sgblack@eecs.umich.edu //1 should cause an illegal instruction exception 4643587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 4653587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 4663823Ssaidi@eecs.umich.edu 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 4673587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 4683587Sgblack@eecs.umich.edu if(Pstate<3:>) 4693587Sgblack@eecs.umich.edu Rd = (xc->readPC())<31:0>; 4703587Sgblack@eecs.umich.edu else 4713587Sgblack@eecs.umich.edu Rd = xc->readPC();}}); 4723587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 4733587Sgblack@eecs.umich.edu //Wait for all fpops to finish. 4743587Sgblack@eecs.umich.edu Rd = Fprs; 4753587Sgblack@eecs.umich.edu }}); 4763587Sgblack@eecs.umich.edu //7-14 should cause an illegal instruction exception 4773587Sgblack@eecs.umich.edu 0x0F: decode I { 4784040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 4794040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 4802954Sgblack@eecs.umich.edu } 4813587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 4823587Sgblack@eecs.umich.edu 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 4833587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 4843587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 4854010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 4864010Ssaidi@eecs.umich.edu if (fault) 4874010Ssaidi@eecs.umich.edu return fault; 4884010Ssaidi@eecs.umich.edu Rd = Gsr; 4892954Sgblack@eecs.umich.edu }}); 4903587Sgblack@eecs.umich.edu //0x14-0x15 should cause an illegal instruction exception 4913587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 4923823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 4933823Ssaidi@eecs.umich.edu 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 4943823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 4953598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 4963598Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 4973598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 4983598Sgblack@eecs.umich.edu else 4993598Sgblack@eecs.umich.edu Rd = StrandStsReg; 5003598Sgblack@eecs.umich.edu }}); 5013598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it reads the strand 5023598Sgblack@eecs.umich.edu //status register. 5033598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 5042954Sgblack@eecs.umich.edu } 5053587Sgblack@eecs.umich.edu 0x29: decode RS1 { 5063587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 5073587Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{ 5083587Sgblack@eecs.umich.edu if(Tl == 0) 5093587Sgblack@eecs.umich.edu return new IllegalInstruction; 5103587Sgblack@eecs.umich.edu Rd = Htstate; 5113587Sgblack@eecs.umich.edu }}); 5123587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 5133587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 5143587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 5153587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 5163587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 5173587Sgblack@eecs.umich.edu //0x07-0x1E should cause an illegal instruction exception 5183823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 5193587Sgblack@eecs.umich.edu } 5203587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 5213587Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{ 5223587Sgblack@eecs.umich.edu if(Tl == 0) 5233587Sgblack@eecs.umich.edu return new IllegalInstruction; 5243587Sgblack@eecs.umich.edu Rd = Tpc; 5253587Sgblack@eecs.umich.edu }}); 5263587Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{ 5273587Sgblack@eecs.umich.edu if(Tl == 0) 5283587Sgblack@eecs.umich.edu return new IllegalInstruction; 5293587Sgblack@eecs.umich.edu Rd = Tnpc; 5303587Sgblack@eecs.umich.edu }}); 5313587Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{ 5323587Sgblack@eecs.umich.edu if(Tl == 0) 5333587Sgblack@eecs.umich.edu return new IllegalInstruction; 5343587Sgblack@eecs.umich.edu Rd = Tstate; 5353587Sgblack@eecs.umich.edu }}); 5363587Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{ 5373587Sgblack@eecs.umich.edu if(Tl == 0) 5383587Sgblack@eecs.umich.edu return new IllegalInstruction; 5393587Sgblack@eecs.umich.edu Rd = Tt; 5403587Sgblack@eecs.umich.edu }}); 5413823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 5423587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 5433587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 5443587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 5453587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 5463587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 5473587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 5483587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 5493587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 5503587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 5513587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 5523587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 5533587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 5543587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 5553587Sgblack@eecs.umich.edu } 5562526SN/A 0x2B: BasicOperate::flushw({{ 5573911Ssaidi@eecs.umich.edu if(NWindows - 2 - Cansave != 0) 5582526SN/A { 5592526SN/A if(Otherwin) 5603909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 5612526SN/A else 5623909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 5632526SN/A } 5642526SN/A }}); 5652526SN/A 0x2C: decode MOVCC3 5662469SN/A { 5672526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 5682526SN/A 0x1: decode CC 5692526SN/A { 5702526SN/A 0x0: movcci({{ 5712646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 5722591SN/A Rd = Rs2_or_imm11; 5732591SN/A else 5742591SN/A Rd = Rd; 5752526SN/A }}); 5762526SN/A 0x2: movccx({{ 5772646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 5782591SN/A Rd = Rs2_or_imm11; 5792591SN/A else 5802591SN/A Rd = Rd; 5812526SN/A }}); 5822224SN/A } 5832526SN/A } 5842526SN/A 0x2D: sdivx({{ 5852615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 5862615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 5872526SN/A }}); 5883941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 5892526SN/A 0x2F: decode RCOND3 5902526SN/A { 5912615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 5922615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 5932615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 5942615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 5952615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 5962615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 5972526SN/A } 5983587Sgblack@eecs.umich.edu 0x30: decode RD { 5993929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 6003587Sgblack@eecs.umich.edu //0x01 should cause an illegal instruction exception 6013587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 6023826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 6033587Sgblack@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 6043587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 6053587Sgblack@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 6063587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 6073587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 6083587Sgblack@eecs.umich.edu 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 6093587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 6103587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 6113587Sgblack@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 6123587Sgblack@eecs.umich.edu return new FpDisabled; 6133587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 6143587Sgblack@eecs.umich.edu }}); 6153587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 6163587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 6173587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 6183823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 6193587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 6203587Sgblack@eecs.umich.edu if(!Hpstate<2:>) 6213587Sgblack@eecs.umich.edu return new IllegalInstruction; 6223823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 6233587Sgblack@eecs.umich.edu }}); 6243823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 6253598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 6263598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 6273598Sgblack@eecs.umich.edu }}); 6283598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it writes the strand 6293598Sgblack@eecs.umich.edu //status register. 6303598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 6313587Sgblack@eecs.umich.edu } 6322526SN/A 0x31: decode FCN { 6333417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 6343417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 6353417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 6363417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 6373417Sgblack@eecs.umich.edu if(Otherwin == 0) 6383417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 6393417Sgblack@eecs.umich.edu else 6403417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 6413417Sgblack@eecs.umich.edu }}); 6423598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 6433417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 6443417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 6453417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 6463417Sgblack@eecs.umich.edu if(Otherwin == 0) 6473417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 6483417Sgblack@eecs.umich.edu else 6493417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 6503928Ssaidi@eecs.umich.edu 6513928Ssaidi@eecs.umich.edu if(Cleanwin < NWindows - 1) 6523928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 6533417Sgblack@eecs.umich.edu }}); 6542526SN/A } 6553587Sgblack@eecs.umich.edu 0x32: decode RD { 6563587Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc({{ 6573587Sgblack@eecs.umich.edu if(Tl == 0) 6583587Sgblack@eecs.umich.edu return new IllegalInstruction; 6593587Sgblack@eecs.umich.edu else 6603587Sgblack@eecs.umich.edu Tpc = Rs1 ^ Rs2_or_imm13; 6613587Sgblack@eecs.umich.edu }}); 6623587Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc({{ 6633587Sgblack@eecs.umich.edu if(Tl == 0) 6643587Sgblack@eecs.umich.edu return new IllegalInstruction; 6653587Sgblack@eecs.umich.edu else 6663587Sgblack@eecs.umich.edu Tnpc = Rs1 ^ Rs2_or_imm13; 6673587Sgblack@eecs.umich.edu }}); 6683587Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate({{ 6693587Sgblack@eecs.umich.edu if(Tl == 0) 6703587Sgblack@eecs.umich.edu return new IllegalInstruction; 6713587Sgblack@eecs.umich.edu else 6723587Sgblack@eecs.umich.edu Tstate = Rs1 ^ Rs2_or_imm13; 6733587Sgblack@eecs.umich.edu }}); 6743587Sgblack@eecs.umich.edu 0x03: Priv::wrprtt({{ 6753587Sgblack@eecs.umich.edu if(Tl == 0) 6763587Sgblack@eecs.umich.edu return new IllegalInstruction; 6773587Sgblack@eecs.umich.edu else 6783587Sgblack@eecs.umich.edu Tt = Rs1 ^ Rs2_or_imm13; 6793587Sgblack@eecs.umich.edu }}); 6803823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 6813587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 6823587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 6833587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 6843587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 6853587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 6863587Sgblack@eecs.umich.edu else 6873587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 6883587Sgblack@eecs.umich.edu }}); 6893587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 6903587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 6913587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 6923587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 6933587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 6943587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 6953587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 6963587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 6973587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 6983587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 6993587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 7003587Sgblack@eecs.umich.edu else 7013587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 7023587Sgblack@eecs.umich.edu }}); 7033587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 7043587Sgblack@eecs.umich.edu } 7053587Sgblack@eecs.umich.edu 0x33: decode RD { 7063587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 7073587Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate({{ 7083587Sgblack@eecs.umich.edu if(Tl == 0) 7093587Sgblack@eecs.umich.edu return new IllegalInstruction; 7103587Sgblack@eecs.umich.edu Htstate = Rs1 ^ Rs2_or_imm13; 7113587Sgblack@eecs.umich.edu }}); 7123587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 7133587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 7143587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 7153587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 7163587Sgblack@eecs.umich.edu //0x06-0x01D should cause an illegal instruction exception 7173823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 7183587Sgblack@eecs.umich.edu } 7192954Sgblack@eecs.umich.edu 0x34: decode OPF{ 7204008Ssaidi@eecs.umich.edu format FpBasic{ 7212963Sgblack@eecs.umich.edu 0x01: fmovs({{ 7223279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw; 7232963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7242963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7252963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7262963Sgblack@eecs.umich.edu }}); 7272963Sgblack@eecs.umich.edu 0x02: fmovd({{ 7283057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw; 7292963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7302963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7312963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7322963Sgblack@eecs.umich.edu }}); 7333995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 7342963Sgblack@eecs.umich.edu 0x05: fnegs({{ 7353279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw ^ (1UL << 31); 7362963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7372963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7382963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7392963Sgblack@eecs.umich.edu }}); 7402963Sgblack@eecs.umich.edu 0x06: fnegd({{ 7413057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw ^ (1ULL << 63); 7422963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7432963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7442963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7452963Sgblack@eecs.umich.edu }}); 7463995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 7472963Sgblack@eecs.umich.edu 0x09: fabss({{ 7483279Sgblack@eecs.umich.edu Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 7492963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7502963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7512963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7522963Sgblack@eecs.umich.edu }}); 7532963Sgblack@eecs.umich.edu 0x0A: fabsd({{ 7543057Sgblack@eecs.umich.edu Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 7552963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 7562963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 7572963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 7582963Sgblack@eecs.umich.edu }}); 7593995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 7603918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 7613918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 7623995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 7633279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 7642963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 7653995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 7663279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 7674008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 7683995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 7693279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 7702963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 7713995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 7723279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 7732963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 7743995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 7753279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 7763995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 7772963Sgblack@eecs.umich.edu 0x81: fstox({{ 7784008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2s.sf); 7792963Sgblack@eecs.umich.edu }}); 7802963Sgblack@eecs.umich.edu 0x82: fdtox({{ 7814008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2.df); 7822963Sgblack@eecs.umich.edu }}); 7833995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 7842963Sgblack@eecs.umich.edu 0x84: fxtos({{ 7854008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2.sdw); 7862963Sgblack@eecs.umich.edu }}); 7872963Sgblack@eecs.umich.edu 0x88: fxtod({{ 7884008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2.sdw); 7892963Sgblack@eecs.umich.edu }}); 7903995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 7912963Sgblack@eecs.umich.edu 0xC4: fitos({{ 7924008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2s.sw); 7932963Sgblack@eecs.umich.edu }}); 7943279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 7953995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 7962963Sgblack@eecs.umich.edu 0xC8: fitod({{ 7974008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2s.sw); 7982963Sgblack@eecs.umich.edu }}); 7993279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 8003995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 8013995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 8023995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 8033995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 8042963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 8054008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 8064008Ssaidi@eecs.umich.edu float t = Frds.sw; 8074008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 8084008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 8092963Sgblack@eecs.umich.edu }}); 8102963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 8114008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 8124008Ssaidi@eecs.umich.edu double t = Frds.sw; 8134008Ssaidi@eecs.umich.edu if (t != Frs2.df) 8144008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 8152963Sgblack@eecs.umich.edu }}); 8163995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 8173941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 8182963Sgblack@eecs.umich.edu } 8192954Sgblack@eecs.umich.edu } 8203992Sgblack@eecs.umich.edu 0x35: decode OPF{ 8214008Ssaidi@eecs.umich.edu format FpBasic{ 8224204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 8234204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 8244204Sgblack@eecs.umich.edu Frds = Frs2s; 8254204Sgblack@eecs.umich.edu else 8264204Sgblack@eecs.umich.edu Frds = Frds; 8274204Sgblack@eecs.umich.edu }}); 8284204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 8294204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 8304204Sgblack@eecs.umich.edu Frd = Frs2; 8314204Sgblack@eecs.umich.edu else 8324204Sgblack@eecs.umich.edu Frd = Frd; 8334204Sgblack@eecs.umich.edu }}); 8344204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 8354204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 8364204Sgblack@eecs.umich.edu if(Rs1 == 0) 8374204Sgblack@eecs.umich.edu Frds = Frs2s; 8384204Sgblack@eecs.umich.edu else 8394204Sgblack@eecs.umich.edu Frds = Frds; 8404204Sgblack@eecs.umich.edu }}); 8414204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 8424204Sgblack@eecs.umich.edu if(Rs1 == 0) 8434204Sgblack@eecs.umich.edu Frd = Frs2; 8444204Sgblack@eecs.umich.edu else 8454204Sgblack@eecs.umich.edu Frd = Frd; 8464204Sgblack@eecs.umich.edu }}); 8474204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 8484204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 8494204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 8504204Sgblack@eecs.umich.edu Frds = Frs2s; 8514204Sgblack@eecs.umich.edu else 8524204Sgblack@eecs.umich.edu Frds = Frds; 8534204Sgblack@eecs.umich.edu }}); 8544204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 8554204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 8564204Sgblack@eecs.umich.edu Frd = Frs2; 8574204Sgblack@eecs.umich.edu else 8584204Sgblack@eecs.umich.edu Frd = Frd; 8594204Sgblack@eecs.umich.edu }}); 8604204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 8614204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 8624204Sgblack@eecs.umich.edu if(Rs1 <= 0) 8634204Sgblack@eecs.umich.edu Frds = Frs2s; 8644204Sgblack@eecs.umich.edu else 8654204Sgblack@eecs.umich.edu Frds = Frds; 8664204Sgblack@eecs.umich.edu }}); 8674204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 8684204Sgblack@eecs.umich.edu if(Rs1 <= 0) 8694204Sgblack@eecs.umich.edu Frd = Frs2; 8704204Sgblack@eecs.umich.edu else 8714204Sgblack@eecs.umich.edu Frd = Frd; 8724204Sgblack@eecs.umich.edu }}); 8734204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 8743992Sgblack@eecs.umich.edu 0x51: fcmps({{ 8753992Sgblack@eecs.umich.edu uint8_t fcc; 8763998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 8773992Sgblack@eecs.umich.edu fcc = 3; 8783992Sgblack@eecs.umich.edu else if(Frs1s < Frs2s) 8793992Sgblack@eecs.umich.edu fcc = 1; 8803992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 8813992Sgblack@eecs.umich.edu fcc = 2; 8823992Sgblack@eecs.umich.edu else 8833992Sgblack@eecs.umich.edu fcc = 0; 8843992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 8853992Sgblack@eecs.umich.edu if(FCMPCC) 8863992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 8873992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 8883992Sgblack@eecs.umich.edu }}); 8893992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 8903992Sgblack@eecs.umich.edu uint8_t fcc; 8914008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 8923992Sgblack@eecs.umich.edu fcc = 3; 8934008Ssaidi@eecs.umich.edu else if(Frs1 < Frs2) 8943992Sgblack@eecs.umich.edu fcc = 1; 8954008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 8963992Sgblack@eecs.umich.edu fcc = 2; 8973992Sgblack@eecs.umich.edu else 8983992Sgblack@eecs.umich.edu fcc = 0; 8993992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 9003992Sgblack@eecs.umich.edu if(FCMPCC) 9013992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 9023992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 9033992Sgblack@eecs.umich.edu }}); 9043995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 9053997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 9063992Sgblack@eecs.umich.edu uint8_t fcc = 0; 9073998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 9083992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 9093992Sgblack@eecs.umich.edu if(Frs1s < Frs2s) 9103992Sgblack@eecs.umich.edu fcc = 1; 9113992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 9123992Sgblack@eecs.umich.edu fcc = 2; 9133992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 9143992Sgblack@eecs.umich.edu if(FCMPCC) 9153992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 9163992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 9173992Sgblack@eecs.umich.edu }}); 9183997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 9193992Sgblack@eecs.umich.edu uint8_t fcc = 0; 9204008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 9213992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 9224008Ssaidi@eecs.umich.edu if(Frs1 < Frs2) 9233992Sgblack@eecs.umich.edu fcc = 1; 9244008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 9253992Sgblack@eecs.umich.edu fcc = 2; 9263992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 9273992Sgblack@eecs.umich.edu if(FCMPCC) 9283992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 9293992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 9303992Sgblack@eecs.umich.edu }}); 9313997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 9324204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 9334204Sgblack@eecs.umich.edu if(Rs1 < 0) 9344204Sgblack@eecs.umich.edu Frds = Frs2s; 9354204Sgblack@eecs.umich.edu else 9364204Sgblack@eecs.umich.edu Frds = Frds; 9374204Sgblack@eecs.umich.edu }}); 9384204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 9394204Sgblack@eecs.umich.edu if(Rs1 < 0) 9404204Sgblack@eecs.umich.edu Frd = Frs2; 9414204Sgblack@eecs.umich.edu else 9424204Sgblack@eecs.umich.edu Frd = Frd; 9434204Sgblack@eecs.umich.edu }}); 9444204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 9454204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 9464204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 9474204Sgblack@eecs.umich.edu Frds = Frs2s; 9484204Sgblack@eecs.umich.edu else 9494204Sgblack@eecs.umich.edu Frds = Frds; 9504204Sgblack@eecs.umich.edu }}); 9514204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 9524204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 9534204Sgblack@eecs.umich.edu Frd = Frs2; 9544204Sgblack@eecs.umich.edu else 9554204Sgblack@eecs.umich.edu Frd = Frd; 9564204Sgblack@eecs.umich.edu }}); 9574204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 9584204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 9594204Sgblack@eecs.umich.edu if(Rs1 != 0) 9604204Sgblack@eecs.umich.edu Frds = Frs2s; 9614204Sgblack@eecs.umich.edu else 9624204Sgblack@eecs.umich.edu Frds = Frds; 9634204Sgblack@eecs.umich.edu }}); 9644204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 9654204Sgblack@eecs.umich.edu if(Rs1 != 0) 9664204Sgblack@eecs.umich.edu Frd = Frs2; 9674204Sgblack@eecs.umich.edu else 9684204Sgblack@eecs.umich.edu Frd = Frd; 9694204Sgblack@eecs.umich.edu }}); 9704204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 9714204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 9724204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 9734204Sgblack@eecs.umich.edu Frds = Frs2s; 9744204Sgblack@eecs.umich.edu else 9754204Sgblack@eecs.umich.edu Frds = Frds; 9764204Sgblack@eecs.umich.edu }}); 9774204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 9784204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 9794204Sgblack@eecs.umich.edu Frd = Frs2; 9804204Sgblack@eecs.umich.edu else 9814204Sgblack@eecs.umich.edu Frd = Frd; 9824204Sgblack@eecs.umich.edu }}); 9834204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 9844204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 9854204Sgblack@eecs.umich.edu if(Rs1 > 0) 9864204Sgblack@eecs.umich.edu Frds = Frs2s; 9874204Sgblack@eecs.umich.edu else 9884204Sgblack@eecs.umich.edu Frds = Frds; 9894204Sgblack@eecs.umich.edu }}); 9904204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 9914204Sgblack@eecs.umich.edu if(Rs1 > 0) 9924204Sgblack@eecs.umich.edu Frd = Frs2; 9934204Sgblack@eecs.umich.edu else 9944204Sgblack@eecs.umich.edu Frd = Frd; 9954204Sgblack@eecs.umich.edu }}); 9964204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 9974204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 9984204Sgblack@eecs.umich.edu if(Rs1 >= 0) 9994204Sgblack@eecs.umich.edu Frds = Frs2s; 10004204Sgblack@eecs.umich.edu else 10014204Sgblack@eecs.umich.edu Frds = Frds; 10024204Sgblack@eecs.umich.edu }}); 10034204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 10044204Sgblack@eecs.umich.edu if(Rs1 >= 0) 10054204Sgblack@eecs.umich.edu Frd = Frs2; 10064204Sgblack@eecs.umich.edu else 10074204Sgblack@eecs.umich.edu Frd = Frd; 10084204Sgblack@eecs.umich.edu }}); 10094204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 10104204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 10114204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 10124204Sgblack@eecs.umich.edu Frds = Frs2s; 10134204Sgblack@eecs.umich.edu else 10144204Sgblack@eecs.umich.edu Frds = Frds; 10154204Sgblack@eecs.umich.edu }}); 10164204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 10174204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 10184204Sgblack@eecs.umich.edu Frd = Frs2; 10194204Sgblack@eecs.umich.edu else 10204204Sgblack@eecs.umich.edu Frd = Frd; 10214204Sgblack@eecs.umich.edu }}); 10224204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 10234204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 10244204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 10254204Sgblack@eecs.umich.edu Frds = Frs2s; 10264204Sgblack@eecs.umich.edu else 10274204Sgblack@eecs.umich.edu Frds = Frds; 10284204Sgblack@eecs.umich.edu }}); 10294204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 10304204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 10314204Sgblack@eecs.umich.edu Frd = Frs2; 10324204Sgblack@eecs.umich.edu else 10334204Sgblack@eecs.umich.edu Frd = Frd; 10344204Sgblack@eecs.umich.edu }}); 10354204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 10363992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 10373992Sgblack@eecs.umich.edu } 10383992Sgblack@eecs.umich.edu } 10392954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 10402954Sgblack@eecs.umich.edu //of instructions 10412954Sgblack@eecs.umich.edu 0x36: decode OPF{ 10423941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 10433941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 10443941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 10453941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 10463941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 10473941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 10483941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 10493941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 10503941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 10513941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 10523941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 10533941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 10543941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 10553941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 10563941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 10573042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 10582963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 10593042Sgblack@eecs.umich.edu Rd = sum & ~7; 10602963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 10612963Sgblack@eecs.umich.edu }}); 10623941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 10632963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 10642963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 10653042Sgblack@eecs.umich.edu Rd = sum & ~7; 10662963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 10672963Sgblack@eecs.umich.edu }}); 10683941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 10693941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 10703941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 10713941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 10723941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 10733941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 10743941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 10753941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 10763941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 10773941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 10783941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 10793941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 10803941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 10813941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 10823941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 10832954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 10842954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 10852954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 10862954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 10872963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 10883057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 10893057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 10903057Sgblack@eecs.umich.edu //Some special cases need to be split out, first 10913057Sgblack@eecs.umich.edu //because they're the most likely to be used, and 10923057Sgblack@eecs.umich.edu //second because otherwise, we end up shifting by 10933057Sgblack@eecs.umich.edu //greater than the width of the type being shifted, 10943057Sgblack@eecs.umich.edu //namely 64, which produces undefined results according 10953057Sgblack@eecs.umich.edu //to the C standard. 10963057Sgblack@eecs.umich.edu switch(Gsr<2:0>) 10973057Sgblack@eecs.umich.edu { 10983057Sgblack@eecs.umich.edu case 0: 10993057Sgblack@eecs.umich.edu Frd.udw = msbX; 11003057Sgblack@eecs.umich.edu break; 11013057Sgblack@eecs.umich.edu case 8: 11023057Sgblack@eecs.umich.edu Frd.udw = lsbX; 11033057Sgblack@eecs.umich.edu break; 11043057Sgblack@eecs.umich.edu default: 11053057Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 11063057Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 11073057Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 11083057Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 11093057Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 11103057Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 11113057Sgblack@eecs.umich.edu } 11122963Sgblack@eecs.umich.edu }}); 11132954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 11143941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 11153941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 11163941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 11173941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 11183941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 11193941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 11203941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 11213941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 11223941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 11233941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 11244008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 11254008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 11263941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 11273941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 11283941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 11293941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 11304008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 11312963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 11322963Sgblack@eecs.umich.edu }}); 11334008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 11343279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 11352963Sgblack@eecs.umich.edu }}); 11363941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 11373941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 11384008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 11392963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 11402963Sgblack@eecs.umich.edu }}); 11414008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 11423279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 11432963Sgblack@eecs.umich.edu }}); 11443941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 11453941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 11463941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 11473941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 11483941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 11493941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 11503941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 11513941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 11524008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 11534008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 11543941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 11553941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 11564008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 11574008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 11583941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 11593941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 11603941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 11613941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 11624008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 11634008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 11642954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 11653941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 11662954Sgblack@eecs.umich.edu } 11674090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 11684090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 11694096Sgblack@eecs.umich.edu#if FULL_SYSTEM 11704113Sgblack@eecs.umich.edu format BasicOperate { 11714113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 11724113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 11734113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 11744113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 11754113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 11764113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 11774113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 11784113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 11794113Sgblack@eecs.umich.edu 0x54: m5panic({{ 11804113Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 11814113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 11824113Sgblack@eecs.umich.edu } 11834096Sgblack@eecs.umich.edu#endif 11844096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 11854090Ssaidi@eecs.umich.edu } 11862526SN/A 0x38: Branch::jmpl({{ 11872526SN/A Addr target = Rs1 + Rs2_or_imm13; 11882526SN/A if(target & 0x3) 11892526SN/A fault = new MemAddressNotAligned; 11902526SN/A else 11912526SN/A { 11923928Ssaidi@eecs.umich.edu if (Pstate<3:>) 11933929Ssaidi@eecs.umich.edu Rd = (xc->readPC())<31:0>; 11943928Ssaidi@eecs.umich.edu else 11953928Ssaidi@eecs.umich.edu Rd = xc->readPC(); 11962526SN/A NNPC = target; 11972526SN/A } 11982526SN/A }}); 11992526SN/A 0x39: Branch::return({{ 12002526SN/A Addr target = Rs1 + Rs2_or_imm13; 12012561SN/A if(fault == NoFault) 12022561SN/A { 12033765Sgblack@eecs.umich.edu //Check for fills which are higher priority than alignment 12043765Sgblack@eecs.umich.edu //faults. 12052561SN/A if(Canrestore == 0) 12062561SN/A { 12072561SN/A if(Otherwin) 12083909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 12092561SN/A else 12103909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 12112561SN/A } 12123765Sgblack@eecs.umich.edu //Check for alignment faults 12133765Sgblack@eecs.umich.edu else if(target & 0x3) 12143765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 12152561SN/A else 12162561SN/A { 12173765Sgblack@eecs.umich.edu NNPC = target; 12183417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 12192561SN/A Cansave = Cansave + 1; 12202561SN/A Canrestore = Canrestore - 1; 12212561SN/A } 12222561SN/A } 12232526SN/A }}); 12242526SN/A 0x3A: decode CC 12252526SN/A { 12262526SN/A 0x0: Trap::tcci({{ 12272646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 12282561SN/A { 12292561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 12302561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 12313531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 12322561SN/A } 12334828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 12342526SN/A 0x2: Trap::tccx({{ 12352646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 12362561SN/A { 12372561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 12382561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 12393531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 12402526SN/A } 12414828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 12422526SN/A } 12434090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 12444090Ssaidi@eecs.umich.edu MemWriteOp); 12452526SN/A 0x3C: save({{ 12462526SN/A if(Cansave == 0) 12472526SN/A { 12482526SN/A if(Otherwin) 12493909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 12502526SN/A else 12513909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 12522526SN/A } 12532526SN/A else if(Cleanwin - Canrestore == 0) 12542526SN/A { 12552526SN/A fault = new CleanWindow; 12562526SN/A } 12572526SN/A else 12582526SN/A { 12592526SN/A Cwp = (Cwp + 1) % NWindows; 12603765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 12612561SN/A Cansave = Cansave - 1; 12622561SN/A Canrestore = Canrestore + 1; 12632526SN/A } 12642526SN/A }}); 12652526SN/A 0x3D: restore({{ 12662526SN/A if(Canrestore == 0) 12672526SN/A { 12682526SN/A if(Otherwin) 12693909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 12702526SN/A else 12713909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 12722526SN/A } 12732526SN/A else 12742526SN/A { 12753417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 12763765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 12772561SN/A Cansave = Cansave + 1; 12782561SN/A Canrestore = Canrestore - 1; 12792526SN/A } 12802526SN/A }}); 12812526SN/A 0x3E: decode FCN { 12822526SN/A 0x0: Priv::done({{ 12832526SN/A if(Tl == 0) 12842526SN/A return new IllegalInstruction; 12852646Ssaidi@eecs.umich.edu 12862646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 12872646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 12882646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 12892646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 12902646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 12913825Ssaidi@eecs.umich.edu Hpstate = Htstate; 12922646Ssaidi@eecs.umich.edu NPC = Tnpc; 12932646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 12942526SN/A Tl = Tl - 1; 12952526SN/A }}); 12962938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 12972526SN/A if(Tl == 0) 12982526SN/A return new IllegalInstruction; 12992646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 13002646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 13012646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 13022646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 13032646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 13043826Ssaidi@eecs.umich.edu Hpstate = Htstate; 13052646Ssaidi@eecs.umich.edu NPC = Tpc; 13063417Sgblack@eecs.umich.edu NNPC = Tnpc; 13072526SN/A Tl = Tl - 1; 13082526SN/A }}); 13092526SN/A } 13102526SN/A } 13112469SN/A } 13122469SN/A 0x3: decode OP3 { 13132526SN/A format Load { 13143272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 13153272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 13163272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 13173835Sgblack@eecs.umich.edu 0x03: ldtw({{ 13184115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 13194115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 13203272Sgblack@eecs.umich.edu }}); 13212526SN/A } 13222526SN/A format Store { 13233272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 13243272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 13253272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 13264224Sgblack@eecs.umich.edu 0x07: sttw({{ 13274256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 13284256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 13294256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 13304256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 13314256Sgblack@eecs.umich.edu Twin32_t temp; 13324256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 13334256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 13344256Sgblack@eecs.umich.edu Mem.tuw = temp; 13354224Sgblack@eecs.umich.edu }}); 13362526SN/A } 13372526SN/A format Load { 13383272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 13393272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 13403272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 13413272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 13422526SN/A } 13434040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 13444040Ssaidi@eecs.umich.edu {{ 13454040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 13464040Ssaidi@eecs.umich.edu Rd.ub = tmp; 13474040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 13483272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 13494040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 13504040Ssaidi@eecs.umich.edu {{ 13514040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 13524040Ssaidi@eecs.umich.edu Rd.uw = tmp; 13534040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 13543810Sgblack@eecs.umich.edu format LoadAlt { 13553810Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 13563810Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 13573810Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 13583856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 13593926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUP 13603926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 13614040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13624040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13633926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUS 13643926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 13654040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13664040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13673856Ssaidi@eecs.umich.edu //ASI_QUAD_LDD 13683856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 13694040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13704040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13713856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL 13723856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 13734040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13744040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13754040Ssaidi@eecs.umich.edu //ASI_LDTX_N 13764040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 13774040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13784040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13794040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUP_L 13804040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 13814040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13824040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13834040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUS_L 13844040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 13854040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13864040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13874040Ssaidi@eecs.umich.edu //ASI_LDTX_L 13884040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 13894040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13904040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13913856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL_L 13923856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 13934040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13944040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13953856Ssaidi@eecs.umich.edu //ASI_LDTX_N_L 13963856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 13974040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 13984040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 13993901Ssaidi@eecs.umich.edu //ASI_LDTX_P 14003901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 14014040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 14024040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 14033926Ssaidi@eecs.umich.edu //ASI_LDTX_S 14043926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 14054040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 14064040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 14074040Ssaidi@eecs.umich.edu //ASI_LDTX_PL 14084040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 14094040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 14104040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 14114040Ssaidi@eecs.umich.edu //ASI_LDTX_SL 14124040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 14134040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 14144040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 14153856Ssaidi@eecs.umich.edu default: ldtwa({{ 14164115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 14174115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 14183856Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}); 14193856Ssaidi@eecs.umich.edu } 14202526SN/A } 14213810Sgblack@eecs.umich.edu format StoreAlt { 14223810Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 14233810Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 14243810Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 14254224Sgblack@eecs.umich.edu 0x17: sttwa({{ 14264256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 14274256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 14284256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 14294256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 14304256Sgblack@eecs.umich.edu Twin32_t temp; 14314256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 14324256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 14334256Sgblack@eecs.umich.edu Mem.tuw = temp; 14344224Sgblack@eecs.umich.edu }}, {{EXT_ASI}}); 14352526SN/A } 14363810Sgblack@eecs.umich.edu format LoadAlt { 14373810Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 14383810Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 14393810Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 14403810Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 14412526SN/A } 14424040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 14434040Ssaidi@eecs.umich.edu {{ 14444040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 14454040Ssaidi@eecs.umich.edu Rd.ub = tmp; 14464040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 14473810Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 14484040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 14494040Ssaidi@eecs.umich.edu {{ 14504040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 14514040Ssaidi@eecs.umich.edu Rd.uw = tmp; 14524040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 14534040Ssaidi@eecs.umich.edu 14542526SN/A format Trap { 14553931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 14564008Ssaidi@eecs.umich.edu 0x21: decode RD { 14574011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 14584011Ssaidi@eecs.umich.edu if (fault) 14594011Ssaidi@eecs.umich.edu return fault; 14604011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 14614011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 14624011Ssaidi@eecs.umich.edu if (fault) 14634011Ssaidi@eecs.umich.edu return fault; 14644011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 14654008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 14662469SN/A } 14672526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 14683272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 14693931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 14704008Ssaidi@eecs.umich.edu 0x25: decode RD { 14714011Ssaidi@eecs.umich.edu 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 14724011Ssaidi@eecs.umich.edu if (fault) 14734011Ssaidi@eecs.umich.edu return fault; 14744011Ssaidi@eecs.umich.edu Mem.uw = Fsr<31:0>; 14754008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 14764011Ssaidi@eecs.umich.edu 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 14774011Ssaidi@eecs.umich.edu if (fault) 14784011Ssaidi@eecs.umich.edu return fault; 14794011Ssaidi@eecs.umich.edu Mem.udw = Fsr; 14804011Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 14814008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 14822526SN/A } 14832526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 14843272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 14852526SN/A 0x2D: Nop::prefetch({{ }}); 14863931Ssaidi@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 14872526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 14883272Sgblack@eecs.umich.edu format LoadAlt { 14893272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 14903272Sgblack@eecs.umich.edu //ASI_NUCLEUS 14913272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 14923272Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 14933272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 14943272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 14953272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 14963272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 14973272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 14983272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 14993272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 15003272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 15013272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 15023272Sgblack@eecs.umich.edu //ASI_REAL 15033272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 15043272Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 15053272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 15063272Sgblack@eecs.umich.edu //ASI_REAL_IO 15073272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 15083272Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 15093272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 15103272Sgblack@eecs.umich.edu //ASI_PRIMARY 15113272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 15123272Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 15133272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 15143272Sgblack@eecs.umich.edu //ASI_SECONDARY 15153272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 15163272Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 15173272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 15183272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 15193272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 15203272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 15213272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 15223272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 15233272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 15243272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 15253272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 15263272Sgblack@eecs.umich.edu 15273272Sgblack@eecs.umich.edu format BlockLoad { 15283272Sgblack@eecs.umich.edu // LDBLOCKF 15293272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 15303272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 15313272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 15323272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 15333272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 15343272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 15353272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 15363272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 15373272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 15383810Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 15393272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 15403272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 15413272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 15423272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 15433272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 15443272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 15453272Sgblack@eecs.umich.edu } 15463272Sgblack@eecs.umich.edu 15473272Sgblack@eecs.umich.edu //LDSHORTF 15483272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 15493272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 15503272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 15513272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 15523272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 15533272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 15543272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 15553272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 15563272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 15573272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 15583272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 15593272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 15603272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 15613272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 15623272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 15633272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 15643272Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 15653378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 15663378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 15673272Sgblack@eecs.umich.edu } 15683272Sgblack@eecs.umich.edu } 15693931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 15702954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 15713378Sgblack@eecs.umich.edu format StoreAlt { 15723378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 15733378Sgblack@eecs.umich.edu //ASI_NUCLEUS 15743378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 15753378Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 15763378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 15773378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 15783378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 15793378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 15803378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 15813378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 15823378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 15833378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 15843378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 15853378Sgblack@eecs.umich.edu //ASI_REAL 15863378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 15873378Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 15883378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 15893378Sgblack@eecs.umich.edu //ASI_REAL_IO 15903378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 15913378Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 15923378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 15933378Sgblack@eecs.umich.edu //ASI_PRIMARY 15943378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 15953378Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 15963378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 15973378Sgblack@eecs.umich.edu //ASI_SECONDARY 15983378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 15993378Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 16003378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 16013378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 16023378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 16033378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 16043378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 16053378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 16063378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 16073378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 16083378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 16093378Sgblack@eecs.umich.edu 16103378Sgblack@eecs.umich.edu format BlockStore { 16113378Sgblack@eecs.umich.edu // STBLOCKF 16123378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 16133378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 16143378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 16153378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 16163378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 16173378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 16183378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 16193378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 16203378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 16213810Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 16223378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 16233378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 16243378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 16253378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 16263378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 16273378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 16283378Sgblack@eecs.umich.edu } 16293378Sgblack@eecs.umich.edu 16303378Sgblack@eecs.umich.edu //STSHORTF 16313378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 16323378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 16333378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 16343378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 16353378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 16363378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 16373378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 16383378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 16393378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 16403378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 16413378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 16423378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 16433378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 16443378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 16453378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 16463378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 16473378Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 16483378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 16493378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 16503378Sgblack@eecs.umich.edu } 16513378Sgblack@eecs.umich.edu } 16524040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 16534040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 16544040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 16554040Ssaidi@eecs.umich.edu {{ 16564040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 16574040Ssaidi@eecs.umich.edu Rd.uw = tmp; 16584040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP_COND); 16592526SN/A 0x3D: Nop::prefetcha({{ }}); 16604040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 16614040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 16624040Ssaidi@eecs.umich.edu {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 16632526SN/A } 16642469SN/A } 16652022SN/A} 1666