decoder.isa revision 3765
12SN/A// Copyright (c) 2006 The Regents of The University of Michigan 210298Salexandru.dutu@amd.com// All rights reserved. 38852Sandreas.hansson@arm.com// 48852Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 58852Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 68852Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 78852Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 88852Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 98852Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 108852Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 118852Sandreas.hansson@arm.com// neither the name of the copyright holders nor the names of its 128852Sandreas.hansson@arm.com// contributors may be used to endorse or promote products derived from 138852Sandreas.hansson@arm.com// this software without specific prior written permission. 148852Sandreas.hansson@arm.com// 151762SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A// 272SN/A// Authors: Ali Saidi 282SN/A// Gabe Black 292SN/A// Steve Reinhardt 302SN/A 312SN/A//////////////////////////////////////////////////////////////////// 322SN/A// 332SN/A// The actual decoder specification 342SN/A// 352SN/A 362SN/Adecode OP default Unknown::unknown() 372SN/A{ 382SN/A 0x0: decode OP2 392SN/A { 402665Ssaidi@eecs.umich.edu //Throw an illegal instruction acception 412665Ssaidi@eecs.umich.edu 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422665Ssaidi@eecs.umich.edu format BranchN 432665Ssaidi@eecs.umich.edu { 442SN/A //bpcc 452SN/A 0x1: decode COND2 468229Snate@binkert.org { 472SN/A //Branch Always 486712Snate@binkert.org 0x8: decode A 496712Snate@binkert.org { 502SN/A 0x0: bpa(19, {{ 512SN/A NNPC = xc->readPC() + disp; 5256SN/A }}); 531158SN/A 0x1: bpa(19, {{ 548229Snate@binkert.org NPC = xc->readPC() + disp; 55146SN/A NNPC = NPC + 4; 566658Snate@binkert.org }}, ',a'); 572680Sktlim@umich.edu } 582378SN/A //Branch Never 5910298Salexandru.dutu@amd.com 0x0: decode A 608706Sandreas.hansson@arm.com { 618229Snate@binkert.org 0x0: bpn(19, {{ 625154Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 635512SMichael.Adler@intel.com }}); 64360SN/A 0x1: bpn(19, {{ 654434Ssaidi@eecs.umich.edu NPC = xc->readNextPC() + 4; 66695SN/A NNPC = NPC + 4; 672093SN/A }}, ',a'); 682378SN/A } 692SN/A default: decode BPCC 702715Sstever@eecs.umich.edu { 712715Sstever@eecs.umich.edu 0x0: bpcci(19, {{ 722715Sstever@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 732715Sstever@eecs.umich.edu NNPC = xc->readPC() + disp; 742715Sstever@eecs.umich.edu else 752715Sstever@eecs.umich.edu handle_annul 762715Sstever@eecs.umich.edu }}); 772715Sstever@eecs.umich.edu 0x2: bpccx(19, {{ 785335Shines@cs.fsu.edu if(passesCondition(Ccr<7:4>, COND2)) 795335Shines@cs.fsu.edu { 8010810Sbr@bsdpad.com //warn("Took branch!\n"); 814157Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 824166Sgblack@eecs.umich.edu } 836691Stjones1@inf.ed.ac.uk else 846691Stjones1@inf.ed.ac.uk { 852715Sstever@eecs.umich.edu //warn("Didn't take branch!\n"); 862715Sstever@eecs.umich.edu handle_annul 872715Sstever@eecs.umich.edu } 882715Sstever@eecs.umich.edu }}); 892715Sstever@eecs.umich.edu } 902SN/A } 912107SN/A //bicc 922SN/A 0x2: decode COND2 932SN/A { 942SN/A //Branch Always 952SN/A 0x8: decode A 965758Shsul@eecs.umich.edu { 975771Shsul@eecs.umich.edu 0x0: ba(22, {{ 985758Shsul@eecs.umich.edu NNPC = xc->readPC() + disp; 995758Shsul@eecs.umich.edu }}); 1005758Shsul@eecs.umich.edu 0x1: ba(22, {{ 1015758Shsul@eecs.umich.edu NPC = xc->readPC() + disp; 1025758Shsul@eecs.umich.edu NNPC = NPC + 4; 1038737Skoansin.tan@gmail.com }}, ',a'); 1048737Skoansin.tan@gmail.com } 1055758Shsul@eecs.umich.edu //Branch Never 1065154Sgblack@eecs.umich.edu 0x0: decode A 1077532Ssteve.reinhardt@amd.com { 10810559Sandreas.hansson@arm.com 0x0: bn(22, {{ 1098852Sandreas.hansson@arm.com NNPC = NNPC;//Don't do anything 11010559Sandreas.hansson@arm.com }}); 1118852Sandreas.hansson@arm.com 0x1: bn(22, {{ 11210299Salexandru.dutu@amd.com NPC = xc->readNextPC() + 4; 11310554Salexandru.dutu@amd.com NNPC = NPC + 4; 11410299Salexandru.dutu@amd.com }}, ',a'); 11510299Salexandru.dutu@amd.com } 11610299Salexandru.dutu@amd.com default: bicc(22, {{ 1178852Sandreas.hansson@arm.com if(passesCondition(Ccr<3:0>, COND2)) 1188852Sandreas.hansson@arm.com NNPC = xc->readPC() + disp; 1192SN/A else 1205154Sgblack@eecs.umich.edu handle_annul 1215154Sgblack@eecs.umich.edu }}); 1225514SMichael.Adler@intel.com } 1235154Sgblack@eecs.umich.edu } 1245154Sgblack@eecs.umich.edu 0x3: decode RCOND2 1255154Sgblack@eecs.umich.edu { 1265154Sgblack@eecs.umich.edu format BranchSplit 1275154Sgblack@eecs.umich.edu { 1285154Sgblack@eecs.umich.edu 0x1: bpreq({{ 1295154Sgblack@eecs.umich.edu if(Rs1.sdw == 0) 1305154Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1315154Sgblack@eecs.umich.edu else 1325154Sgblack@eecs.umich.edu handle_annul 1335154Sgblack@eecs.umich.edu }}); 1345154Sgblack@eecs.umich.edu 0x2: bprle({{ 1355154Sgblack@eecs.umich.edu if(Rs1.sdw <= 0) 1365154Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1375154Sgblack@eecs.umich.edu else 1385154Sgblack@eecs.umich.edu handle_annul 1395154Sgblack@eecs.umich.edu }}); 1405154Sgblack@eecs.umich.edu 0x3: bprl({{ 1415154Sgblack@eecs.umich.edu if(Rs1.sdw < 0) 1425154Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1435514SMichael.Adler@intel.com else 1445514SMichael.Adler@intel.com handle_annul 1455514SMichael.Adler@intel.com }}); 1465514SMichael.Adler@intel.com 0x5: bprne({{ 1475514SMichael.Adler@intel.com if(Rs1.sdw != 0) 1485514SMichael.Adler@intel.com NNPC = xc->readPC() + disp; 1495514SMichael.Adler@intel.com else 1505514SMichael.Adler@intel.com handle_annul 1515514SMichael.Adler@intel.com }}); 1525514SMichael.Adler@intel.com 0x6: bprg({{ 1535154Sgblack@eecs.umich.edu if(Rs1.sdw > 0) 1542SN/A NNPC = xc->readPC() + disp; 1555282Srstrong@cs.ucsd.edu else 1565282Srstrong@cs.ucsd.edu handle_annul 1575282Srstrong@cs.ucsd.edu }}); 1585282Srstrong@cs.ucsd.edu 0x7: bprge({{ 1595282Srstrong@cs.ucsd.edu if(Rs1.sdw >= 0) 1605282Srstrong@cs.ucsd.edu NNPC = xc->readPC() + disp; 1615282Srstrong@cs.ucsd.edu else 1625282Srstrong@cs.ucsd.edu handle_annul 1635282Srstrong@cs.ucsd.edu }}); 1645282Srstrong@cs.ucsd.edu } 1655282Srstrong@cs.ucsd.edu } 1665282Srstrong@cs.ucsd.edu //SETHI (or NOP if rd == 0 and imm == 0) 1675282Srstrong@cs.ucsd.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1685282Srstrong@cs.ucsd.edu 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 1695282Srstrong@cs.ucsd.edu 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 1705282Srstrong@cs.ucsd.edu } 1715514SMichael.Adler@intel.com 0x1: BranchN::call(30, {{ 1725282Srstrong@cs.ucsd.edu R15 = xc->readPC(); 1735282Srstrong@cs.ucsd.edu NNPC = R15 + disp; 1745282Srstrong@cs.ucsd.edu }}); 1755282Srstrong@cs.ucsd.edu 0x2: decode OP3 { 1762SN/A format IntOp { 1772SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1782SN/A 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1799550Sandreas.hansson@arm.com 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1805282Srstrong@cs.ucsd.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1812SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1822SN/A 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1831450SN/A 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1841514SN/A 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1852SN/A 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1862SN/A 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1872SN/A 0x0A: umul({{ 1882378SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1892SN/A Y = Rd<63:32>; 1902SN/A }}); 1912SN/A 0x0B: smul({{ 192729SN/A Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 1932SN/A Y = Rd.sdw; 1942SN/A }}); 1958240Snate@binkert.org 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1962SN/A 0x0D: udivx({{ 1972SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1982SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1992SN/A }}); 2002SN/A 0x0E: udiv({{ 2012SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 2022SN/A else 2032SN/A { 2042SN/A Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 2052SN/A if(Rd.udw >> 32 != 0) 2062SN/A Rd.udw = 0xFFFFFFFF; 2072SN/A } 2082SN/A }}); 2092SN/A 0x0F: sdiv({{ 2102SN/A if(Rs2_or_imm13.sdw == 0) 2112SN/A fault = new DivisionByZero; 2122SN/A else 2132SN/A { 2142SN/A Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 2152SN/A if(Rd.udw<63:31> != 0) 2162SN/A Rd.udw = 0x7FFFFFFF; 2172SN/A else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 2182SN/A Rd.udw = 0xFFFFFFFF80000000ULL; 2192SN/A } 2202SN/A }}); 2215514SMichael.Adler@intel.com } 2222SN/A format IntOpCc { 2232SN/A 0x10: addcc({{ 2242SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2252SN/A Rd = resTemp = Rs1 + val2;}}, 2262SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 2272SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2282SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 2292SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2302SN/A ); 2312SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2325713Shsul@eecs.umich.edu 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2335713Shsul@eecs.umich.edu 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2342SN/A 0x14: subcc({{ 2355713Shsul@eecs.umich.edu int64_t val2 = Rs2_or_imm13; 2365713Shsul@eecs.umich.edu Rd = Rs1 - val2;}}, 2375713Shsul@eecs.umich.edu {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 2385713Shsul@eecs.umich.edu {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 2396029Ssteve.reinhardt@amd.com {{(~(Rs1<63:1> + (~val2)<63:1> + 2405713Shsul@eecs.umich.edu (Rs1 | ~val2)<0:>))<63:>}}, 2415713Shsul@eecs.umich.edu {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 2425713Shsul@eecs.umich.edu ); 2435512SMichael.Adler@intel.com 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2445713Shsul@eecs.umich.edu 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2452SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2462SN/A 0x18: addccc({{ 2471395SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2487532Ssteve.reinhardt@amd.com int64_t carryin = Ccr<0:0>; 2491395SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 2505713Shsul@eecs.umich.edu {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 2515713Shsul@eecs.umich.edu {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2522378SN/A {{(Rs1<63:1> + val2<63:1> + 2532680Sktlim@umich.edu ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 2545713Shsul@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2551395SN/A ); 2561634SN/A 0x1A: IntOpCcRes::umulcc({{ 25710407Smitch.hayenga@arm.com uint64_t resTemp; 25810298Salexandru.dutu@amd.com Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 25910298Salexandru.dutu@amd.com Y = resTemp<63:32>;}}); 2601395SN/A 0x1B: IntOpCcRes::smulcc({{ 2612SN/A int64_t resTemp; 2622SN/A Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 2632SN/A Y = resTemp<63:32>;}}); 2642SN/A 0x1C: subccc({{ 2652SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2662SN/A int64_t carryin = Ccr<0:0>; 2672SN/A Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 2682SN/A {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 2695282Srstrong@cs.ucsd.edu {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2705282Srstrong@cs.ucsd.edu {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 2712SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2722SN/A ); 2732SN/A 0x1D: IntOpCcRes::udivxcc({{ 2742SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2752SN/A else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 27610782Snilay@cs.wisc.edu 0x1E: udivcc({{ 27710782Snilay@cs.wisc.edu uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2782SN/A int32_t overflow = 0; 2792SN/A if(val2 == 0) fault = new DivisionByZero; 2802SN/A else 2812SN/A { 2822SN/A resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2832SN/A overflow = (resTemp<63:32> != 0); 2845282Srstrong@cs.ucsd.edu if(overflow) Rd = resTemp = 0xFFFFFFFF; 2855282Srstrong@cs.ucsd.edu else Rd = resTemp; 28610496Ssteve.reinhardt@amd.com } }}, 2875282Srstrong@cs.ucsd.edu {{0}}, 2885282Srstrong@cs.ucsd.edu {{overflow}}, 2895282Srstrong@cs.ucsd.edu {{0}}, 2905282Srstrong@cs.ucsd.edu {{0}} 2915282Srstrong@cs.ucsd.edu ); 2925282Srstrong@cs.ucsd.edu 0x1F: sdivcc({{ 2935282Srstrong@cs.ucsd.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2941970SN/A bool overflow = false, underflow = false; 2951970SN/A if(val2 == 0) fault = new DivisionByZero; 2962SN/A else 2972SN/A { 2981970SN/A Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2991970SN/A overflow = (Rd<63:31> != 0); 3002SN/A underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 3011970SN/A if(overflow) Rd = 0x7FFFFFFF; 3021970SN/A else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 3031970SN/A } }}, 3041970SN/A {{0}}, 3051970SN/A {{overflow || underflow}}, 3065282Srstrong@cs.ucsd.edu {{0}}, 3075282Srstrong@cs.ucsd.edu {{0}} 3081970SN/A ); 3091970SN/A 0x20: taddcc({{ 3105282Srstrong@cs.ucsd.edu int64_t resTemp, val2 = Rs2_or_imm13; 3115282Srstrong@cs.ucsd.edu Rd = resTemp = Rs1 + val2; 3125282Srstrong@cs.ucsd.edu int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 3135282Srstrong@cs.ucsd.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3145282Srstrong@cs.ucsd.edu {{overflow}}, 3155282Srstrong@cs.ucsd.edu {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3165282Srstrong@cs.ucsd.edu {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 31710496Ssteve.reinhardt@amd.com ); 3182SN/A 0x21: tsubcc({{ 3192SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3202SN/A Rd = resTemp = Rs1 + val2; 3212SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 3222SN/A {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 3232SN/A {{overflow}}, 3242SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3258324Ssteve.reinhardt@amd.com {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3262SN/A ); 3272SN/A 0x22: taddcctv({{ 3285282Srstrong@cs.ucsd.edu int64_t val2 = Rs2_or_imm13; 3292SN/A Rd = Rs1 + val2; 3302SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || 3315282Srstrong@cs.ucsd.edu (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 3325282Srstrong@cs.ucsd.edu if(overflow) fault = new TagOverflow;}}, 3335282Srstrong@cs.ucsd.edu {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3348324Ssteve.reinhardt@amd.com {{overflow}}, 3358324Ssteve.reinhardt@amd.com {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3365282Srstrong@cs.ucsd.edu {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 3375282Srstrong@cs.ucsd.edu ); 3385282Srstrong@cs.ucsd.edu 0x23: tsubcctv({{ 3397487Ssteve.reinhardt@amd.com int64_t resTemp, val2 = Rs2_or_imm13; 3408601Ssteve.reinhardt@amd.com Rd = resTemp = Rs1 + val2; 3418601Ssteve.reinhardt@amd.com int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 3428601Ssteve.reinhardt@amd.com if(overflow) fault = new TagOverflow;}}, 34310318Sandreas.hansson@arm.com {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 3448601Ssteve.reinhardt@amd.com {{overflow}}, 34510558Salexandru.dutu@amd.com {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3468601Ssteve.reinhardt@amd.com {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3478601Ssteve.reinhardt@amd.com ); 3484434Ssaidi@eecs.umich.edu 0x24: mulscc({{ 3498539Sgblack@eecs.umich.edu int64_t resTemp, multiplicand = Rs2_or_imm13; 3504434Ssaidi@eecs.umich.edu int32_t multiplier = Rs1<31:0>; 3518539Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 3528539Sgblack@eecs.umich.edu multiplier = multiplier<31:1> | 3534434Ssaidi@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 32); 35410318Sandreas.hansson@arm.com if(!Y<0:>) 3554434Ssaidi@eecs.umich.edu multiplicand = 0; 3564434Ssaidi@eecs.umich.edu Rd = resTemp = multiplicand + multiplier; 3574434Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 3588539Sgblack@eecs.umich.edu {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}}, 3598539Sgblack@eecs.umich.edu {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 3605154Sgblack@eecs.umich.edu {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 3615154Sgblack@eecs.umich.edu {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 3625154Sgblack@eecs.umich.edu ); 3638539Sgblack@eecs.umich.edu } 3645154Sgblack@eecs.umich.edu format IntOp 3658601Ssteve.reinhardt@amd.com { 3665823Ssaidi@eecs.umich.edu 0x25: decode X { 3675154Sgblack@eecs.umich.edu 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3684434Ssaidi@eecs.umich.edu 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3694434Ssaidi@eecs.umich.edu } 3704434Ssaidi@eecs.umich.edu 0x26: decode X { 3714434Ssaidi@eecs.umich.edu 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3724434Ssaidi@eecs.umich.edu 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3737487Ssteve.reinhardt@amd.com } 3745282Srstrong@cs.ucsd.edu 0x27: decode X { 3757487Ssteve.reinhardt@amd.com 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3767487Ssteve.reinhardt@amd.com 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3775282Srstrong@cs.ucsd.edu } 3785282Srstrong@cs.ucsd.edu 0x28: decode RS1 { 3795282Srstrong@cs.ucsd.edu 0x00: NoPriv::rdy({{Rd = Y;}}); 3805282Srstrong@cs.ucsd.edu //1 should cause an illegal instruction exception 3815282Srstrong@cs.ucsd.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3825514SMichael.Adler@intel.com 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3835282Srstrong@cs.ucsd.edu 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3845282Srstrong@cs.ucsd.edu 0x05: NoPriv::rdpc({{ 3855282Srstrong@cs.ucsd.edu if(Pstate<3:>) 3865282Srstrong@cs.ucsd.edu Rd = (xc->readPC())<31:0>; 3875282Srstrong@cs.ucsd.edu else 3885282Srstrong@cs.ucsd.edu Rd = xc->readPC();}}); 38910782Snilay@cs.wisc.edu 0x06: NoPriv::rdfprs({{ 3905282Srstrong@cs.ucsd.edu //Wait for all fpops to finish. 3917487Ssteve.reinhardt@amd.com Rd = Fprs; 3927487Ssteve.reinhardt@amd.com }}); 3935282Srstrong@cs.ucsd.edu //7-14 should cause an illegal instruction exception 3945282Srstrong@cs.ucsd.edu 0x0F: decode I { 3955282Srstrong@cs.ucsd.edu 0x0: Nop::stbar({{/*stuff*/}}); 3965282Srstrong@cs.ucsd.edu 0x1: Nop::membar({{/*stuff*/}}); 3975282Srstrong@cs.ucsd.edu } 3985282Srstrong@cs.ucsd.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3995282Srstrong@cs.ucsd.edu 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 4005282Srstrong@cs.ucsd.edu //0x12 should cause an illegal instruction exception 4015282Srstrong@cs.ucsd.edu 0x13: NoPriv::rdgsr({{ 40210782Snilay@cs.wisc.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 4035282Srstrong@cs.ucsd.edu Rd = Gsr; 4047487Ssteve.reinhardt@amd.com else 4055282Srstrong@cs.ucsd.edu fault = new FpDisabled; 4065514SMichael.Adler@intel.com }}); 4075514SMichael.Adler@intel.com //0x14-0x15 should cause an illegal instruction exception 4085282Srstrong@cs.ucsd.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 4095282Srstrong@cs.ucsd.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 4105514SMichael.Adler@intel.com 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 4115514SMichael.Adler@intel.com 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 4125514SMichael.Adler@intel.com 0x1A: Priv::rdstrand_sts_reg({{ 4135514SMichael.Adler@intel.com if(Pstate<2:> && !Hpstate<2:>) 41410782Snilay@cs.wisc.edu Rd = StrandStsReg<0:>; 4155514SMichael.Adler@intel.com else 4165514SMichael.Adler@intel.com Rd = StrandStsReg; 4175514SMichael.Adler@intel.com }}); 4185514SMichael.Adler@intel.com //0x1A is supposed to be reserved, but it reads the strand 4195514SMichael.Adler@intel.com //status register. 4205514SMichael.Adler@intel.com //0x1B-0x1F should cause an illegal instruction exception 4215514SMichael.Adler@intel.com } 4225514SMichael.Adler@intel.com 0x29: decode RS1 { 4235282Srstrong@cs.ucsd.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 4245282Srstrong@cs.ucsd.edu 0x01: HPriv::rdhprhtstate({{ 4255282Srstrong@cs.ucsd.edu if(Tl == 0) 4265282Srstrong@cs.ucsd.edu return new IllegalInstruction; 4275282Srstrong@cs.ucsd.edu Rd = Htstate; 4285282Srstrong@cs.ucsd.edu }}); 4295282Srstrong@cs.ucsd.edu //0x02 should cause an illegal instruction exception 4305282Srstrong@cs.ucsd.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 4315282Srstrong@cs.ucsd.edu //0x04 should cause an illegal instruction exception 4325282Srstrong@cs.ucsd.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 4335282Srstrong@cs.ucsd.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 4345282Srstrong@cs.ucsd.edu //0x07-0x1E should cause an illegal instruction exception 4355282Srstrong@cs.ucsd.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 4365282Srstrong@cs.ucsd.edu } 4375282Srstrong@cs.ucsd.edu 0x2A: decode RS1 { 4385282Srstrong@cs.ucsd.edu 0x00: Priv::rdprtpc({{ 4395282Srstrong@cs.ucsd.edu if(Tl == 0) 4405282Srstrong@cs.ucsd.edu return new IllegalInstruction; 4415282Srstrong@cs.ucsd.edu Rd = Tpc; 4425282Srstrong@cs.ucsd.edu }}); 4435282Srstrong@cs.ucsd.edu 0x01: Priv::rdprtnpc({{ 4445282Srstrong@cs.ucsd.edu if(Tl == 0) 4455282Srstrong@cs.ucsd.edu return new IllegalInstruction; 4465282Srstrong@cs.ucsd.edu Rd = Tnpc; 4475282Srstrong@cs.ucsd.edu }}); 4485282Srstrong@cs.ucsd.edu 0x02: Priv::rdprtstate({{ 4495282Srstrong@cs.ucsd.edu if(Tl == 0) 4505282Srstrong@cs.ucsd.edu return new IllegalInstruction; 4515282Srstrong@cs.ucsd.edu Rd = Tstate; 4525282Srstrong@cs.ucsd.edu }}); 4535282Srstrong@cs.ucsd.edu 0x03: Priv::rdprtt({{ 4545282Srstrong@cs.ucsd.edu if(Tl == 0) 4555282Srstrong@cs.ucsd.edu return new IllegalInstruction; 4565282Srstrong@cs.ucsd.edu Rd = Tt; 4575282Srstrong@cs.ucsd.edu }}); 4585282Srstrong@cs.ucsd.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 4595282Srstrong@cs.ucsd.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 4605282Srstrong@cs.ucsd.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 46110782Snilay@cs.wisc.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 4627487Ssteve.reinhardt@amd.com 0x08: Priv::rdprpil({{Rd = Pil;}}); 4637487Ssteve.reinhardt@amd.com 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 4645282Srstrong@cs.ucsd.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 4655282Srstrong@cs.ucsd.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 4665282Srstrong@cs.ucsd.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 4675282Srstrong@cs.ucsd.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 4687487Ssteve.reinhardt@amd.com 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 4695282Srstrong@cs.ucsd.edu //0x0F should cause an illegal instruction exception 4707487Ssteve.reinhardt@amd.com 0x10: Priv::rdprgl({{Rd = Gl;}}); 4717487Ssteve.reinhardt@amd.com //0x11-0x1F should cause an illegal instruction exception 4725282Srstrong@cs.ucsd.edu } 4735282Srstrong@cs.ucsd.edu 0x2B: BasicOperate::flushw({{ 4745282Srstrong@cs.ucsd.edu if(NWindows - 2 - Cansave == 0) 4755282Srstrong@cs.ucsd.edu { 4767487Ssteve.reinhardt@amd.com if(Otherwin) 47710782Snilay@cs.wisc.edu fault = new SpillNOther(Wstate<5:3>); 47810782Snilay@cs.wisc.edu else 4795282Srstrong@cs.ucsd.edu fault = new SpillNNormal(Wstate<2:0>); 4805282Srstrong@cs.ucsd.edu } 4815282Srstrong@cs.ucsd.edu }}); 4825282Srstrong@cs.ucsd.edu 0x2C: decode MOVCC3 4835282Srstrong@cs.ucsd.edu { 4847487Ssteve.reinhardt@amd.com 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 4857487Ssteve.reinhardt@amd.com 0x1: decode CC 4865282Srstrong@cs.ucsd.edu { 4875282Srstrong@cs.ucsd.edu 0x0: movcci({{ 4885282Srstrong@cs.ucsd.edu if(passesCondition(Ccr<3:0>, COND4)) 4895282Srstrong@cs.ucsd.edu Rd = Rs2_or_imm11; 4905282Srstrong@cs.ucsd.edu else 4915282Srstrong@cs.ucsd.edu Rd = Rd; 4925282Srstrong@cs.ucsd.edu }}); 4935282Srstrong@cs.ucsd.edu 0x2: movccx({{ 4945282Srstrong@cs.ucsd.edu if(passesCondition(Ccr<7:4>, COND4)) 4955282Srstrong@cs.ucsd.edu Rd = Rs2_or_imm11; 4965282Srstrong@cs.ucsd.edu else 4975282Srstrong@cs.ucsd.edu Rd = Rd; 4985282Srstrong@cs.ucsd.edu }}); 4995282Srstrong@cs.ucsd.edu } 5005282Srstrong@cs.ucsd.edu } 5015282Srstrong@cs.ucsd.edu 0x2D: sdivx({{ 5025282Srstrong@cs.ucsd.edu if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 5035282Srstrong@cs.ucsd.edu else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 5045282Srstrong@cs.ucsd.edu }}); 5055282Srstrong@cs.ucsd.edu 0x2E: decode RS1 { 5065282Srstrong@cs.ucsd.edu 0x0: IntOp::popc({{ 5075282Srstrong@cs.ucsd.edu int64_t count = 0; 5085282Srstrong@cs.ucsd.edu uint64_t temp = Rs2_or_imm13; 5095282Srstrong@cs.ucsd.edu //Count the 1s in the front 4bits until none are left 5105282Srstrong@cs.ucsd.edu uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 5115282Srstrong@cs.ucsd.edu while(temp) 5123311Ssaidi@eecs.umich.edu { 5133311Ssaidi@eecs.umich.edu count += oneBits[temp & 0xF]; 5143311Ssaidi@eecs.umich.edu temp = temp >> 4; 5153311Ssaidi@eecs.umich.edu } 5163311Ssaidi@eecs.umich.edu Rd = count; 5173311Ssaidi@eecs.umich.edu }}); 5183311Ssaidi@eecs.umich.edu } 5193311Ssaidi@eecs.umich.edu 0x2F: decode RCOND3 5203311Ssaidi@eecs.umich.edu { 5213311Ssaidi@eecs.umich.edu 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 5223311Ssaidi@eecs.umich.edu 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 5233311Ssaidi@eecs.umich.edu 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 5245282Srstrong@cs.ucsd.edu 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 5255282Srstrong@cs.ucsd.edu 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 5265282Srstrong@cs.ucsd.edu 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 5275282Srstrong@cs.ucsd.edu } 5285282Srstrong@cs.ucsd.edu 0x30: decode RD { 5295282Srstrong@cs.ucsd.edu 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 5306820SLisa.Hsu@amd.com //0x01 should cause an illegal instruction exception 5313311Ssaidi@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 5323311Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 5333311Ssaidi@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 5343311Ssaidi@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 5353311Ssaidi@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 5363311Ssaidi@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 5373311Ssaidi@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 5383311Ssaidi@eecs.umich.edu 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 5393311Ssaidi@eecs.umich.edu //0x12 should cause an illegal instruction exception 5403311Ssaidi@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 5413311Ssaidi@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 5423311Ssaidi@eecs.umich.edu return new FpDisabled; 5433311Ssaidi@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 5443311Ssaidi@eecs.umich.edu }}); 5453311Ssaidi@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 5463311Ssaidi@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 5475282Srstrong@cs.ucsd.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 5485282Srstrong@cs.ucsd.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5497487Ssteve.reinhardt@amd.com 0x18: NoPriv::wrstick({{ 5505282Srstrong@cs.ucsd.edu if(!Hpstate<2:>) 5516820SLisa.Hsu@amd.com return new IllegalInstruction; 5526820SLisa.Hsu@amd.com Stick = Rs1 ^ Rs2_or_imm13; 5536820SLisa.Hsu@amd.com }}); 5546820SLisa.Hsu@amd.com 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5556820SLisa.Hsu@amd.com 0x1A: Priv::wrstrand_sts_reg({{ 5563311Ssaidi@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5572SN/A StrandStsReg = StrandStsReg<63:1> | 5582SN/A (Rs1 ^ Rs2_or_imm13)<0:>; 5599110Ssteve.reinhardt@amd.com else 56010558Salexandru.dutu@amd.com StrandStsReg = Rs1 ^ Rs2_or_imm13; 5619110Ssteve.reinhardt@amd.com }}); 56210558Salexandru.dutu@amd.com //0x1A is supposed to be reserved, but it writes the strand 56310558Salexandru.dutu@amd.com //status register. 5649110Ssteve.reinhardt@amd.com //0x1B-0x1F should cause an illegal instruction exception 5659110Ssteve.reinhardt@amd.com } 5669110Ssteve.reinhardt@amd.com 0x31: decode FCN { 5679110Ssteve.reinhardt@amd.com 0x0: Priv::saved({{ 5682SN/A assert(Cansave < NWindows - 2); 5692SN/A assert(Otherwin || Canrestore); 5702SN/A Cansave = Cansave + 1; 5712SN/A if(Otherwin == 0) 5722SN/A Canrestore = Canrestore - 1; 5732SN/A else 57412SN/A Otherwin = Otherwin - 1; 57510499Ssteve.reinhardt@amd.com }}); 5765154Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 57710496Ssteve.reinhardt@amd.com assert(Cansave || Otherwin); 57810499Ssteve.reinhardt@amd.com assert(Canrestore < NWindows - 2); 57910499Ssteve.reinhardt@amd.com Canrestore = Canrestore + 1; 58010499Ssteve.reinhardt@amd.com if(Otherwin == 0) 58110496Ssteve.reinhardt@amd.com Cansave = Cansave - 1; 5822SN/A else 5833114Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 5841158SN/A }}); 5851158SN/A } 5861158SN/A 0x32: decode RD { 5871158SN/A 0x00: Priv::wrprtpc({{ 5881158SN/A if(Tl == 0) 5899641Sguodeyuan@tsinghua.org.cn return new IllegalInstruction; 5909641Sguodeyuan@tsinghua.org.cn else 5911158SN/A Tpc = Rs1 ^ Rs2_or_imm13; 5921158SN/A }}); 5931158SN/A 0x01: Priv::wrprtnpc({{ 5941158SN/A if(Tl == 0) 5951158SN/A return new IllegalInstruction; 5962378SN/A else 5971158SN/A Tnpc = Rs1 ^ Rs2_or_imm13; 5982378SN/A }}); 5992680Sktlim@umich.edu 0x02: Priv::wrprtstate({{ 6002093SN/A if(Tl == 0) 6012093SN/A return new IllegalInstruction; 6022093SN/A else 6032093SN/A Tstate = Rs1 ^ Rs2_or_imm13; 6042093SN/A }}); 6052093SN/A 0x03: Priv::wrprtt({{ 6062093SN/A if(Tl == 0) 6072680Sktlim@umich.edu return new IllegalInstruction; 6082093SN/A else 6092SN/A Tt = Rs1 ^ Rs2_or_imm13; 6106701Sgblack@eecs.umich.edu }}); 6116701Sgblack@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 6126701Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 6136701Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 6146701Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 6156701Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 61610496Ssteve.reinhardt@amd.com Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 61710496Ssteve.reinhardt@amd.com else 61810496Ssteve.reinhardt@amd.com Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 61910496Ssteve.reinhardt@amd.com }}); 62010496Ssteve.reinhardt@amd.com 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 62110496Ssteve.reinhardt@amd.com 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 62210496Ssteve.reinhardt@amd.com 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 62310496Ssteve.reinhardt@amd.com 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 62410496Ssteve.reinhardt@amd.com 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 62510496Ssteve.reinhardt@amd.com 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 62610496Ssteve.reinhardt@amd.com 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 62710496Ssteve.reinhardt@amd.com //0x0F should cause an illegal instruction exception 62810496Ssteve.reinhardt@amd.com 0x10: Priv::wrprgl({{ 6292715Sstever@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 6305154Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 6312715Sstever@eecs.umich.edu else 6322715Sstever@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 6332715Sstever@eecs.umich.edu }}); 6345154Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 6355154Sgblack@eecs.umich.edu } 6362715Sstever@eecs.umich.edu 0x33: decode RD { 6372715Sstever@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 6382715Sstever@eecs.umich.edu 0x01: HPriv::wrhprhtstate({{ 6392715Sstever@eecs.umich.edu if(Tl == 0) 6402715Sstever@eecs.umich.edu return new IllegalInstruction; 6413917Ssaidi@eecs.umich.edu Htstate = Rs1 ^ Rs2_or_imm13; 6423917Ssaidi@eecs.umich.edu }}); 6435070Ssaidi@eecs.umich.edu //0x02 should cause an illegal instruction exception 6443917Ssaidi@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 6453917Ssaidi@eecs.umich.edu //0x04 should cause an illegal instruction exception 6465089Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 6475753Ssteve.reinhardt@amd.com //0x06-0x01D should cause an illegal instruction exception 6485753Ssteve.reinhardt@amd.com 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 6495753Ssteve.reinhardt@amd.com } 6502715Sstever@eecs.umich.edu 0x34: decode OPF{ 6512715Sstever@eecs.umich.edu format BasicOperate{ 6525154Sgblack@eecs.umich.edu 0x01: fmovs({{ 6532715Sstever@eecs.umich.edu Frds.uw = Frs2s.uw; 6542715Sstever@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6555753Ssteve.reinhardt@amd.com Fsr &= ~(7 << 14); 6565753Ssteve.reinhardt@amd.com Fsr &= ~(0x1F); 6575753Ssteve.reinhardt@amd.com }}); 6582715Sstever@eecs.umich.edu 0x02: fmovd({{ 6595154Sgblack@eecs.umich.edu Frd.udw = Frs2.udw; 6602715Sstever@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6612715Sstever@eecs.umich.edu Fsr &= ~(7 << 14); 6622715Sstever@eecs.umich.edu Fsr &= ~(0x1F); 6632715Sstever@eecs.umich.edu }}); 6642715Sstever@eecs.umich.edu 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 6652715Sstever@eecs.umich.edu 0x05: fnegs({{ 6665753Ssteve.reinhardt@amd.com Frds.uw = Frs2s.uw ^ (1UL << 31); 6675753Ssteve.reinhardt@amd.com //fsr.ftt = fsr.cexc = 0 6682715Sstever@eecs.umich.edu Fsr &= ~(7 << 14); 6692715Sstever@eecs.umich.edu Fsr &= ~(0x1F); 6705753Ssteve.reinhardt@amd.com }}); 6715753Ssteve.reinhardt@amd.com 0x06: fnegd({{ 6725753Ssteve.reinhardt@amd.com Frd.udw = Frs2.udw ^ (1ULL << 63); 6732715Sstever@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6744111Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 6755154Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 6764111Sgblack@eecs.umich.edu }}); 6775154Sgblack@eecs.umich.edu 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 6784111Sgblack@eecs.umich.edu 0x09: fabss({{ 6792715Sstever@eecs.umich.edu Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 6802715Sstever@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6812715Sstever@eecs.umich.edu Fsr &= ~(7 << 14); 6822715Sstever@eecs.umich.edu Fsr &= ~(0x1F); 6835154Sgblack@eecs.umich.edu }}); 6842715Sstever@eecs.umich.edu 0x0A: fabsd({{ 6855753Ssteve.reinhardt@amd.com Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 6862715Sstever@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 6872715Sstever@eecs.umich.edu Fsr &= ~(7 << 14); 6882715Sstever@eecs.umich.edu Fsr &= ~(0x1F); 6894157Sgblack@eecs.umich.edu }}); 6905874Sgblack@eecs.umich.edu 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 6915874Sgblack@eecs.umich.edu 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); 6924166Sgblack@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 6934157Sgblack@eecs.umich.edu 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 6945753Ssteve.reinhardt@amd.com 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 6955753Ssteve.reinhardt@amd.com 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 6965753Ssteve.reinhardt@amd.com 0x43: Trap::faddq({{fault = new FpDisabled;}}); 6974166Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 6985874Sgblack@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 6995955Sgblack@eecs.umich.edu 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 7005874Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 7015955Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 7025874Sgblack@eecs.umich.edu 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 7034166Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 7045753Ssteve.reinhardt@amd.com 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 7054157Sgblack@eecs.umich.edu 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 7064157Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 7074157Sgblack@eecs.umich.edu 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 7082715Sstever@eecs.umich.edu 0x81: fstox({{ 7092715Sstever@eecs.umich.edu Frd.df = (double)static_cast<int64_t>(Frs2s.sf); 7102715Sstever@eecs.umich.edu }}); 7112715Sstever@eecs.umich.edu 0x82: fdtox({{ 7125753Ssteve.reinhardt@amd.com Frd.df = (double)static_cast<int64_t>(Frs2.df); 7135753Ssteve.reinhardt@amd.com }}); 7145753Ssteve.reinhardt@amd.com 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 7152715Sstever@eecs.umich.edu 0x84: fxtos({{ 7165154Sgblack@eecs.umich.edu Frds.sf = static_cast<float>((int64_t)Frs2.df); 7172715Sstever@eecs.umich.edu }}); 7182715Sstever@eecs.umich.edu 0x88: fxtod({{ 7192715Sstever@eecs.umich.edu Frd.df = static_cast<double>((int64_t)Frs2.df); 7202715Sstever@eecs.umich.edu }}); 7212715Sstever@eecs.umich.edu 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 7225335Shines@cs.fsu.edu 0xC4: fitos({{ 72310037SARM gem5 Developers Frds.sf = static_cast<float>((int32_t)Frs2s.sf); 72410037SARM gem5 Developers }}); 72510037SARM gem5 Developers 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 7265335Shines@cs.fsu.edu 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 7275335Shines@cs.fsu.edu 0xC8: fitod({{ 7285753Ssteve.reinhardt@amd.com Frd.df = static_cast<double>((int32_t)Frs2s.sf); 7295753Ssteve.reinhardt@amd.com }}); 7305753Ssteve.reinhardt@amd.com 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 7315335Shines@cs.fsu.edu 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 73210037SARM gem5 Developers 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 73310037SARM gem5 Developers 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 73410037SARM gem5 Developers 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 73510037SARM gem5 Developers 0xD1: fstoi({{ 73610037SARM gem5 Developers Frds.sf = (float)static_cast<int32_t>(Frs2s.sf); 73710037SARM gem5 Developers }}); 73810037SARM gem5 Developers 0xD2: fdtoi({{ 7395335Shines@cs.fsu.edu Frds.sf = (float)static_cast<int32_t>(Frs2.df); 74010810Sbr@bsdpad.com }}); 74110810Sbr@bsdpad.com 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 74210810Sbr@bsdpad.com default: Trap::fpop1({{fault = new FpDisabled;}}); 74310810Sbr@bsdpad.com } 74410810Sbr@bsdpad.com } 74510810Sbr@bsdpad.com 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 74610810Sbr@bsdpad.com //This used to be just impdep1, but now it's a whole bunch 74710810Sbr@bsdpad.com //of instructions 74810810Sbr@bsdpad.com 0x36: decode OPF{ 7496392Ssaidi@eecs.umich.edu 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 7506392Ssaidi@eecs.umich.edu 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 7516392Ssaidi@eecs.umich.edu 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 7525335Shines@cs.fsu.edu 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 7535335Shines@cs.fsu.edu 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 7545335Shines@cs.fsu.edu 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 7556691Stjones1@inf.ed.ac.uk 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 7566691Stjones1@inf.ed.ac.uk 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 7576691Stjones1@inf.ed.ac.uk 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 7586691Stjones1@inf.ed.ac.uk 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 7596691Stjones1@inf.ed.ac.uk 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 7606691Stjones1@inf.ed.ac.uk 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 7616691Stjones1@inf.ed.ac.uk 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 7626691Stjones1@inf.ed.ac.uk 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 7636691Stjones1@inf.ed.ac.uk 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 7646691Stjones1@inf.ed.ac.uk 0x18: BasicOperate::alignaddr({{ 7656691Stjones1@inf.ed.ac.uk uint64_t sum = Rs1 + Rs2; 7666691Stjones1@inf.ed.ac.uk Rd = sum & ~7; 7676691Stjones1@inf.ed.ac.uk Gsr = (Gsr & ~7) | (sum & 7); 7686691Stjones1@inf.ed.ac.uk }}); 7692715Sstever@eecs.umich.edu 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 7702715Sstever@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 7712715Sstever@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 7722715Sstever@eecs.umich.edu Rd = sum & ~7; 7732715Sstever@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 7742715Sstever@eecs.umich.edu }}); 7752715Sstever@eecs.umich.edu 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 7762715Sstever@eecs.umich.edu 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 7772715Sstever@eecs.umich.edu 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 7784762Snate@binkert.org 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 7794762Snate@binkert.org 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 7802715Sstever@eecs.umich.edu 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 7815154Sgblack@eecs.umich.edu 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 7822715Sstever@eecs.umich.edu 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 783 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 784 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 785 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 786 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 787 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 788 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 789 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 790 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 791 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 792 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 793 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 794 0x48: BasicOperate::faligndata({{ 795 uint64_t msbX = Frs1.udw; 796 uint64_t lsbX = Frs2.udw; 797 //Some special cases need to be split out, first 798 //because they're the most likely to be used, and 799 //second because otherwise, we end up shifting by 800 //greater than the width of the type being shifted, 801 //namely 64, which produces undefined results according 802 //to the C standard. 803 switch(Gsr<2:0>) 804 { 805 case 0: 806 Frd.udw = msbX; 807 break; 808 case 8: 809 Frd.udw = lsbX; 810 break; 811 default: 812 uint64_t msbShift = Gsr<2:0> * 8; 813 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 814 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 815 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 816 Frd.udw = ((msbX & msbMask) << msbShift) | 817 ((lsbX & lsbMask) >> lsbShift); 818 } 819 }}); 820 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 821 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 822 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 823 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 824 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 825 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 826 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 827 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 828 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 829 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 830 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 831 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 832 0x61: BasicOperate::fzeros({{Frds.sf = 0;}}); 833 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 834 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 835 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 836 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 837 0x66: BasicOperate::fnot2({{ 838 Frd.df = (double)(~((uint64_t)Frs2.df)); 839 }}); 840 0x67: BasicOperate::fnot2s({{ 841 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 842 }}); 843 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 844 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 845 0x6A: BasicOperate::fnot1({{ 846 Frd.df = (double)(~((uint64_t)Frs1.df)); 847 }}); 848 0x6B: BasicOperate::fnot1s({{ 849 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 850 }}); 851 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 852 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 853 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 854 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 855 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 856 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 857 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 858 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 859 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); 860 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); 861 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 862 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 863 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); 864 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); 865 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 866 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 867 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 868 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 869 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 870 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 871 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 872 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 873 } 874 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 875 0x38: Branch::jmpl({{ 876 Addr target = Rs1 + Rs2_or_imm13; 877 if(target & 0x3) 878 fault = new MemAddressNotAligned; 879 else 880 { 881 Rd = xc->readPC(); 882 NNPC = target; 883 } 884 }}); 885 0x39: Branch::return({{ 886 Addr target = Rs1 + Rs2_or_imm13; 887 if(fault == NoFault) 888 { 889 //Check for fills which are higher priority than alignment 890 //faults. 891 if(Canrestore == 0) 892 { 893 if(Otherwin) 894 fault = new FillNOther(Wstate<5:3>); 895 else 896 fault = new FillNNormal(Wstate<2:0>); 897 } 898 //Check for alignment faults 899 else if(target & 0x3) 900 fault = new MemAddressNotAligned; 901 else 902 { 903 NNPC = target; 904 Cwp = (Cwp - 1 + NWindows) % NWindows; 905 Cansave = Cansave + 1; 906 Canrestore = Canrestore - 1; 907 } 908 } 909 }}); 910 0x3A: decode CC 911 { 912 0x0: Trap::tcci({{ 913 if(passesCondition(Ccr<3:0>, COND2)) 914 { 915#if FULL_SYSTEM 916 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 917 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 918 fault = new TrapInstruction(lTrapNum); 919#else 920 DPRINTF(Sparc, "The syscall number is %d\n", R1); 921 xc->syscall(R1); 922#endif 923 } 924 }}, IsSerializeAfter, IsNonSpeculative); 925 0x2: Trap::tccx({{ 926 if(passesCondition(Ccr<7:4>, COND2)) 927 { 928#if FULL_SYSTEM 929 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 930 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 931 fault = new TrapInstruction(lTrapNum); 932#else 933 DPRINTF(Sparc, "The syscall number is %d\n", R1); 934 xc->syscall(R1); 935#endif 936 } 937 }}, IsSerializeAfter, IsNonSpeculative); 938 } 939 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 940 0x3C: save({{ 941 if(Cansave == 0) 942 { 943 if(Otherwin) 944 fault = new SpillNOther(Wstate<5:3>); 945 else 946 fault = new SpillNNormal(Wstate<2:0>); 947 } 948 else if(Cleanwin - Canrestore == 0) 949 { 950 fault = new CleanWindow; 951 } 952 else 953 { 954 Cwp = (Cwp + 1) % NWindows; 955 Rd_next = Rs1 + Rs2_or_imm13; 956 Cansave = Cansave - 1; 957 Canrestore = Canrestore + 1; 958 } 959 }}); 960 0x3D: restore({{ 961 if(Canrestore == 0) 962 { 963 if(Otherwin) 964 fault = new FillNOther(Wstate<5:3>); 965 else 966 fault = new FillNNormal(Wstate<2:0>); 967 } 968 else 969 { 970 Cwp = (Cwp - 1 + NWindows) % NWindows; 971 Rd_prev = Rs1 + Rs2_or_imm13; 972 Cansave = Cansave + 1; 973 Canrestore = Canrestore - 1; 974 } 975 }}); 976 0x3E: decode FCN { 977 0x0: Priv::done({{ 978 if(Tl == 0) 979 return new IllegalInstruction; 980 981 Cwp = Tstate<4:0>; 982 Pstate = Tstate<20:8>; 983 Asi = Tstate<31:24>; 984 Ccr = Tstate<39:32>; 985 Gl = Tstate<42:40>; 986 NPC = Tnpc; 987 NNPC = Tnpc + 4; 988 Tl = Tl - 1; 989 }}); 990 0x1: Priv::retry({{ 991 if(Tl == 0) 992 return new IllegalInstruction; 993 Cwp = Tstate<4:0>; 994 Pstate = Tstate<20:8>; 995 Asi = Tstate<31:24>; 996 Ccr = Tstate<39:32>; 997 Gl = Tstate<42:40>; 998 NPC = Tpc; 999 NNPC = Tnpc; 1000 Tl = Tl - 1; 1001 }}); 1002 } 1003 } 1004 } 1005 0x3: decode OP3 { 1006 format Load { 1007 0x00: lduw({{Rd = Mem.uw;}}); 1008 0x01: ldub({{Rd = Mem.ub;}}); 1009 0x02: lduh({{Rd = Mem.uhw;}}); 1010 0x03: ldd({{ 1011 uint64_t val = Mem.udw; 1012 RdLow = val<31:0>; 1013 RdHigh = val<63:32>; 1014 }}); 1015 } 1016 format Store { 1017 0x04: stw({{Mem.uw = Rd.sw;}}); 1018 0x05: stb({{Mem.ub = Rd.sb;}}); 1019 0x06: sth({{Mem.uhw = Rd.shw;}}); 1020 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 1021 } 1022 format Load { 1023 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1024 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1025 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1026 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1027 } 1028 0x0D: LoadStore::ldstub( 1029 {{Rd = Mem.ub;}}, 1030 {{Mem.ub = 0xFF;}}); 1031 0x0E: Store::stx({{Mem.udw = Rd}}); 1032 0x0F: LoadStore::swap( 1033 {{uReg0 = Rd.uw; 1034 Rd.uw = Mem.uw;}}, 1035 {{Mem.uw = uReg0;}}); 1036 format Load { 1037 0x10: lduwa({{Rd = Mem.uw;}}); 1038 0x11: lduba({{Rd = Mem.ub;}}); 1039 0x12: lduha({{Rd = Mem.uhw;}}); 1040 0x13: ldda({{ 1041 uint64_t val = Mem.udw; 1042 RdLow = val<31:0>; 1043 RdHigh = val<63:32>; 1044 }}); 1045 } 1046 format Store { 1047 0x14: stwa({{Mem.uw = Rd;}}); 1048 0x15: stba({{Mem.ub = Rd;}}); 1049 0x16: stha({{Mem.uhw = Rd;}}); 1050 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); 1051 } 1052 format Load { 1053 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1054 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1055 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1056 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 1057 } 1058 0x1D: LoadStore::ldstuba( 1059 {{Rd = Mem.ub;}}, 1060 {{Mem.ub = 0xFF}}); 1061 0x1E: Store::stxa({{Mem.udw = Rd}}); 1062 0x1F: LoadStore::swapa( 1063 {{uReg0 = Rd.uw; 1064 Rd.uw = Mem.uw;}}, 1065 {{Mem.uw = uReg0;}}); 1066 format Trap { 1067 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1068 0x21: decode X { 1069 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1070 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1071 } 1072 0x22: ldqf({{fault = new FpDisabled;}}); 1073 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1074 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1075 0x25: decode X { 1076 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1077 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1078 } 1079 0x26: stqf({{fault = new FpDisabled;}}); 1080 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1081 0x2D: Nop::prefetch({{ }}); 1082 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); 1083 0x32: ldqfa({{fault = new FpDisabled;}}); 1084 format LoadAlt { 1085 0x33: decode EXT_ASI { 1086 //ASI_NUCLEUS 1087 0x04: FailUnimpl::lddfa_n(); 1088 //ASI_NUCLEUS_LITTLE 1089 0x0C: FailUnimpl::lddfa_nl(); 1090 //ASI_AS_IF_USER_PRIMARY 1091 0x10: FailUnimpl::lddfa_aiup(); 1092 //ASI_AS_IF_USER_PRIMARY_LITTLE 1093 0x18: FailUnimpl::lddfa_aiupl(); 1094 //ASI_AS_IF_USER_SECONDARY 1095 0x11: FailUnimpl::lddfa_aius(); 1096 //ASI_AS_IF_USER_SECONDARY_LITTLE 1097 0x19: FailUnimpl::lddfa_aiusl(); 1098 //ASI_REAL 1099 0x14: FailUnimpl::lddfa_real(); 1100 //ASI_REAL_LITTLE 1101 0x1C: FailUnimpl::lddfa_real_l(); 1102 //ASI_REAL_IO 1103 0x15: FailUnimpl::lddfa_real_io(); 1104 //ASI_REAL_IO_LITTLE 1105 0x1D: FailUnimpl::lddfa_real_io_l(); 1106 //ASI_PRIMARY 1107 0x80: FailUnimpl::lddfa_p(); 1108 //ASI_PRIMARY_LITTLE 1109 0x88: FailUnimpl::lddfa_pl(); 1110 //ASI_SECONDARY 1111 0x81: FailUnimpl::lddfa_s(); 1112 //ASI_SECONDARY_LITTLE 1113 0x89: FailUnimpl::lddfa_sl(); 1114 //ASI_PRIMARY_NO_FAULT 1115 0x82: FailUnimpl::lddfa_pnf(); 1116 //ASI_PRIMARY_NO_FAULT_LITTLE 1117 0x8A: FailUnimpl::lddfa_pnfl(); 1118 //ASI_SECONDARY_NO_FAULT 1119 0x83: FailUnimpl::lddfa_snf(); 1120 //ASI_SECONDARY_NO_FAULT_LITTLE 1121 0x8B: FailUnimpl::lddfa_snfl(); 1122 1123 format BlockLoad { 1124 // LDBLOCKF 1125 //ASI_BLOCK_AS_IF_USER_PRIMARY 1126 0x16: FailUnimpl::ldblockf_aiup(); 1127 //ASI_BLOCK_AS_IF_USER_SECONDARY 1128 0x17: FailUnimpl::ldblockf_aius(); 1129 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1130 0x1E: FailUnimpl::ldblockf_aiupl(); 1131 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1132 0x1F: FailUnimpl::ldblockf_aiusl(); 1133 //ASI_BLOCK_PRIMARY 1134 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 1135 //ASI_BLOCK_SECONDARY 1136 0xF1: FailUnimpl::ldblockf_s(); 1137 //ASI_BLOCK_PRIMARY_LITTLE 1138 0xF8: FailUnimpl::ldblockf_pl(); 1139 //ASI_BLOCK_SECONDARY_LITTLE 1140 0xF9: FailUnimpl::ldblockf_sl(); 1141 } 1142 1143 //LDSHORTF 1144 //ASI_FL8_PRIMARY 1145 0xD0: FailUnimpl::ldshortf_8p(); 1146 //ASI_FL8_SECONDARY 1147 0xD1: FailUnimpl::ldshortf_8s(); 1148 //ASI_FL8_PRIMARY_LITTLE 1149 0xD8: FailUnimpl::ldshortf_8pl(); 1150 //ASI_FL8_SECONDARY_LITTLE 1151 0xD9: FailUnimpl::ldshortf_8sl(); 1152 //ASI_FL16_PRIMARY 1153 0xD2: FailUnimpl::ldshortf_16p(); 1154 //ASI_FL16_SECONDARY 1155 0xD3: FailUnimpl::ldshortf_16s(); 1156 //ASI_FL16_PRIMARY_LITTLE 1157 0xDA: FailUnimpl::ldshortf_16pl(); 1158 //ASI_FL16_SECONDARY_LITTLE 1159 0xDB: FailUnimpl::ldshortf_16sl(); 1160 //Not an ASI which is legal with lddfa 1161 default: Trap::lddfa_bad_asi( 1162 {{fault = new DataAccessException;}}); 1163 } 1164 } 1165 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); 1166 0x36: stqfa({{fault = new FpDisabled;}}); 1167 format StoreAlt { 1168 0x37: decode EXT_ASI { 1169 //ASI_NUCLEUS 1170 0x04: FailUnimpl::stdfa_n(); 1171 //ASI_NUCLEUS_LITTLE 1172 0x0C: FailUnimpl::stdfa_nl(); 1173 //ASI_AS_IF_USER_PRIMARY 1174 0x10: FailUnimpl::stdfa_aiup(); 1175 //ASI_AS_IF_USER_PRIMARY_LITTLE 1176 0x18: FailUnimpl::stdfa_aiupl(); 1177 //ASI_AS_IF_USER_SECONDARY 1178 0x11: FailUnimpl::stdfa_aius(); 1179 //ASI_AS_IF_USER_SECONDARY_LITTLE 1180 0x19: FailUnimpl::stdfa_aiusl(); 1181 //ASI_REAL 1182 0x14: FailUnimpl::stdfa_real(); 1183 //ASI_REAL_LITTLE 1184 0x1C: FailUnimpl::stdfa_real_l(); 1185 //ASI_REAL_IO 1186 0x15: FailUnimpl::stdfa_real_io(); 1187 //ASI_REAL_IO_LITTLE 1188 0x1D: FailUnimpl::stdfa_real_io_l(); 1189 //ASI_PRIMARY 1190 0x80: FailUnimpl::stdfa_p(); 1191 //ASI_PRIMARY_LITTLE 1192 0x88: FailUnimpl::stdfa_pl(); 1193 //ASI_SECONDARY 1194 0x81: FailUnimpl::stdfa_s(); 1195 //ASI_SECONDARY_LITTLE 1196 0x89: FailUnimpl::stdfa_sl(); 1197 //ASI_PRIMARY_NO_FAULT 1198 0x82: FailUnimpl::stdfa_pnf(); 1199 //ASI_PRIMARY_NO_FAULT_LITTLE 1200 0x8A: FailUnimpl::stdfa_pnfl(); 1201 //ASI_SECONDARY_NO_FAULT 1202 0x83: FailUnimpl::stdfa_snf(); 1203 //ASI_SECONDARY_NO_FAULT_LITTLE 1204 0x8B: FailUnimpl::stdfa_snfl(); 1205 1206 format BlockStore { 1207 // STBLOCKF 1208 //ASI_BLOCK_AS_IF_USER_PRIMARY 1209 0x16: FailUnimpl::stblockf_aiup(); 1210 //ASI_BLOCK_AS_IF_USER_SECONDARY 1211 0x17: FailUnimpl::stblockf_aius(); 1212 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1213 0x1E: FailUnimpl::stblockf_aiupl(); 1214 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1215 0x1F: FailUnimpl::stblockf_aiusl(); 1216 //ASI_BLOCK_PRIMARY 1217 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 1218 //ASI_BLOCK_SECONDARY 1219 0xF1: FailUnimpl::stblockf_s(); 1220 //ASI_BLOCK_PRIMARY_LITTLE 1221 0xF8: FailUnimpl::stblockf_pl(); 1222 //ASI_BLOCK_SECONDARY_LITTLE 1223 0xF9: FailUnimpl::stblockf_sl(); 1224 } 1225 1226 //STSHORTF 1227 //ASI_FL8_PRIMARY 1228 0xD0: FailUnimpl::stshortf_8p(); 1229 //ASI_FL8_SECONDARY 1230 0xD1: FailUnimpl::stshortf_8s(); 1231 //ASI_FL8_PRIMARY_LITTLE 1232 0xD8: FailUnimpl::stshortf_8pl(); 1233 //ASI_FL8_SECONDARY_LITTLE 1234 0xD9: FailUnimpl::stshortf_8sl(); 1235 //ASI_FL16_PRIMARY 1236 0xD2: FailUnimpl::stshortf_16p(); 1237 //ASI_FL16_SECONDARY 1238 0xD3: FailUnimpl::stshortf_16s(); 1239 //ASI_FL16_PRIMARY_LITTLE 1240 0xDA: FailUnimpl::stshortf_16pl(); 1241 //ASI_FL16_SECONDARY_LITTLE 1242 0xDB: FailUnimpl::stshortf_16sl(); 1243 //Not an ASI which is legal with lddfa 1244 default: Trap::stdfa_bad_asi( 1245 {{fault = new DataAccessException;}}); 1246 } 1247 } 1248 0x3C: Cas::casa( 1249 {{uReg0 = Mem.uw;}}, 1250 {{if(Rs2.uw == uReg0) 1251 Mem.uw = Rd.uw; 1252 else 1253 storeCond = false; 1254 Rd.uw = uReg0;}}); 1255 0x3D: Nop::prefetcha({{ }}); 1256 0x3E: Cas::casxa( 1257 {{uReg0 = Mem.udw;}}, 1258 {{if(Rs2 == uReg0) 1259 Mem.udw = Rd; 1260 else 1261 storeCond = false; 1262 Rd = uReg0;}}); 1263 } 1264 } 1265} 1266