decoder.isa revision 3272
11060SN/A// Copyright (c) 2006 The Regents of The University of Michigan 27944SGiacomo.Gabrielli@arm.com// All rights reserved. 37944SGiacomo.Gabrielli@arm.com// 47944SGiacomo.Gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 57944SGiacomo.Gabrielli@arm.com// modification, are permitted provided that the following conditions are 67944SGiacomo.Gabrielli@arm.com// met: redistributions of source code must retain the above copyright 77944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 87944SGiacomo.Gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 97944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 107944SGiacomo.Gabrielli@arm.com// documentation and/or other materials provided with the distribution; 117944SGiacomo.Gabrielli@arm.com// neither the name of the copyright holders nor the names of its 127944SGiacomo.Gabrielli@arm.com// contributors may be used to endorse or promote products derived from 137944SGiacomo.Gabrielli@arm.com// this software without specific prior written permission. 142702Sktlim@umich.edu// 156973Stjones1@inf.ed.ac.uk// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161060SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171060SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181060SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191060SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201060SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211060SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221060SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231060SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241060SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251060SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261060SN/A// 271060SN/A// Authors: Ali Saidi 281060SN/A// Gabe Black 291060SN/A// Steve Reinhardt 301060SN/A 311060SN/A//////////////////////////////////////////////////////////////////// 321060SN/A// 331060SN/A// The actual decoder specification 341060SN/A// 351060SN/A 361060SN/Adecode OP default Unknown::unknown() 371060SN/A{ 381060SN/A 0x0: decode OP2 391060SN/A { 402665Ssaidi@eecs.umich.edu //Throw an illegal instruction acception 412665Ssaidi@eecs.umich.edu 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 426973Stjones1@inf.ed.ac.uk format BranchN 431060SN/A { 441060SN/A 0x1: decode COND2 451464SN/A { 461464SN/A //Branch Always 471060SN/A 0x8: decode A 482731Sktlim@umich.edu { 492292SN/A 0x0: b(19, {{ 501464SN/A NNPC = xc->readPC() + disp; 511060SN/A }}); 522669Sktlim@umich.edu 0x1: b(19, {{ 537720Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 541060SN/A NNPC = NPC + 4; 551060SN/A }}, ',a'); 561858SN/A } 576658Snate@binkert.org //Branch Never 583770Sgblack@eecs.umich.edu 0x0: decode A 591464SN/A { 601464SN/A 0x0: bn(19, {{ 612669Sktlim@umich.edu NNPC = NNPC;//Don't do anything 621060SN/A }}); 636973Stjones1@inf.ed.ac.uk 0x1: bn(19, {{ 642669Sktlim@umich.edu NPC = xc->readNextPC() + 4; 657678Sgblack@eecs.umich.edu NNPC = NPC + 4; 662292SN/A }}, ',a'); 676023Snate@binkert.org } 681060SN/A default: decode BPCC 691060SN/A { 701060SN/A 0x0: bpcci(19, {{ 711060SN/A if(passesCondition(Ccr<3:0>, COND2)) 721060SN/A NNPC = xc->readPC() + disp; 731060SN/A else 741061SN/A handle_annul 751061SN/A }}); 761060SN/A 0x2: bpccx(19, {{ 771060SN/A if(passesCondition(Ccr<7:4>, COND2)) 781061SN/A NNPC = xc->readPC() + disp; 791060SN/A else 801060SN/A handle_annul 811060SN/A }}); 822733Sktlim@umich.edu } 832733Sktlim@umich.edu } 841060SN/A 0x2: bicc(22, {{ 852292SN/A if(passesCondition(Ccr<3:0>, COND2)) 862107SN/A NNPC = xc->readPC() + disp; 872690Sktlim@umich.edu else 882107SN/A handle_annul 892690Sktlim@umich.edu }}); 902690Sktlim@umich.edu } 911060SN/A 0x3: decode RCOND2 922292SN/A { 932292SN/A format BranchSplit 942292SN/A { 952292SN/A 0x1: bpreq({{ 962292SN/A if(Rs1.sdw == 0) 972292SN/A NNPC = xc->readPC() + disp; 981060SN/A else 995543Ssaidi@eecs.umich.edu handle_annul 1005543Ssaidi@eecs.umich.edu }}); 1011060SN/A 0x2: bprle({{ 1021060SN/A if(Rs1.sdw <= 0) 1032292SN/A NNPC = xc->readPC() + disp; 1042107SN/A else 1051060SN/A handle_annul 1061060SN/A }}); 1071060SN/A 0x3: bprl({{ 1081060SN/A if(Rs1.sdw < 0) 1091060SN/A NNPC = xc->readPC() + disp; 1101060SN/A else 1112292SN/A handle_annul 1121060SN/A }}); 1131060SN/A 0x5: bprne({{ 1145358Sgblack@eecs.umich.edu if(Rs1.sdw != 0) 1155358Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1165358Sgblack@eecs.umich.edu else 1175358Sgblack@eecs.umich.edu handle_annul 1185358Sgblack@eecs.umich.edu }}); 1195358Sgblack@eecs.umich.edu 0x6: bprg({{ 1205358Sgblack@eecs.umich.edu if(Rs1.sdw > 0) 1215358Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 1225358Sgblack@eecs.umich.edu else 1235358Sgblack@eecs.umich.edu handle_annul 1245358Sgblack@eecs.umich.edu }}); 1255358Sgblack@eecs.umich.edu 0x7: bprge({{ 1265358Sgblack@eecs.umich.edu if(Rs1.sdw >= 0) 1272292SN/A NNPC = xc->readPC() + disp; 1282292SN/A else 1292292SN/A handle_annul 1302292SN/A }}); 1312292SN/A } 1322292SN/A } 1332292SN/A //SETHI (or NOP if rd == 0 and imm == 0) 1341060SN/A 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1352132SN/A 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 1361060SN/A 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 1377520Sgblack@eecs.umich.edu } 1387520Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1392292SN/A R15 = xc->readPC(); 1402292SN/A NNPC = R15 + disp; 1412292SN/A }}); 1422292SN/A 0x2: decode OP3 { 1432292SN/A format IntOp { 1442292SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1452292SN/A 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1462292SN/A 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1471060SN/A 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1486973Stjones1@inf.ed.ac.uk 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1496973Stjones1@inf.ed.ac.uk 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1507520Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1517520Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1527520Sgblack@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1536974Stjones1@inf.ed.ac.uk 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1546974Stjones1@inf.ed.ac.uk 0x0A: umul({{ 1556974Stjones1@inf.ed.ac.uk Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1566974Stjones1@inf.ed.ac.uk Y = Rd<63:32>; 1576973Stjones1@inf.ed.ac.uk }}); 1586974Stjones1@inf.ed.ac.uk 0x0B: smul({{ 1596974Stjones1@inf.ed.ac.uk Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 1606973Stjones1@inf.ed.ac.uk Y = Rd.sdw; 1616973Stjones1@inf.ed.ac.uk }}); 1626973Stjones1@inf.ed.ac.uk 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1636973Stjones1@inf.ed.ac.uk 0x0D: udivx({{ 1641060SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1657944SGiacomo.Gabrielli@arm.com else Rd.udw = Rs1.udw / Rs2_or_imm13; 1667944SGiacomo.Gabrielli@arm.com }}); 1677944SGiacomo.Gabrielli@arm.com 0x0E: udiv({{ 1687944SGiacomo.Gabrielli@arm.com if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1697944SGiacomo.Gabrielli@arm.com else 1707944SGiacomo.Gabrielli@arm.com { 1717944SGiacomo.Gabrielli@arm.com Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1727944SGiacomo.Gabrielli@arm.com if(Rd.udw >> 32 != 0) 1737944SGiacomo.Gabrielli@arm.com Rd.udw = 0xFFFFFFFF; 1747944SGiacomo.Gabrielli@arm.com } 1757944SGiacomo.Gabrielli@arm.com }}); 1767944SGiacomo.Gabrielli@arm.com 0x0F: sdiv({{ 1777944SGiacomo.Gabrielli@arm.com if(Rs2_or_imm13.sdw == 0) 1787944SGiacomo.Gabrielli@arm.com fault = new DivisionByZero; 1797944SGiacomo.Gabrielli@arm.com else 1807944SGiacomo.Gabrielli@arm.com { 1817944SGiacomo.Gabrielli@arm.com Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1827944SGiacomo.Gabrielli@arm.com if(Rd.udw<63:31> != 0) 1837944SGiacomo.Gabrielli@arm.com Rd.udw = 0x7FFFFFFF; 1847944SGiacomo.Gabrielli@arm.com else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 1857944SGiacomo.Gabrielli@arm.com Rd.udw = 0xFFFFFFFF80000000ULL; 1867944SGiacomo.Gabrielli@arm.com } 1877944SGiacomo.Gabrielli@arm.com }}); 1881684SN/A } 1891060SN/A format IntOpCc { 1901060SN/A 0x10: addcc({{ 1911060SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1921060SN/A Rd = resTemp = Rs1 + val2;}}, 1932731Sktlim@umich.edu {{(Rs1<31:0> + val2<31:0>)<32:>}}, 1942731Sktlim@umich.edu {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1952731Sktlim@umich.edu {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 1962731Sktlim@umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1972731Sktlim@umich.edu ); 1982731Sktlim@umich.edu 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 1992731Sktlim@umich.edu 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2002731Sktlim@umich.edu 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2012731Sktlim@umich.edu 0x14: subcc({{ 2022731Sktlim@umich.edu int64_t val2 = Rs2_or_imm13; 2032731Sktlim@umich.edu Rd = Rs1 - val2;}}, 2042731Sktlim@umich.edu {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 2052731Sktlim@umich.edu {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 2062731Sktlim@umich.edu {{(~(Rs1<63:1> + (~val2)<63:1> + 2072731Sktlim@umich.edu (Rs1 | ~val2)<0:>))<63:>}}, 2082731Sktlim@umich.edu {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 2092731Sktlim@umich.edu ); 2102731Sktlim@umich.edu 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2112731Sktlim@umich.edu 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2122731Sktlim@umich.edu 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2132731Sktlim@umich.edu 0x18: addccc({{ 2142731Sktlim@umich.edu int64_t resTemp, val2 = Rs2_or_imm13; 2152731Sktlim@umich.edu int64_t carryin = Ccr<0:0>; 2162731Sktlim@umich.edu Rd = resTemp = Rs1 + val2 + carryin;}}, 2172731Sktlim@umich.edu {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 2182292SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2192731Sktlim@umich.edu {{(Rs1<63:1> + val2<63:1> + 2202731Sktlim@umich.edu ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 2211060SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2221060SN/A ); 2236221Snate@binkert.org 0x1A: umulcc({{ 2241060SN/A uint64_t resTemp; 2251060SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2261060SN/A Y = resTemp<63:32>;}}, 2271060SN/A {{0}},{{0}},{{0}},{{0}}); 2282292SN/A 0x1B: smulcc({{ 2292292SN/A int64_t resTemp; 2302292SN/A Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 2312733Sktlim@umich.edu Y = resTemp<63:32>;}}, 2322733Sktlim@umich.edu {{0}},{{0}},{{0}},{{0}}); 2331060SN/A 0x1C: subccc({{ 2342680Sktlim@umich.edu int64_t resTemp, val2 = Rs2_or_imm13; 2352292SN/A int64_t carryin = Ccr<0:0>; 2361060SN/A Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 2371060SN/A {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 2382132SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2391060SN/A {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 2402702Sktlim@umich.edu {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2412669Sktlim@umich.edu ); 2422292SN/A 0x1D: udivxcc({{ 2431060SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2441060SN/A else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 2451060SN/A ,{{0}},{{0}},{{0}},{{0}}); 2468199SAli.Saidi@ARM.com 0x1E: udivcc({{ 2478199SAli.Saidi@ARM.com uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2488199SAli.Saidi@ARM.com int32_t overflow = 0; 2494032Sktlim@umich.edu if(val2 == 0) fault = new DivisionByZero; 2504032Sktlim@umich.edu else 2514032Sktlim@umich.edu { 2521060SN/A resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2531060SN/A overflow = (resTemp<63:32> != 0); 2541060SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 2551060SN/A else Rd = resTemp; 2561060SN/A } }}, 2571060SN/A {{0}}, 2581060SN/A {{overflow}}, 2591060SN/A {{0}}, 2601060SN/A {{0}} 2611060SN/A ); 2621060SN/A 0x1F: sdivcc({{ 2631060SN/A int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2641464SN/A bool overflow = false, underflow = false; 2651464SN/A if(val2 == 0) fault = new DivisionByZero; 2662356SN/A else 2671464SN/A { 2681464SN/A Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2691060SN/A overflow = (Rd<63:31> != 0); 2701464SN/A underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 2711464SN/A if(overflow) Rd = 0x7FFFFFFF; 2721464SN/A else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 2731464SN/A } }}, 2741060SN/A {{0}}, 2753326Sktlim@umich.edu {{overflow || underflow}}, 2763326Sktlim@umich.edu {{0}}, 2773326Sktlim@umich.edu {{0}} 2787597Sminkyu.jeong@arm.com ); 2797597Sminkyu.jeong@arm.com 0x20: taddcc({{ 2807597Sminkyu.jeong@arm.com int64_t resTemp, val2 = Rs2_or_imm13; 2813965Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + val2; 2827720Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2837720Sgblack@eecs.umich.edu {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2841060SN/A {{overflow}}, 2857720Sgblack@eecs.umich.edu {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2867720Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2874636Sgblack@eecs.umich.edu ); 2883794Sgblack@eecs.umich.edu 0x21: tsubcc({{ 2893794Sgblack@eecs.umich.edu int64_t resTemp, val2 = Rs2_or_imm13; 2903794Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + val2; 2913965Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2923965Sgblack@eecs.umich.edu {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 2932292SN/A {{overflow}}, 2942292SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2952292SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2962292SN/A ); 2972292SN/A 0x22: taddcctv({{ 2982292SN/A int64_t val2 = Rs2_or_imm13; 2991060SN/A Rd = Rs1 + val2; 3001060SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || 3011060SN/A (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 3023770Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow;}}, 3033770Sgblack@eecs.umich.edu {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 3043770Sgblack@eecs.umich.edu {{overflow}}, 3053770Sgblack@eecs.umich.edu {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3063770Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 3073770Sgblack@eecs.umich.edu ); 3083770Sgblack@eecs.umich.edu 0x23: tsubcctv({{ 3093770Sgblack@eecs.umich.edu int64_t resTemp, val2 = Rs2_or_imm13; 3103770Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + val2; 3113770Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 3123770Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow;}}, 3133770Sgblack@eecs.umich.edu {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 3143770Sgblack@eecs.umich.edu {{overflow}}, 3153770Sgblack@eecs.umich.edu {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3163770Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3173770Sgblack@eecs.umich.edu ); 3183770Sgblack@eecs.umich.edu 0x24: mulscc({{ 3193770Sgblack@eecs.umich.edu int64_t resTemp, multiplicand = Rs2_or_imm13; 3203770Sgblack@eecs.umich.edu int32_t multiplier = Rs1<31:0>; 3213770Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 3223770Sgblack@eecs.umich.edu multiplier = multiplier<31:1> | 3233770Sgblack@eecs.umich.edu ((Ccr<3:3> 3243770Sgblack@eecs.umich.edu ^ Ccr<1:1>) << 32); 3253770Sgblack@eecs.umich.edu if(!Y<0:>) 3263770Sgblack@eecs.umich.edu multiplicand = 0; 3273770Sgblack@eecs.umich.edu Rd = resTemp = multiplicand + multiplier; 3281060SN/A Y = Y<31:1> | (savedLSB << 31);}}, 3293770Sgblack@eecs.umich.edu {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 3303770Sgblack@eecs.umich.edu {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 3313770Sgblack@eecs.umich.edu {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 3323770Sgblack@eecs.umich.edu {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 3333770Sgblack@eecs.umich.edu ); 3343770Sgblack@eecs.umich.edu } 3353770Sgblack@eecs.umich.edu format IntOp 3363770Sgblack@eecs.umich.edu { 3373770Sgblack@eecs.umich.edu 0x25: decode X { 3383770Sgblack@eecs.umich.edu 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3393770Sgblack@eecs.umich.edu 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3403770Sgblack@eecs.umich.edu } 3413770Sgblack@eecs.umich.edu 0x26: decode X { 3423770Sgblack@eecs.umich.edu 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3433770Sgblack@eecs.umich.edu 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3443770Sgblack@eecs.umich.edu } 3453770Sgblack@eecs.umich.edu 0x27: decode X { 3463770Sgblack@eecs.umich.edu 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3473770Sgblack@eecs.umich.edu 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3483770Sgblack@eecs.umich.edu } 3493770Sgblack@eecs.umich.edu // XXX might want a format rdipr thing here 3503770Sgblack@eecs.umich.edu 0x28: decode RS1 { 3513770Sgblack@eecs.umich.edu 0xF: decode I { 3523770Sgblack@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}); 3533770Sgblack@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}); 3543770Sgblack@eecs.umich.edu } 3553770Sgblack@eecs.umich.edu default: rdasr({{ 3563770Sgblack@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 3573770Sgblack@eecs.umich.edu }}); 3583770Sgblack@eecs.umich.edu } 3593770Sgblack@eecs.umich.edu 0x29: HPriv::rdhpr({{ 3603770Sgblack@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 3613770Sgblack@eecs.umich.edu // access 3623770Sgblack@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 3633770Sgblack@eecs.umich.edu }}); 3643770Sgblack@eecs.umich.edu 0x2A: Priv::rdpr({{ 3653770Sgblack@eecs.umich.edu // XXX Need to protect with format that traps non-priv 3663770Sgblack@eecs.umich.edu // access 3673770Sgblack@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 3683770Sgblack@eecs.umich.edu }}); 3693770Sgblack@eecs.umich.edu 0x2B: BasicOperate::flushw({{ 3703770Sgblack@eecs.umich.edu if(NWindows - 2 - Cansave == 0) 3713770Sgblack@eecs.umich.edu { 3723770Sgblack@eecs.umich.edu if(Otherwin) 3733770Sgblack@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 3743770Sgblack@eecs.umich.edu else 3753770Sgblack@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 3763770Sgblack@eecs.umich.edu } 3773770Sgblack@eecs.umich.edu }}); 3783770Sgblack@eecs.umich.edu 0x2C: decode MOVCC3 3793770Sgblack@eecs.umich.edu { 3803770Sgblack@eecs.umich.edu 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 3813770Sgblack@eecs.umich.edu 0x1: decode CC 3823770Sgblack@eecs.umich.edu { 3833770Sgblack@eecs.umich.edu 0x0: movcci({{ 3843770Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 3853770Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 3863770Sgblack@eecs.umich.edu else 3873770Sgblack@eecs.umich.edu Rd = Rd; 3883770Sgblack@eecs.umich.edu }}); 3893770Sgblack@eecs.umich.edu 0x2: movccx({{ 3903770Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 3913770Sgblack@eecs.umich.edu Rd = Rs2_or_imm11; 3923770Sgblack@eecs.umich.edu else 3933770Sgblack@eecs.umich.edu Rd = Rd; 3943770Sgblack@eecs.umich.edu }}); 3953770Sgblack@eecs.umich.edu } 3963770Sgblack@eecs.umich.edu } 3973770Sgblack@eecs.umich.edu 0x2D: sdivx({{ 3983770Sgblack@eecs.umich.edu if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 3993770Sgblack@eecs.umich.edu else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4004636Sgblack@eecs.umich.edu }}); 4014636Sgblack@eecs.umich.edu 0x2E: decode RS1 { 4027720Sgblack@eecs.umich.edu 0x0: IntOp::popc({{ 4037720Sgblack@eecs.umich.edu int64_t count = 0; 4044636Sgblack@eecs.umich.edu uint64_t temp = Rs2_or_imm13; 4054636Sgblack@eecs.umich.edu //Count the 1s in the front 4bits until none are left 4064636Sgblack@eecs.umich.edu uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 4077720Sgblack@eecs.umich.edu while(temp) 4087720Sgblack@eecs.umich.edu { 4093770Sgblack@eecs.umich.edu count += oneBits[temp & 0xF]; 4102292SN/A temp = temp >> 4; 4112292SN/A } 4127720Sgblack@eecs.umich.edu Rd = count; 4137720Sgblack@eecs.umich.edu }}); 4142292SN/A } 4152292SN/A 0x2F: decode RCOND3 4162292SN/A { 4177720Sgblack@eecs.umich.edu 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4187720Sgblack@eecs.umich.edu 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4191060SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4202292SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4212292SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4222292SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4232107SN/A } 4241060SN/A 0x30: wrasr({{ 4251060SN/A xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 4261060SN/A }}); 4271060SN/A 0x31: decode FCN { 4281464SN/A 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 4291684SN/A 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 4301464SN/A } 4311060SN/A 0x32: Priv::wrpr({{ 4321464SN/A // XXX Need to protect with format that traps non-priv 4331060SN/A // access 4341060SN/A fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 4351060SN/A }}); 4361060SN/A 0x33: HPriv::wrhpr({{ 4371060SN/A // XXX Need to protect with format that traps non-priv/priv 4381060SN/A // access 4393326Sktlim@umich.edu fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 4405712Shsul@eecs.umich.edu }}); 4413326Sktlim@umich.edu 0x34: decode OPF{ 4425714Shsul@eecs.umich.edu format BasicOperate{ 4435714Shsul@eecs.umich.edu 0x01: fmovs({{ 4445714Shsul@eecs.umich.edu Frd.uw = Frs2.uw; 4451060SN/A //fsr.ftt = fsr.cexc = 0 4462132SN/A Fsr &= ~(7 << 14); 4471060SN/A Fsr &= ~(0x1F); 4481060SN/A }}); 4491060SN/A 0x02: fmovd({{ 4501060SN/A Frd.udw = Frs2.udw; 4512292SN/A //fsr.ftt = fsr.cexc = 0 4521060SN/A Fsr &= ~(7 << 14); 4531060SN/A Fsr &= ~(0x1F); 4541060SN/A }}); 4557720Sgblack@eecs.umich.edu 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 4567720Sgblack@eecs.umich.edu 0x05: fnegs({{ 4573965Sgblack@eecs.umich.edu Frd.uw = Frs2.uw ^ (1UL << 31); 4587720Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4593965Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4602935Sksewell@umich.edu Fsr &= ~(0x1F); 4617720Sgblack@eecs.umich.edu }}); 4621060SN/A 0x06: fnegd({{ 4633794Sgblack@eecs.umich.edu Frd.udw = Frs2.udw ^ (1ULL << 63); 4647720Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4653794Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4663794Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4677720Sgblack@eecs.umich.edu }}); 4681060SN/A 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 4694636Sgblack@eecs.umich.edu 0x09: fabss({{ 4707720Sgblack@eecs.umich.edu Frd.uw = ((1UL << 31) - 1) & Frs2.uw; 4714636Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4721060SN/A Fsr &= ~(7 << 14); 4733794Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4743794Sgblack@eecs.umich.edu }}); 4753794Sgblack@eecs.umich.edu 0x0A: fabsd({{ 4763794Sgblack@eecs.umich.edu Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 4773794Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4783794Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4793794Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4803794Sgblack@eecs.umich.edu }}); 4813794Sgblack@eecs.umich.edu 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 4821060SN/A 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}}); 4831060SN/A 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 4842935Sksewell@umich.edu 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 4853794Sgblack@eecs.umich.edu 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}}); 4867720Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 4877720Sgblack@eecs.umich.edu 0x43: Trap::faddq({{fault = new FpDisabled;}}); 4887720Sgblack@eecs.umich.edu 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}}); 4893794Sgblack@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 4903794Sgblack@eecs.umich.edu 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 4911060SN/A 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}}); 4921060SN/A 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 4931060SN/A 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 4945543Ssaidi@eecs.umich.edu 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}}); 4955543Ssaidi@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 4965543Ssaidi@eecs.umich.edu 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 4975543Ssaidi@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}}); 4982336SN/A 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 4992336SN/A 0x81: fstox({{ 5001060SN/A Frd.df = (double)static_cast<int64_t>(Frs2.sf); 5011060SN/A }}); 5021060SN/A 0x82: fdtox({{ 5035543Ssaidi@eecs.umich.edu Frd.df = (double)static_cast<int64_t>(Frs2.df); 5045543Ssaidi@eecs.umich.edu }}); 5055543Ssaidi@eecs.umich.edu 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 5065543Ssaidi@eecs.umich.edu 0x84: fxtos({{ 5075543Ssaidi@eecs.umich.edu Frd.sf = static_cast<float>((int64_t)Frs2.df); 5085543Ssaidi@eecs.umich.edu }}); 5091060SN/A 0x88: fxtod({{ 5105543Ssaidi@eecs.umich.edu Frd.df = static_cast<double>((int64_t)Frs2.df); 5115543Ssaidi@eecs.umich.edu }}); 5122935Sksewell@umich.edu 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 5131060SN/A 0xC4: fitos({{ 5141060SN/A Frd.sf = static_cast<float>((int32_t)Frs2.sf); 5152292SN/A }}); 5162731Sktlim@umich.edu 0xC6: fdtos({{Frd.sf = Frs2.df;}}); 5172292SN/A 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 5182731Sktlim@umich.edu 0xC8: fitod({{ 5197784SAli.Saidi@ARM.com Frd.df = static_cast<double>((int32_t)Frs2.sf); 5201060SN/A }}); 5211060SN/A 0xC9: fstod({{Frd.df = Frs2.sf;}}); 5221060SN/A 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 5232292SN/A 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 5242336SN/A 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 5252308SN/A 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 5264828Sgblack@eecs.umich.edu 0xD1: fstoi({{ 5274654Sgblack@eecs.umich.edu Frd.sf = (float)static_cast<int32_t>(Frs2.sf); 5284654Sgblack@eecs.umich.edu }}); 5294636Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 5304654Sgblack@eecs.umich.edu Frd.sf = (float)static_cast<int32_t>(Frs2.df); 5314654Sgblack@eecs.umich.edu }}); 5324636Sgblack@eecs.umich.edu 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 5332292SN/A default: Trap::fpop1({{fault = new FpDisabled;}}); 5342292SN/A } 5352731Sktlim@umich.edu } 5362292SN/A 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 5372292SN/A //This used to be just impdep1, but now it's a whole bunch 5382731Sktlim@umich.edu //of instructions 5392292SN/A 0x36: decode OPF{ 5402292SN/A 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 5412731Sktlim@umich.edu 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 5422292SN/A 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 5432292SN/A 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 5442731Sktlim@umich.edu 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 5452292SN/A 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 5462292SN/A 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 5472731Sktlim@umich.edu 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 5482292SN/A 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 5492292SN/A 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 5502731Sktlim@umich.edu 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 5512292SN/A 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 5522731Sktlim@umich.edu 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 5532731Sktlim@umich.edu 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 5542292SN/A 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 5552292SN/A 0x18: BasicOperate::alignaddr({{ 5562292SN/A uint64_t sum = Rs1 + Rs2; 5572292SN/A Rd = sum & ~7; 5582292SN/A Gsr = (Gsr & ~7) | (sum & 7); 5592292SN/A }}); 5602731Sktlim@umich.edu 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 5611060SN/A 0x1A: BasicOperate::alignaddresslittle({{ 5621464SN/A uint64_t sum = Rs1 + Rs2; 5631464SN/A Rd = sum & ~7; 5641464SN/A Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 5651464SN/A }}); 5667720Sgblack@eecs.umich.edu 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 5677720Sgblack@eecs.umich.edu 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 5681464SN/A 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 5692292SN/A 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 5705543Ssaidi@eecs.umich.edu 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 5711684SN/A 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 5722292SN/A 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 5731060SN/A 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 5741060SN/A 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 5751060SN/A 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 5761060SN/A 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 5771060SN/A 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 5781060SN/A 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 5791060SN/A 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 5801060SN/A 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 5812292SN/A 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 5821060SN/A 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 5831060SN/A 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 5842292SN/A 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 5851060SN/A 0x48: BasicOperate::faligndata({{ 5861684SN/A uint64_t msbX = Frs1.udw; 5871464SN/A uint64_t lsbX = Frs2.udw; 5881684SN/A //Some special cases need to be split out, first 5891684SN/A //because they're the most likely to be used, and 5902356SN/A //second because otherwise, we end up shifting by 5911684SN/A //greater than the width of the type being shifted, 5921684SN/A //namely 64, which produces undefined results according 5931464SN/A //to the C standard. 5941060SN/A switch(Gsr<2:0>) 5952702Sktlim@umich.edu { 5963735Sstever@eecs.umich.edu case 0: 5971060SN/A Frd.udw = msbX; 5983326Sktlim@umich.edu break; 5993326Sktlim@umich.edu case 8: 6001060SN/A Frd.udw = lsbX; 6011060SN/A break; 6022702Sktlim@umich.edu default: 6033735Sstever@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 6043735Sstever@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 6052690Sktlim@umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 6063326Sktlim@umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 6073326Sktlim@umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 6083326Sktlim@umich.edu ((lsbX & lsbMask) >> lsbShift); 6093326Sktlim@umich.edu } 6103326Sktlim@umich.edu }}); 6113326Sktlim@umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 6123326Sktlim@umich.edu 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 6133326Sktlim@umich.edu 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 6142690Sktlim@umich.edu 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 6152690Sktlim@umich.edu 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 6162702Sktlim@umich.edu 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 6173735Sstever@eecs.umich.edu 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 6181060SN/A 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 6193326Sktlim@umich.edu 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 6203326Sktlim@umich.edu 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 6212308SN/A 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 6221060SN/A 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 6232702Sktlim@umich.edu 0x61: BasicOperate::fzeros({{Frd.sf = 0;}}); 6243735Sstever@eecs.umich.edu 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 6253735Sstever@eecs.umich.edu 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 6262308SN/A 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 6273326Sktlim@umich.edu 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 6283326Sktlim@umich.edu 0x66: BasicOperate::fnot2({{ 6292308SN/A Frd.df = (double)(~((uint64_t)Frs2.df)); 6301060SN/A }}); 6312702Sktlim@umich.edu 0x67: BasicOperate::fnot2s({{ 6323735Sstever@eecs.umich.edu Frd.sf = (float)(~((uint32_t)Frs2.sf)); 6332308SN/A }}); 6343326Sktlim@umich.edu 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 6353326Sktlim@umich.edu 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 6361060SN/A 0x6A: BasicOperate::fnot1({{ 6371060SN/A Frd.df = (double)(~((uint64_t)Frs1.df)); 6382190SN/A }}); 6392292SN/A 0x6B: BasicOperate::fnot1s({{ 6402190SN/A Frd.sf = (float)(~((uint32_t)Frs1.sf)); 6412331SN/A }}); 6422292SN/A 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 6432190SN/A 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 6441684SN/A 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 6451464SN/A 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 6461464SN/A 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 6471464SN/A 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 6481464SN/A 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 6491464SN/A 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 6501684SN/A 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); 6512731Sktlim@umich.edu 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); 6521464SN/A 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 6532292SN/A 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 6542731Sktlim@umich.edu 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); 6551464SN/A 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); 6562731Sktlim@umich.edu 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 6572731Sktlim@umich.edu 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 6582308SN/A 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 6592731Sktlim@umich.edu 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 6602731Sktlim@umich.edu 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 6612308SN/A 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 6621060SN/A 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 6632731Sktlim@umich.edu 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 6641060SN/A } 6651060SN/A 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 6662731Sktlim@umich.edu 0x38: Branch::jmpl({{ 6671060SN/A Addr target = Rs1 + Rs2_or_imm13; 6684032Sktlim@umich.edu if(target & 0x3) 6694032Sktlim@umich.edu fault = new MemAddressNotAligned; 6704032Sktlim@umich.edu else 6711060SN/A { 6722731Sktlim@umich.edu Rd = xc->readPC(); 6731060SN/A NNPC = target; 6741060SN/A } 6752731Sktlim@umich.edu }}); 6761060SN/A 0x39: Branch::return({{ 6774032Sktlim@umich.edu //If both MemAddressNotAligned and 6784032Sktlim@umich.edu //a fill trap happen, it's not clear 6794032Sktlim@umich.edu //which one should be returned. 6801060SN/A Addr target = Rs1 + Rs2_or_imm13; 6812731Sktlim@umich.edu if(target & 0x3) 6821060SN/A fault = new MemAddressNotAligned; 6831060SN/A else 6842731Sktlim@umich.edu NNPC = target; 6851060SN/A if(fault == NoFault) 6861060SN/A { 6872731Sktlim@umich.edu //CWP should be set directly so that it always happens 6881060SN/A //Also, this will allow writing to the new window and 6891061SN/A //reading from the old one 6902731Sktlim@umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 6911061SN/A if(Canrestore == 0) 6921060SN/A { 6932731Sktlim@umich.edu if(Otherwin) 6942731Sktlim@umich.edu fault = new FillNOther(Wstate<5:3>); 6952731Sktlim@umich.edu else 6962731Sktlim@umich.edu fault = new FillNNormal(Wstate<2:0>); 6972731Sktlim@umich.edu } 6981060SN/A else 6992292SN/A { 7002731Sktlim@umich.edu Rd = Rs1 + Rs2_or_imm13; 7012292SN/A Cansave = Cansave + 1; 7022292SN/A Canrestore = Canrestore - 1; 7032731Sktlim@umich.edu } 7042292SN/A //This is here to make sure the CWP is written 7051060SN/A //no matter what. This ensures that the results 7062731Sktlim@umich.edu //are written in the new window as well. 7071060SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7081060SN/A } 7092731Sktlim@umich.edu }}); 7101060SN/A 0x3A: decode CC 7112292SN/A { 7122292SN/A 0x0: Trap::tcci({{ 7132292SN/A if(passesCondition(Ccr<3:0>, COND2)) 7142731Sktlim@umich.edu { 7152292SN/A#if FULL_SYSTEM 7162292SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 7172731Sktlim@umich.edu DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 7182731Sktlim@umich.edu fault = new TrapInstruction(lTrapNum); 7192731Sktlim@umich.edu#else 7202731Sktlim@umich.edu DPRINTF(Sparc, "The syscall number is %d\n", R1); 7212292SN/A xc->syscall(R1); 7221060SN/A#endif 7232731Sktlim@umich.edu } 7241060SN/A }}); 7251060SN/A 0x2: Trap::tccx({{ 7262731Sktlim@umich.edu if(passesCondition(Ccr<7:4>, COND2)) 7272292SN/A { 7282292SN/A#if FULL_SYSTEM 7292292SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 7302292SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 7312292SN/A fault = new TrapInstruction(lTrapNum); 7322731Sktlim@umich.edu#else 7332292SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 7342292SN/A xc->syscall(R1); 7352731Sktlim@umich.edu#endif 7362731Sktlim@umich.edu } 7372731Sktlim@umich.edu }}); 7382731Sktlim@umich.edu } 7392292SN/A 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 7402292SN/A 0x3C: save({{ 7412731Sktlim@umich.edu //CWP should be set directly so that it always happens 7422292SN/A //Also, this will allow writing to the new window and 7432292SN/A //reading from the old one 7442731Sktlim@umich.edu if(Cansave == 0) 7452292SN/A { 7462292SN/A if(Otherwin) 7472292SN/A fault = new SpillNOther(Wstate<5:3>); 7482292SN/A else 7492292SN/A fault = new SpillNNormal(Wstate<2:0>); 7502731Sktlim@umich.edu Cwp = (Cwp + 2) % NWindows; 7512292SN/A } 7522292SN/A else if(Cleanwin - Canrestore == 0) 7532731Sktlim@umich.edu { 7542731Sktlim@umich.edu Cwp = (Cwp + 1) % NWindows; 7552731Sktlim@umich.edu fault = new CleanWindow; 7562731Sktlim@umich.edu } 7572292SN/A else 7582292SN/A { 7592731Sktlim@umich.edu Cwp = (Cwp + 1) % NWindows; 7602292SN/A Rd = Rs1 + Rs2_or_imm13; 7612292SN/A Cansave = Cansave - 1; 7622731Sktlim@umich.edu Canrestore = Canrestore + 1; 7632292SN/A } 7647720Sgblack@eecs.umich.edu //This is here to make sure the CWP is written 7657720Sgblack@eecs.umich.edu //no matter what. This ensures that the results 7667720Sgblack@eecs.umich.edu //are written in the new window as well. 7677720Sgblack@eecs.umich.edu xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7687720Sgblack@eecs.umich.edu }}); 7697720Sgblack@eecs.umich.edu 0x3D: restore({{ 7701060SN/A //CWP should be set directly so that it always happens 7717720Sgblack@eecs.umich.edu //Also, this will allow writing to the new window and 7727720Sgblack@eecs.umich.edu //reading from the old one 7737720Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 7747720Sgblack@eecs.umich.edu if(Canrestore == 0) 7751060SN/A { 7764636Sgblack@eecs.umich.edu if(Otherwin) 7777720Sgblack@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 7784636Sgblack@eecs.umich.edu else 7797597Sminkyu.jeong@arm.com fault = new FillNNormal(Wstate<2:0>); 7807597Sminkyu.jeong@arm.com } 7817597Sminkyu.jeong@arm.com else 7827597Sminkyu.jeong@arm.com { 7837597Sminkyu.jeong@arm.com Rd = Rs1 + Rs2_or_imm13; 7847597Sminkyu.jeong@arm.com Cansave = Cansave + 1; 7857597Sminkyu.jeong@arm.com Canrestore = Canrestore - 1; 7867597Sminkyu.jeong@arm.com } 7877600Sminkyu.jeong@arm.com //This is here to make sure the CWP is written 7887600Sminkyu.jeong@arm.com //no matter what. This ensures that the results 7897600Sminkyu.jeong@arm.com //are written in the new window as well. 7907600Sminkyu.jeong@arm.com xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7917597Sminkyu.jeong@arm.com }}); 7927597Sminkyu.jeong@arm.com 0x3E: decode FCN { 7932702Sktlim@umich.edu 0x0: Priv::done({{ 7942292SN/A if(Tl == 0) 7952292SN/A return new IllegalInstruction; 7962702Sktlim@umich.edu 7976221Snate@binkert.org Cwp = Tstate<4:0>; 7982292SN/A Pstate = Tstate<20:8>; 7992731Sktlim@umich.edu Asi = Tstate<31:24>; 8002702Sktlim@umich.edu Ccr = Tstate<39:32>; 8011060SN/A Gl = Tstate<42:40>; 8022731Sktlim@umich.edu NPC = Tnpc; 8032680Sktlim@umich.edu NNPC = Tnpc + 4; 8041464SN/A Tl = Tl - 1; 8051464SN/A }}); 8061684SN/A 0x1: Priv::retry({{ 8071684SN/A if(Tl == 0) 8081684SN/A return new IllegalInstruction; 8091464SN/A Cwp = Tstate<4:0>; 8102292SN/A Pstate = Tstate<20:8>; 8111684SN/A Asi = Tstate<31:24>; 8121684SN/A Ccr = Tstate<39:32>; 8131684SN/A Gl = Tstate<42:40>; 8141464SN/A NPC = Tpc; 8151464SN/A NNPC = Tnpc + 4; 8164032Sktlim@umich.edu Tl = Tl - 1; 8174032Sktlim@umich.edu }}); 8184032Sktlim@umich.edu } 8194032Sktlim@umich.edu } 8204032Sktlim@umich.edu } 8214032Sktlim@umich.edu 0x3: decode OP3 { 8221464SN/A format Load { 8231684SN/A 0x00: lduw({{Rd = Mem.uw;}}); 8241464SN/A 0x01: ldub({{Rd = Mem.ub;}}); 8251684SN/A 0x02: lduh({{Rd = Mem.uhw;}}); 8261684SN/A 0x03: ldd({{ 8271464SN/A uint64_t val = Mem.udw; 8281684SN/A RdLow = val<31:0>; 8291684SN/A RdHigh = val<63:32>; 8301464SN/A }}); 8311684SN/A } 8321684SN/A format Store { 8331464SN/A 0x04: stw({{Mem.uw = Rd.sw;}}); 8341681SN/A 0x05: stb({{Mem.ub = Rd.sb;}}); 8352292SN/A 0x06: sth({{Mem.uhw = Rd.shw;}}); 8362292SN/A 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 8372292SN/A } 8384032Sktlim@umich.edu format Load { 8394032Sktlim@umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 8404032Sktlim@umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 8414032Sktlim@umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 8424032Sktlim@umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 8434032Sktlim@umich.edu 0x0D: ldstub({{ 8441681SN/A Rd = Mem.ub; 8451684SN/A Mem.ub = 0xFF; 8461681SN/A }}); 8471684SN/A } 8481684SN/A 0x0E: Store::stx({{Mem.udw = Rd}}); 8491681SN/A 0x0F: LoadStore::swap({{ 8502292SN/A uint32_t temp = Rd; 8512292SN/A Rd = Mem.uw; 8522292SN/A Mem.uw = temp; 8532292SN/A }}); 8542292SN/A format Load { 8552292SN/A 0x10: lduwa({{Rd = Mem.uw;}}); 8562292SN/A 0x11: lduba({{Rd = Mem.ub;}}); 8572292SN/A 0x12: lduha({{Rd = Mem.uhw;}}); 8582292SN/A 0x13: ldda({{ 8593326Sktlim@umich.edu uint64_t val = Mem.udw; 8603326Sktlim@umich.edu RdLow = val<31:0>; 8613326Sktlim@umich.edu RdHigh = val<63:32>; 8623326Sktlim@umich.edu }}); 8633326Sktlim@umich.edu } 8643326Sktlim@umich.edu format Store { 8653326Sktlim@umich.edu 0x14: stwa({{Mem.uw = Rd;}}); 8663326Sktlim@umich.edu 0x15: stba({{Mem.ub = Rd;}}); 8673326Sktlim@umich.edu 0x16: stha({{Mem.uhw = Rd;}}); 8681060SN/A 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); 8691060SN/A } 8701060SN/A format Load { 8717520Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 8727520Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 8737520Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 8741060SN/A 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 8754032Sktlim@umich.edu } 8767944SGiacomo.Gabrielli@arm.com 0x1D: LoadStore::ldstuba({{ 8776974Stjones1@inf.ed.ac.uk Rd = Mem.ub; 8786974Stjones1@inf.ed.ac.uk Mem.ub = 0xFF; 8796974Stjones1@inf.ed.ac.uk }}); 8807944SGiacomo.Gabrielli@arm.com 0x1E: Store::stxa({{Mem.udw = Rd}}); 8817944SGiacomo.Gabrielli@arm.com 0x1F: LoadStore::swapa({{ 8827944SGiacomo.Gabrielli@arm.com uint32_t temp = Rd; 8837944SGiacomo.Gabrielli@arm.com Rd = Mem.uw; 8847944SGiacomo.Gabrielli@arm.com Mem.uw = temp; 8857944SGiacomo.Gabrielli@arm.com }}); 8867944SGiacomo.Gabrielli@arm.com format Trap { 8874032Sktlim@umich.edu 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 8887944SGiacomo.Gabrielli@arm.com 0x21: decode X { 8897944SGiacomo.Gabrielli@arm.com 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 8907944SGiacomo.Gabrielli@arm.com 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 8917944SGiacomo.Gabrielli@arm.com } 8927944SGiacomo.Gabrielli@arm.com 0x22: ldqf({{fault = new FpDisabled;}}); 8931060SN/A 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 8941060SN/A 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 8957944SGiacomo.Gabrielli@arm.com 0x25: decode X { 8967944SGiacomo.Gabrielli@arm.com 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 8977944SGiacomo.Gabrielli@arm.com 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 8988199SAli.Saidi@ARM.com } 8997944SGiacomo.Gabrielli@arm.com 0x26: stqf({{fault = new FpDisabled;}}); 9007944SGiacomo.Gabrielli@arm.com 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 9017944SGiacomo.Gabrielli@arm.com 0x2D: Nop::prefetch({{ }}); 9027944SGiacomo.Gabrielli@arm.com 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); 9037944SGiacomo.Gabrielli@arm.com 0x32: ldqfa({{fault = new FpDisabled;}}); 9047944SGiacomo.Gabrielli@arm.com format LoadAlt { 9057944SGiacomo.Gabrielli@arm.com 0x33: decode EXT_ASI { 9067944SGiacomo.Gabrielli@arm.com //ASI_NUCLEUS 9077944SGiacomo.Gabrielli@arm.com 0x04: FailUnimpl::lddfa_n(); 9087944SGiacomo.Gabrielli@arm.com //ASI_NUCLEUS_LITTLE 9097944SGiacomo.Gabrielli@arm.com 0x0C: FailUnimpl::lddfa_nl(); 9107944SGiacomo.Gabrielli@arm.com //ASI_AS_IF_USER_PRIMARY 9117944SGiacomo.Gabrielli@arm.com 0x10: FailUnimpl::lddfa_aiup(); 9127944SGiacomo.Gabrielli@arm.com //ASI_AS_IF_USER_PRIMARY_LITTLE 9137577SAli.Saidi@ARM.com 0x18: FailUnimpl::lddfa_aiupl(); 9147577SAli.Saidi@ARM.com //ASI_AS_IF_USER_SECONDARY 9151060SN/A 0x11: FailUnimpl::lddfa_aius(); 9161060SN/A //ASI_AS_IF_USER_SECONDARY_LITTLE 9171060SN/A 0x19: FailUnimpl::lddfa_aiusl(); 9181060SN/A //ASI_REAL 9191060SN/A 0x14: FailUnimpl::lddfa_real(); 9201060SN/A //ASI_REAL_LITTLE 9211060SN/A 0x1C: FailUnimpl::lddfa_real_l(); 9221060SN/A //ASI_REAL_IO 9231060SN/A 0x15: FailUnimpl::lddfa_real_io(); 9242132SN/A //ASI_REAL_IO_LITTLE 9257520Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 9267520Sgblack@eecs.umich.edu //ASI_PRIMARY 9277520Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 9287520Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 9297520Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 9307520Sgblack@eecs.umich.edu //ASI_SECONDARY 9317520Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 9327520Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 9337520Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 9347520Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 9357520Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 9367520Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 9377520Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 9387520Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 9397520Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 9407520Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 9417520Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 9421060SN/A 9431060SN/A format BlockLoad { 9441060SN/A // LDBLOCKF 9451060SN/A //ASI_BLOCK_AS_IF_USER_PRIMARY 9461060SN/A 0x16: FailUnimpl::ldblockf_aiup(); 9474032Sktlim@umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 9487944SGiacomo.Gabrielli@arm.com 0x17: FailUnimpl::ldblockf_aius(); 9496974Stjones1@inf.ed.ac.uk //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 9506974Stjones1@inf.ed.ac.uk 0x1E: FailUnimpl::ldblockf_aiupl(); 9516974Stjones1@inf.ed.ac.uk //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 9527944SGiacomo.Gabrielli@arm.com 0x1F: FailUnimpl::ldblockf_aiusl(); 9537944SGiacomo.Gabrielli@arm.com //ASI_BLOCK_PRIMARY 9547944SGiacomo.Gabrielli@arm.com 0xF0: ldblockf_p({{Frd_%(micro_pc)d = Mem.udw}}); 9557944SGiacomo.Gabrielli@arm.com //ASI_BLOCK_SECONDARY 9567944SGiacomo.Gabrielli@arm.com 0xF1: FailUnimpl::ldblockf_s(); 9577944SGiacomo.Gabrielli@arm.com //ASI_BLOCK_PRIMARY_LITTLE 9587944SGiacomo.Gabrielli@arm.com 0xF8: FailUnimpl::ldblockf_pl(); 9597944SGiacomo.Gabrielli@arm.com //ASI_BLOCK_SECONDARY_LITTLE 9607944SGiacomo.Gabrielli@arm.com 0xF9: FailUnimpl::ldblockf_sl(); 9617944SGiacomo.Gabrielli@arm.com } 9627944SGiacomo.Gabrielli@arm.com 9637944SGiacomo.Gabrielli@arm.com //LDSHORTF 9647944SGiacomo.Gabrielli@arm.com //ASI_FL8_PRIMARY 9656974Stjones1@inf.ed.ac.uk 0xD0: FailUnimpl::ldshortf_8p(); 9664032Sktlim@umich.edu //ASI_FL8_SECONDARY 9677944SGiacomo.Gabrielli@arm.com 0xD1: FailUnimpl::ldshortf_8s(); 9682678Sktlim@umich.edu //ASI_FL8_PRIMARY_LITTLE 9698199SAli.Saidi@ARM.com 0xD8: FailUnimpl::ldshortf_8pl(); 9704032Sktlim@umich.edu //ASI_FL8_SECONDARY_LITTLE 9716975Stjones1@inf.ed.ac.uk 0xD9: FailUnimpl::ldshortf_8sl(); 9721060SN/A //ASI_FL16_PRIMARY 9731060SN/A 0xD2: FailUnimpl::ldshortf_16p(); 9741060SN/A //ASI_FL16_SECONDARY 9751060SN/A 0xD3: FailUnimpl::ldshortf_16s(); 9761060SN/A //ASI_FL16_PRIMARY_LITTLE 9776973Stjones1@inf.ed.ac.uk 0xDA: FailUnimpl::ldshortf_16pl(); 9787520Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 9797520Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 9807520Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 9817520Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi({{fault = new DataAccessException;}}); 9827520Sgblack@eecs.umich.edu 9837520Sgblack@eecs.umich.edu //LoadAlt::lddfa({{ 9847520Sgblack@eecs.umich.edu //Do the actual loading 9857520Sgblack@eecs.umich.edu //if(fault == NoFault) 9867520Sgblack@eecs.umich.edu //{ 9877520Sgblack@eecs.umich.edu //if(AsiIsBlock(asi)) 9887520Sgblack@eecs.umich.edu //{ 9897520Sgblack@eecs.umich.edu //Do the block transfer 9906973Stjones1@inf.ed.ac.uk //} 9916974Stjones1@inf.ed.ac.uk //else 9926974Stjones1@inf.ed.ac.uk //{ 9936974Stjones1@inf.ed.ac.uk //uint64_t val = Mem; 9946974Stjones1@inf.ed.ac.uk //if(AsiIsLittle(asi)) 9956974Stjones1@inf.ed.ac.uk //val = gtole(val); 9966974Stjones1@inf.ed.ac.uk //Frd.udw = val; 9976974Stjones1@inf.ed.ac.uk //} 9986974Stjones1@inf.ed.ac.uk //} 9996974Stjones1@inf.ed.ac.uk //}}, {{64}});*/ 10006974Stjones1@inf.ed.ac.uk } 10016974Stjones1@inf.ed.ac.uk } 10026974Stjones1@inf.ed.ac.uk 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); 10036974Stjones1@inf.ed.ac.uk 0x36: stqfa({{fault = new FpDisabled;}}); 10046974Stjones1@inf.ed.ac.uk //XXX need to work in the ASI thing 10056974Stjones1@inf.ed.ac.uk 0x37: Store::stdfa({{Mem.udw = Frd.udw;}}); 10066974Stjones1@inf.ed.ac.uk 0x3C: Cas::casa({{ 10076974Stjones1@inf.ed.ac.uk uint64_t val = Mem.uw; 10086974Stjones1@inf.ed.ac.uk if(Rs2.uw == val) 10096974Stjones1@inf.ed.ac.uk Mem.uw = Rd.uw; 10106973Stjones1@inf.ed.ac.uk Rd.uw = val; 10116973Stjones1@inf.ed.ac.uk }}); 10127944SGiacomo.Gabrielli@arm.com 0x3D: Nop::prefetcha({{ }}); 10137944SGiacomo.Gabrielli@arm.com 0x3E: Cas::casxa({{ 10146974Stjones1@inf.ed.ac.uk uint64_t val = Mem.udw; 10156974Stjones1@inf.ed.ac.uk if(Rs2 == val) 10166974Stjones1@inf.ed.ac.uk Mem.udw = Rd; 10176974Stjones1@inf.ed.ac.uk Rd = val; 10186974Stjones1@inf.ed.ac.uk }}); 10196974Stjones1@inf.ed.ac.uk } 10206974Stjones1@inf.ed.ac.uk } 10216974Stjones1@inf.ed.ac.uk} 10227944SGiacomo.Gabrielli@arm.com