decoder.isa revision 3056
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443056Sgblack@eecs.umich.edu 0x1: decode COND2 452469SN/A { 463056Sgblack@eecs.umich.edu //Branch Always 473056Sgblack@eecs.umich.edu 0x8: decode A 483056Sgblack@eecs.umich.edu { 493056Sgblack@eecs.umich.edu 0x0: b(19, {{ 502516SN/A NNPC = xc->readPC() + disp; 513056Sgblack@eecs.umich.edu }}); 523056Sgblack@eecs.umich.edu 0x1: b(19, {{ 533056Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 543056Sgblack@eecs.umich.edu NNPC = NPC + 4; 553056Sgblack@eecs.umich.edu }}, ',a'); 563056Sgblack@eecs.umich.edu } 573056Sgblack@eecs.umich.edu //Branch Never 583056Sgblack@eecs.umich.edu 0x0: decode A 593056Sgblack@eecs.umich.edu { 603056Sgblack@eecs.umich.edu 0x0: bn(19, {{ 613056Sgblack@eecs.umich.edu NNPC = NNPC;//Don't do anything 623056Sgblack@eecs.umich.edu }}); 633056Sgblack@eecs.umich.edu 0x1: bn(19, {{ 643056Sgblack@eecs.umich.edu NPC = xc->readNextPC() + 4; 653056Sgblack@eecs.umich.edu NNPC = NPC + 4; 663056Sgblack@eecs.umich.edu }}, ',a'); 673056Sgblack@eecs.umich.edu } 683056Sgblack@eecs.umich.edu default: decode BPCC 693056Sgblack@eecs.umich.edu { 703056Sgblack@eecs.umich.edu 0x0: bpcci(19, {{ 713056Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 723056Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 733056Sgblack@eecs.umich.edu else 743056Sgblack@eecs.umich.edu handle_annul 753056Sgblack@eecs.umich.edu }}); 763056Sgblack@eecs.umich.edu 0x2: bpccx(19, {{ 773056Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 783056Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 793056Sgblack@eecs.umich.edu else 803056Sgblack@eecs.umich.edu handle_annul 813056Sgblack@eecs.umich.edu }}); 823056Sgblack@eecs.umich.edu } 832482SN/A } 842944Sgblack@eecs.umich.edu 0x2: bicc(22, {{ 852944Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 862944Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 872944Sgblack@eecs.umich.edu else 882944Sgblack@eecs.umich.edu handle_annul 892944Sgblack@eecs.umich.edu }}); 902516SN/A } 912516SN/A 0x3: decode RCOND2 922516SN/A { 932516SN/A format BranchSplit 942482SN/A { 952482SN/A 0x1: bpreq({{ 962591SN/A if(Rs1.sdw == 0) 972516SN/A NNPC = xc->readPC() + disp; 982580SN/A else 992580SN/A handle_annul 1002482SN/A }}); 1012482SN/A 0x2: bprle({{ 1022591SN/A if(Rs1.sdw <= 0) 1032516SN/A NNPC = xc->readPC() + disp; 1042580SN/A else 1052580SN/A handle_annul 1062482SN/A }}); 1072482SN/A 0x3: bprl({{ 1082591SN/A if(Rs1.sdw < 0) 1092516SN/A NNPC = xc->readPC() + disp; 1102580SN/A else 1112580SN/A handle_annul 1122482SN/A }}); 1132482SN/A 0x5: bprne({{ 1142591SN/A if(Rs1.sdw != 0) 1152516SN/A NNPC = xc->readPC() + disp; 1162580SN/A else 1172580SN/A handle_annul 1182482SN/A }}); 1192482SN/A 0x6: bprg({{ 1202591SN/A if(Rs1.sdw > 0) 1212516SN/A NNPC = xc->readPC() + disp; 1222580SN/A else 1232580SN/A handle_annul 1242482SN/A }}); 1252482SN/A 0x7: bprge({{ 1262591SN/A if(Rs1.sdw >= 0) 1272516SN/A NNPC = xc->readPC() + disp; 1282580SN/A else 1292580SN/A handle_annul 1302482SN/A }}); 1312469SN/A } 1322482SN/A } 1332516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 1343042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 1352516SN/A 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 1362516SN/A 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 1372469SN/A } 1382944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1392516SN/A R15 = xc->readPC(); 1402516SN/A NNPC = R15 + disp; 1412469SN/A }}); 1422469SN/A 0x2: decode OP3 { 1432482SN/A format IntOp { 1442482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1452974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1462974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1472974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1482526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1492974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1502974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1512974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1522646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1532974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1542469SN/A 0x0A: umul({{ 1552516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1562646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1572482SN/A }}); 1582469SN/A 0x0B: smul({{ 1592516SN/A Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 1602646Ssaidi@eecs.umich.edu Y = Rd.sdw; 1612482SN/A }}); 1622954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1632469SN/A 0x0D: udivx({{ 1642516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1652516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1662482SN/A }}); 1672469SN/A 0x0E: udiv({{ 1682516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1692482SN/A else 1702482SN/A { 1712646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1722482SN/A if(Rd.udw >> 32 != 0) 1732482SN/A Rd.udw = 0xFFFFFFFF; 1742482SN/A } 1752482SN/A }}); 1762482SN/A 0x0F: sdiv({{ 1772615SN/A if(Rs2_or_imm13.sdw == 0) 1782469SN/A fault = new DivisionByZero; 1792469SN/A else 1802482SN/A { 1812646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1822482SN/A if(Rd.udw<63:31> != 0) 1832482SN/A Rd.udw = 0x7FFFFFFF; 1842482SN/A else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 1852588SN/A Rd.udw = 0xFFFFFFFF80000000ULL; 1862482SN/A } 1872526SN/A }}); 1882469SN/A } 1892482SN/A format IntOpCc { 1902469SN/A 0x10: addcc({{ 1912516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1922469SN/A Rd = resTemp = Rs1 + val2;}}, 1932580SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 1942469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1952580SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 1962469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1972526SN/A ); 1982482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 1992482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2002482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2012469SN/A 0x14: subcc({{ 2022580SN/A int64_t val2 = Rs2_or_imm13; 2032580SN/A Rd = Rs1 - val2;}}, 2042580SN/A {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 2052580SN/A {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 2062580SN/A {{(~(Rs1<63:1> + (~val2)<63:1> + 2072580SN/A (Rs1 | ~val2)<0:>))<63:>}}, 2082580SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 2092526SN/A ); 2102482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2112482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2122482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2132469SN/A 0x18: addccc({{ 2142516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2152646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2162469SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 2172580SN/A {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 2182469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 2192580SN/A {{(Rs1<63:1> + val2<63:1> + 2202580SN/A ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 2212469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2222526SN/A ); 2232469SN/A 0x1A: umulcc({{ 2242615SN/A uint64_t resTemp; 2252615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2262646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2272526SN/A {{0}},{{0}},{{0}},{{0}}); 2282469SN/A 0x1B: smulcc({{ 2292615SN/A int64_t resTemp; 2302615SN/A Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 2312646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2322526SN/A {{0}},{{0}},{{0}},{{0}}); 2332469SN/A 0x1C: subccc({{ 2342516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2352646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2362954Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 2372580SN/A {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 2382469SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2392580SN/A {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 2402469SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2412526SN/A ); 2422469SN/A 0x1D: udivxcc({{ 2432615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2442615SN/A else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 2452526SN/A ,{{0}},{{0}},{{0}},{{0}}); 2462469SN/A 0x1E: udivcc({{ 2472615SN/A uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2482989Ssaidi@eecs.umich.edu int32_t overflow = 0; 2492469SN/A if(val2 == 0) fault = new DivisionByZero; 2502469SN/A else 2512224SN/A { 2522646Ssaidi@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2532516SN/A overflow = (resTemp<63:32> != 0); 2542516SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 2552516SN/A else Rd = resTemp; 2562469SN/A } }}, 2572469SN/A {{0}}, 2582469SN/A {{overflow}}, 2592469SN/A {{0}}, 2602469SN/A {{0}} 2612526SN/A ); 2622469SN/A 0x1F: sdivcc({{ 2632996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2642996Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2652469SN/A if(val2 == 0) fault = new DivisionByZero; 2662469SN/A else 2672469SN/A { 2682996Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2692996Sgblack@eecs.umich.edu overflow = (Rd<63:31> != 0); 2702996Sgblack@eecs.umich.edu underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); 2712996Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 2722996Sgblack@eecs.umich.edu else if(underflow) Rd = 0xFFFFFFFF80000000ULL; 2732469SN/A } }}, 2742469SN/A {{0}}, 2752469SN/A {{overflow || underflow}}, 2762469SN/A {{0}}, 2772469SN/A {{0}} 2782526SN/A ); 2792469SN/A 0x20: taddcc({{ 2802516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2812469SN/A Rd = resTemp = Rs1 + val2; 2822469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2832469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2842469SN/A {{overflow}}, 2852469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2862469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2872526SN/A ); 2882469SN/A 0x21: tsubcc({{ 2892516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2902469SN/A Rd = resTemp = Rs1 + val2; 2912469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2922516SN/A {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 2932469SN/A {{overflow}}, 2942469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2952469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2962526SN/A ); 2972469SN/A 0x22: taddcctv({{ 2982996Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13; 2992996Sgblack@eecs.umich.edu Rd = Rs1 + val2; 3002954Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || 3012954Sgblack@eecs.umich.edu (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 3022469SN/A if(overflow) fault = new TagOverflow;}}, 3032469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 3042469SN/A {{overflow}}, 3052469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3062996Sgblack@eecs.umich.edu {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 3072526SN/A ); 3082469SN/A 0x23: tsubcctv({{ 3092516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 3102469SN/A Rd = resTemp = Rs1 + val2; 3112469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 3122469SN/A if(overflow) fault = new TagOverflow;}}, 3132469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 3142469SN/A {{overflow}}, 3152469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 3162469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 3172526SN/A ); 3182469SN/A 0x24: mulscc({{ 3192516SN/A int64_t resTemp, multiplicand = Rs2_or_imm13; 3202469SN/A int32_t multiplier = Rs1<31:0>; 3212469SN/A int32_t savedLSB = Rs1<0:>; 3222516SN/A multiplier = multiplier<31:1> | 3232646Ssaidi@eecs.umich.edu ((Ccr<3:3> 3242646Ssaidi@eecs.umich.edu ^ Ccr<1:1>) << 32); 3252646Ssaidi@eecs.umich.edu if(!Y<0:>) 3262469SN/A multiplicand = 0; 3272469SN/A Rd = resTemp = multiplicand + multiplier; 3282646Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 3292469SN/A {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 3302469SN/A {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 3312469SN/A {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 3322469SN/A {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 3332526SN/A ); 3342526SN/A } 3352526SN/A format IntOp 3362526SN/A { 3372526SN/A 0x25: decode X { 3382526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3392526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3402469SN/A } 3412526SN/A 0x26: decode X { 3422526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3432526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3442526SN/A } 3452526SN/A 0x27: decode X { 3462526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3472526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3482526SN/A } 3492646Ssaidi@eecs.umich.edu // XXX might want a format rdipr thing here 3502954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3512954Sgblack@eecs.umich.edu 0xF: decode I { 3522954Sgblack@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}); 3532954Sgblack@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}); 3542954Sgblack@eecs.umich.edu } 3552954Sgblack@eecs.umich.edu default: rdasr({{ 3562646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 3572954Sgblack@eecs.umich.edu }}); 3582954Sgblack@eecs.umich.edu } 3592938Sgblack@eecs.umich.edu 0x29: HPriv::rdhpr({{ 3602646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 3612646Ssaidi@eecs.umich.edu // access 3622646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 3632646Ssaidi@eecs.umich.edu }}); 3642938Sgblack@eecs.umich.edu 0x2A: Priv::rdpr({{ 3652646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 3662646Ssaidi@eecs.umich.edu // access 3672646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 3682646Ssaidi@eecs.umich.edu }}); 3692526SN/A 0x2B: BasicOperate::flushw({{ 3702526SN/A if(NWindows - 2 - Cansave == 0) 3712526SN/A { 3722526SN/A if(Otherwin) 3732646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 3742526SN/A else 3752646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 3762526SN/A } 3772526SN/A }}); 3782526SN/A 0x2C: decode MOVCC3 3792469SN/A { 3802526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 3812526SN/A 0x1: decode CC 3822526SN/A { 3832526SN/A 0x0: movcci({{ 3842646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 3852591SN/A Rd = Rs2_or_imm11; 3862591SN/A else 3872591SN/A Rd = Rd; 3882526SN/A }}); 3892526SN/A 0x2: movccx({{ 3902646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 3912591SN/A Rd = Rs2_or_imm11; 3922591SN/A else 3932591SN/A Rd = Rd; 3942526SN/A }}); 3952224SN/A } 3962526SN/A } 3972526SN/A 0x2D: sdivx({{ 3982615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 3992615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4002526SN/A }}); 4012526SN/A 0x2E: decode RS1 { 4022526SN/A 0x0: IntOp::popc({{ 4032526SN/A int64_t count = 0; 4042526SN/A uint64_t temp = Rs2_or_imm13; 4052526SN/A //Count the 1s in the front 4bits until none are left 4062526SN/A uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 4072526SN/A while(temp) 4082469SN/A { 4092526SN/A count += oneBits[temp & 0xF]; 4102526SN/A temp = temp >> 4; 4112516SN/A } 4122591SN/A Rd = count; 4132516SN/A }}); 4142526SN/A } 4152526SN/A 0x2F: decode RCOND3 4162526SN/A { 4172615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4182615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4192615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4202615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4212615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4222615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4232526SN/A } 4242646Ssaidi@eecs.umich.edu 0x30: wrasr({{ 4252646Ssaidi@eecs.umich.edu xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 4262646Ssaidi@eecs.umich.edu }}); 4272526SN/A 0x31: decode FCN { 4282526SN/A 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 4292526SN/A 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 4302526SN/A } 4312938Sgblack@eecs.umich.edu 0x32: Priv::wrpr({{ 4322646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 4332646Ssaidi@eecs.umich.edu // access 4342938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 4352646Ssaidi@eecs.umich.edu }}); 4362938Sgblack@eecs.umich.edu 0x33: HPriv::wrhpr({{ 4372646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 4382646Ssaidi@eecs.umich.edu // access 4392938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 4402646Ssaidi@eecs.umich.edu }}); 4412954Sgblack@eecs.umich.edu 0x34: decode OPF{ 4422963Sgblack@eecs.umich.edu format BasicOperate{ 4432963Sgblack@eecs.umich.edu 0x01: fmovs({{ 4442963Sgblack@eecs.umich.edu Frd.sf = Frs2.sf; 4452963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4462963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4472963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4482963Sgblack@eecs.umich.edu }}); 4492963Sgblack@eecs.umich.edu 0x02: fmovd({{ 4502963Sgblack@eecs.umich.edu Frd.df = Frs2.df; 4512963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4522963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4532963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4542963Sgblack@eecs.umich.edu }}); 4552963Sgblack@eecs.umich.edu 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 4562963Sgblack@eecs.umich.edu 0x05: fnegs({{ 4572963Sgblack@eecs.umich.edu //XXX might want to explicitly flip the sign bit 4582963Sgblack@eecs.umich.edu //So cases with Nan and +/-0 don't do weird things 4592963Sgblack@eecs.umich.edu Frd.sf = -Frs2.sf; 4602963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4612963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4622963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4632963Sgblack@eecs.umich.edu }}); 4642963Sgblack@eecs.umich.edu 0x06: fnegd({{ 4652963Sgblack@eecs.umich.edu //XXX might want to explicitly flip the sign bit 4662963Sgblack@eecs.umich.edu //So cases with Nan and +/-0 don't do weird things 4672963Sgblack@eecs.umich.edu Frd.df = -Frs2.df; 4682963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4692963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4702963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4712963Sgblack@eecs.umich.edu }}); 4722963Sgblack@eecs.umich.edu 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 4732963Sgblack@eecs.umich.edu 0x09: fabss({{ 4742963Sgblack@eecs.umich.edu //XXX this instruction should be tested individually 4752963Sgblack@eecs.umich.edu //Clear the sign bit 4762963Sgblack@eecs.umich.edu Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf)); 4772963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4782963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4792963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4802963Sgblack@eecs.umich.edu }}); 4812963Sgblack@eecs.umich.edu 0x0A: fabsd({{ 4822963Sgblack@eecs.umich.edu //XXX this instruction should be tested individually 4832963Sgblack@eecs.umich.edu //Clear the sign bit 4842963Sgblack@eecs.umich.edu Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df)); 4852963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 4862963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 4872963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 4882963Sgblack@eecs.umich.edu }}); 4892963Sgblack@eecs.umich.edu 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 4902963Sgblack@eecs.umich.edu 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}}); 4912963Sgblack@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 4922963Sgblack@eecs.umich.edu 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 4932963Sgblack@eecs.umich.edu 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}}); 4942963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 4952963Sgblack@eecs.umich.edu 0x43: Trap::faddq({{fault = new FpDisabled;}}); 4962963Sgblack@eecs.umich.edu 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}}); 4972963Sgblack@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 4982963Sgblack@eecs.umich.edu 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 4992963Sgblack@eecs.umich.edu 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}}); 5002963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 5012963Sgblack@eecs.umich.edu 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 5022963Sgblack@eecs.umich.edu 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}}); 5032963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 5042963Sgblack@eecs.umich.edu 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 5052963Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}}); 5062963Sgblack@eecs.umich.edu 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 5072963Sgblack@eecs.umich.edu 0x81: fstox({{ 5082963Sgblack@eecs.umich.edu Frd.df = (double)static_cast<int64_t>(Frs2.sf); 5092963Sgblack@eecs.umich.edu }}); 5102963Sgblack@eecs.umich.edu 0x82: fdtox({{ 5112963Sgblack@eecs.umich.edu Frd.df = (double)static_cast<int64_t>(Frs2.df); 5122963Sgblack@eecs.umich.edu }}); 5132963Sgblack@eecs.umich.edu 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 5142963Sgblack@eecs.umich.edu 0x84: fxtos({{ 5152963Sgblack@eecs.umich.edu Frd.sf = static_cast<float>((int64_t)Frs2.df); 5162963Sgblack@eecs.umich.edu }}); 5172963Sgblack@eecs.umich.edu 0x88: fxtod({{ 5182963Sgblack@eecs.umich.edu Frd.df = static_cast<double>((int64_t)Frs2.df); 5192963Sgblack@eecs.umich.edu }}); 5202963Sgblack@eecs.umich.edu 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 5212963Sgblack@eecs.umich.edu 0xC4: fitos({{ 5222963Sgblack@eecs.umich.edu Frd.sf = static_cast<float>((int32_t)Frs2.sf); 5232963Sgblack@eecs.umich.edu }}); 5242963Sgblack@eecs.umich.edu 0xC6: fdtos({{Frd.sf = Frs2.df;}}); 5252963Sgblack@eecs.umich.edu 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 5262963Sgblack@eecs.umich.edu 0xC8: fitod({{ 5272963Sgblack@eecs.umich.edu Frd.df = static_cast<double>((int32_t)Frs2.sf); 5282963Sgblack@eecs.umich.edu }}); 5292963Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2.sf;}}); 5302963Sgblack@eecs.umich.edu 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 5312963Sgblack@eecs.umich.edu 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 5322963Sgblack@eecs.umich.edu 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 5332963Sgblack@eecs.umich.edu 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 5342963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 5352963Sgblack@eecs.umich.edu Frd.sf = (float)static_cast<int32_t>(Frs2.sf); 5362963Sgblack@eecs.umich.edu }}); 5372963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 5382963Sgblack@eecs.umich.edu Frd.sf = (float)static_cast<int32_t>(Frs2.df); 5392963Sgblack@eecs.umich.edu }}); 5402963Sgblack@eecs.umich.edu 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 5412963Sgblack@eecs.umich.edu default: Trap::fpop1({{fault = new FpDisabled;}}); 5422963Sgblack@eecs.umich.edu } 5432954Sgblack@eecs.umich.edu } 5442526SN/A 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 5452954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 5462954Sgblack@eecs.umich.edu //of instructions 5472954Sgblack@eecs.umich.edu 0x36: decode OPF{ 5482954Sgblack@eecs.umich.edu 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 5492954Sgblack@eecs.umich.edu 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 5502954Sgblack@eecs.umich.edu 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 5512954Sgblack@eecs.umich.edu 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 5522954Sgblack@eecs.umich.edu 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 5532954Sgblack@eecs.umich.edu 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 5542954Sgblack@eecs.umich.edu 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 5552954Sgblack@eecs.umich.edu 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 5562954Sgblack@eecs.umich.edu 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 5572954Sgblack@eecs.umich.edu 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 5582954Sgblack@eecs.umich.edu 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 5592954Sgblack@eecs.umich.edu 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 5602954Sgblack@eecs.umich.edu 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 5612954Sgblack@eecs.umich.edu 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 5622954Sgblack@eecs.umich.edu 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 5633042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 5642963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 5653042Sgblack@eecs.umich.edu Rd = sum & ~7; 5662963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 5672963Sgblack@eecs.umich.edu }}); 5682954Sgblack@eecs.umich.edu 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 5692963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 5702963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 5713042Sgblack@eecs.umich.edu Rd = sum & ~7; 5722963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 5732963Sgblack@eecs.umich.edu }}); 5742954Sgblack@eecs.umich.edu 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 5752954Sgblack@eecs.umich.edu 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 5762954Sgblack@eecs.umich.edu 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 5772954Sgblack@eecs.umich.edu 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 5782954Sgblack@eecs.umich.edu 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 5792954Sgblack@eecs.umich.edu 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 5802954Sgblack@eecs.umich.edu 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 5812954Sgblack@eecs.umich.edu 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 5822954Sgblack@eecs.umich.edu 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 5832954Sgblack@eecs.umich.edu 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 5842954Sgblack@eecs.umich.edu 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 5852954Sgblack@eecs.umich.edu 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 5862954Sgblack@eecs.umich.edu 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 5872954Sgblack@eecs.umich.edu 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 5882954Sgblack@eecs.umich.edu 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 5892954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 5902954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 5912954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 5922954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 5932963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 5942963Sgblack@eecs.umich.edu uint64_t msbX = (uint64_t)Frs1; 5952963Sgblack@eecs.umich.edu uint64_t lsbX = (uint64_t)Frs2; 5962963Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 5972963Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 5982963Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) << msbShift; 5992963Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 6002963Sgblack@eecs.umich.edu Frd = ((msbX << msbShift) & msbMask) | 6012963Sgblack@eecs.umich.edu ((lsbX << lsbShift) & lsbMask); 6022963Sgblack@eecs.umich.edu }}); 6032954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 6042954Sgblack@eecs.umich.edu 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 6052954Sgblack@eecs.umich.edu 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 6062954Sgblack@eecs.umich.edu 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 6072954Sgblack@eecs.umich.edu 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 6082954Sgblack@eecs.umich.edu 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 6092954Sgblack@eecs.umich.edu 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 6102954Sgblack@eecs.umich.edu 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 6112954Sgblack@eecs.umich.edu 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 6122954Sgblack@eecs.umich.edu 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 6132954Sgblack@eecs.umich.edu 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 6142963Sgblack@eecs.umich.edu 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 6152963Sgblack@eecs.umich.edu 0x61: BasicOperate::fzeros({{Frd.sf = 0;}}); 6162954Sgblack@eecs.umich.edu 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 6172954Sgblack@eecs.umich.edu 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 6182954Sgblack@eecs.umich.edu 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 6192954Sgblack@eecs.umich.edu 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 6202963Sgblack@eecs.umich.edu 0x66: BasicOperate::fnot2({{ 6212963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 6222963Sgblack@eecs.umich.edu }}); 6232963Sgblack@eecs.umich.edu 0x67: BasicOperate::fnot2s({{ 6242963Sgblack@eecs.umich.edu Frd.sf = (float)(~((uint32_t)Frs2.sf)); 6252963Sgblack@eecs.umich.edu }}); 6262954Sgblack@eecs.umich.edu 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 6272954Sgblack@eecs.umich.edu 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 6282963Sgblack@eecs.umich.edu 0x6A: BasicOperate::fnot1({{ 6292963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 6302963Sgblack@eecs.umich.edu }}); 6312963Sgblack@eecs.umich.edu 0x6B: BasicOperate::fnot1s({{ 6322963Sgblack@eecs.umich.edu Frd.sf = (float)(~((uint32_t)Frs1.sf)); 6332963Sgblack@eecs.umich.edu }}); 6342954Sgblack@eecs.umich.edu 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 6352954Sgblack@eecs.umich.edu 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 6362954Sgblack@eecs.umich.edu 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 6372954Sgblack@eecs.umich.edu 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 6382954Sgblack@eecs.umich.edu 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 6392954Sgblack@eecs.umich.edu 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 6402954Sgblack@eecs.umich.edu 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 6412954Sgblack@eecs.umich.edu 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 6422963Sgblack@eecs.umich.edu 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}}); 6432963Sgblack@eecs.umich.edu 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}}); 6442954Sgblack@eecs.umich.edu 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 6452954Sgblack@eecs.umich.edu 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 6462963Sgblack@eecs.umich.edu 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}}); 6472963Sgblack@eecs.umich.edu 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}}); 6482954Sgblack@eecs.umich.edu 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 6492954Sgblack@eecs.umich.edu 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 6502954Sgblack@eecs.umich.edu 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 6512954Sgblack@eecs.umich.edu 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 6522954Sgblack@eecs.umich.edu 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 6532954Sgblack@eecs.umich.edu 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 6542954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 6552954Sgblack@eecs.umich.edu 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 6562954Sgblack@eecs.umich.edu } 6572954Sgblack@eecs.umich.edu 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 6582526SN/A 0x38: Branch::jmpl({{ 6592526SN/A Addr target = Rs1 + Rs2_or_imm13; 6602526SN/A if(target & 0x3) 6612526SN/A fault = new MemAddressNotAligned; 6622526SN/A else 6632526SN/A { 6642526SN/A Rd = xc->readPC(); 6652526SN/A NNPC = target; 6662526SN/A } 6672526SN/A }}); 6682526SN/A 0x39: Branch::return({{ 6692561SN/A //If both MemAddressNotAligned and 6702561SN/A //a fill trap happen, it's not clear 6712561SN/A //which one should be returned. 6722526SN/A Addr target = Rs1 + Rs2_or_imm13; 6732526SN/A if(target & 0x3) 6742526SN/A fault = new MemAddressNotAligned; 6752526SN/A else 6762526SN/A NNPC = target; 6772561SN/A if(fault == NoFault) 6782561SN/A { 6792561SN/A //CWP should be set directly so that it always happens 6802561SN/A //Also, this will allow writing to the new window and 6812561SN/A //reading from the old one 6822561SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 6832561SN/A if(Canrestore == 0) 6842561SN/A { 6852561SN/A if(Otherwin) 6862646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 6872561SN/A else 6882646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 6892561SN/A } 6902561SN/A else 6912561SN/A { 6922561SN/A Rd = Rs1 + Rs2_or_imm13; 6932561SN/A Cansave = Cansave + 1; 6942561SN/A Canrestore = Canrestore - 1; 6952561SN/A } 6962561SN/A //This is here to make sure the CWP is written 6972561SN/A //no matter what. This ensures that the results 6982561SN/A //are written in the new window as well. 6992561SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7002561SN/A } 7012526SN/A }}); 7022526SN/A 0x3A: decode CC 7032526SN/A { 7042526SN/A 0x0: Trap::tcci({{ 7052646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 7062561SN/A { 7073039Sstever@eecs.umich.edu#if FULL_SYSTEM 7082561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 7092561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 7102561SN/A fault = new TrapInstruction(lTrapNum); 7112526SN/A#else 7122561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 7132561SN/A xc->syscall(R1); 7142561SN/A#endif 7152561SN/A } 7162526SN/A }}); 7172526SN/A 0x2: Trap::tccx({{ 7182646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 7192561SN/A { 7203039Sstever@eecs.umich.edu#if FULL_SYSTEM 7212561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 7222561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 7232561SN/A fault = new TrapInstruction(lTrapNum); 7242526SN/A#else 7252561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 7262561SN/A xc->syscall(R1); 7272561SN/A#endif 7282526SN/A } 7292526SN/A }}); 7302526SN/A } 7312526SN/A 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 7322526SN/A 0x3C: save({{ 7332526SN/A //CWP should be set directly so that it always happens 7342526SN/A //Also, this will allow writing to the new window and 7352526SN/A //reading from the old one 7362526SN/A if(Cansave == 0) 7372526SN/A { 7382526SN/A if(Otherwin) 7392646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 7402526SN/A else 7412646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 7422526SN/A Cwp = (Cwp + 2) % NWindows; 7432526SN/A } 7442526SN/A else if(Cleanwin - Canrestore == 0) 7452526SN/A { 7462526SN/A Cwp = (Cwp + 1) % NWindows; 7472526SN/A fault = new CleanWindow; 7482526SN/A } 7492526SN/A else 7502526SN/A { 7512526SN/A Cwp = (Cwp + 1) % NWindows; 7522526SN/A Rd = Rs1 + Rs2_or_imm13; 7532561SN/A Cansave = Cansave - 1; 7542561SN/A Canrestore = Canrestore + 1; 7552526SN/A } 7562526SN/A //This is here to make sure the CWP is written 7572526SN/A //no matter what. This ensures that the results 7582526SN/A //are written in the new window as well. 7592526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7602526SN/A }}); 7612526SN/A 0x3D: restore({{ 7622526SN/A //CWP should be set directly so that it always happens 7632526SN/A //Also, this will allow writing to the new window and 7642526SN/A //reading from the old one 7652526SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 7662526SN/A if(Canrestore == 0) 7672526SN/A { 7682526SN/A if(Otherwin) 7692646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 7702526SN/A else 7712646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 7722526SN/A } 7732526SN/A else 7742526SN/A { 7752526SN/A Rd = Rs1 + Rs2_or_imm13; 7762561SN/A Cansave = Cansave + 1; 7772561SN/A Canrestore = Canrestore - 1; 7782526SN/A } 7792526SN/A //This is here to make sure the CWP is written 7802526SN/A //no matter what. This ensures that the results 7812526SN/A //are written in the new window as well. 7822526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 7832526SN/A }}); 7842526SN/A 0x3E: decode FCN { 7852526SN/A 0x0: Priv::done({{ 7862526SN/A if(Tl == 0) 7872526SN/A return new IllegalInstruction; 7882646Ssaidi@eecs.umich.edu 7892646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 7902646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 7912646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 7922646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 7932646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 7942646Ssaidi@eecs.umich.edu NPC = Tnpc; 7952646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 7962526SN/A Tl = Tl - 1; 7972526SN/A }}); 7982938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 7992526SN/A if(Tl == 0) 8002526SN/A return new IllegalInstruction; 8012646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 8022646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 8032646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 8042646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 8052646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 8062646Ssaidi@eecs.umich.edu NPC = Tpc; 8072646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 8082526SN/A Tl = Tl - 1; 8092526SN/A }}); 8102526SN/A } 8112526SN/A } 8122469SN/A } 8132469SN/A 0x3: decode OP3 { 8142526SN/A format Load { 8152526SN/A 0x00: lduw({{Rd = Mem;}}, {{32}}); 8162526SN/A 0x01: ldub({{Rd = Mem;}}, {{8}}); 8172526SN/A 0x02: lduh({{Rd = Mem;}}, {{16}}); 8182526SN/A 0x03: ldd({{ 8192526SN/A uint64_t val = Mem; 8202526SN/A RdLow = val<31:0>; 8212526SN/A RdHigh = val<63:32>; 8222526SN/A }}, {{64}}); 8232526SN/A } 8242526SN/A format Store { 8252526SN/A 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 8262526SN/A 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 8272526SN/A 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 8282526SN/A 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 8292526SN/A } 8302526SN/A format Load { 8312526SN/A 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 8322526SN/A 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 8332526SN/A 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 8342526SN/A 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 8352526SN/A 0x0D: ldstub({{ 8362526SN/A Rd = Mem; 8372526SN/A Mem = 0xFF; 8382526SN/A }}, {{8}}); 8392526SN/A } 8402526SN/A 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 8412526SN/A 0x0F: LoadStore::swap({{ 8422526SN/A uint32_t temp = Rd; 8432526SN/A Rd = Mem; 8442526SN/A Mem = temp; 8452526SN/A }}, {{32}}); 8462526SN/A format Load { 8472526SN/A 0x10: lduwa({{Rd = Mem;}}, {{32}}); 8482526SN/A 0x11: lduba({{Rd = Mem;}}, {{8}}); 8492526SN/A 0x12: lduha({{Rd = Mem;}}, {{16}}); 8502526SN/A 0x13: ldda({{ 8512526SN/A uint64_t val = Mem; 8522526SN/A RdLow = val<31:0>; 8532526SN/A RdHigh = val<63:32>; 8542526SN/A }}, {{64}}); 8552526SN/A } 8562526SN/A format Store { 8572526SN/A 0x14: stwa({{Mem = Rd;}}, {{32}}); 8582526SN/A 0x15: stba({{Mem = Rd;}}, {{8}}); 8592526SN/A 0x16: stha({{Mem = Rd;}}, {{16}}); 8602526SN/A 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 8612526SN/A } 8622526SN/A format Load { 8632526SN/A 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 8642526SN/A 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 8652526SN/A 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 8662526SN/A 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 8672526SN/A } 8682526SN/A 0x1D: LoadStore::ldstuba({{ 8692526SN/A Rd = Mem; 8702526SN/A Mem = 0xFF; 8712526SN/A }}, {{8}}); 8722526SN/A 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 8732526SN/A 0x1F: LoadStore::swapa({{ 8742526SN/A uint32_t temp = Rd; 8752526SN/A Rd = Mem; 8762526SN/A Mem = temp; 8772526SN/A }}, {{32}}); 8782526SN/A format Trap { 8792963Sgblack@eecs.umich.edu 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}}); 8802526SN/A 0x21: decode X { 8812561SN/A 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 8822561SN/A 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 8832469SN/A } 8842526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 8852963Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}}); 8862963Sgblack@eecs.umich.edu 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 8872526SN/A 0x25: decode X { 8882561SN/A 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 8892561SN/A 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 8902526SN/A } 8912526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 8922963Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}}); 8932526SN/A 0x2D: Nop::prefetch({{ }}); 8942963Sgblack@eecs.umich.edu 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}}); 8952526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 8962963Sgblack@eecs.umich.edu 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}}); 8972963Sgblack@eecs.umich.edu 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 8982954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 8992954Sgblack@eecs.umich.edu //XXX need to work in the ASI thing 9002963Sgblack@eecs.umich.edu 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}}); 9012526SN/A 0x3C: Cas::casa({{ 9022526SN/A uint64_t val = Mem.uw; 9032526SN/A if(Rs2.uw == val) 9042526SN/A Mem.uw = Rd.uw; 9052526SN/A Rd.uw = val; 9062526SN/A }}); 9072526SN/A 0x3D: Nop::prefetcha({{ }}); 9082526SN/A 0x3E: Cas::casxa({{ 9092526SN/A uint64_t val = Mem.udw; 9102526SN/A if(Rs2 == val) 9112526SN/A Mem.udw = Rd; 9122526SN/A Rd = val; 9132526SN/A }}); 9142526SN/A } 9152469SN/A } 9162022SN/A} 917