decoder.isa revision 2954
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 442944Sgblack@eecs.umich.edu 0x1: decode BPCC 452469SN/A { 462944Sgblack@eecs.umich.edu 0x0: bpcci(19, {{ 472646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 482516SN/A NNPC = xc->readPC() + disp; 492580SN/A else 502580SN/A handle_annul 512486SN/A }}); 522944Sgblack@eecs.umich.edu 0x2: bpccx(19, {{ 532646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 542516SN/A NNPC = xc->readPC() + disp; 552580SN/A else 562580SN/A handle_annul 572486SN/A }}); 582482SN/A } 592944Sgblack@eecs.umich.edu 0x2: bicc(22, {{ 602944Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 612944Sgblack@eecs.umich.edu NNPC = xc->readPC() + disp; 622944Sgblack@eecs.umich.edu else 632944Sgblack@eecs.umich.edu handle_annul 642944Sgblack@eecs.umich.edu }}); 652516SN/A } 662516SN/A 0x3: decode RCOND2 672516SN/A { 682516SN/A format BranchSplit 692482SN/A { 702482SN/A 0x1: bpreq({{ 712591SN/A if(Rs1.sdw == 0) 722516SN/A NNPC = xc->readPC() + disp; 732580SN/A else 742580SN/A handle_annul 752482SN/A }}); 762482SN/A 0x2: bprle({{ 772591SN/A if(Rs1.sdw <= 0) 782516SN/A NNPC = xc->readPC() + disp; 792580SN/A else 802580SN/A handle_annul 812482SN/A }}); 822482SN/A 0x3: bprl({{ 832591SN/A if(Rs1.sdw < 0) 842516SN/A NNPC = xc->readPC() + disp; 852580SN/A else 862580SN/A handle_annul 872482SN/A }}); 882482SN/A 0x5: bprne({{ 892591SN/A if(Rs1.sdw != 0) 902516SN/A NNPC = xc->readPC() + disp; 912580SN/A else 922580SN/A handle_annul 932482SN/A }}); 942482SN/A 0x6: bprg({{ 952591SN/A if(Rs1.sdw > 0) 962516SN/A NNPC = xc->readPC() + disp; 972580SN/A else 982580SN/A handle_annul 992482SN/A }}); 1002482SN/A 0x7: bprge({{ 1012591SN/A if(Rs1.sdw >= 0) 1022516SN/A NNPC = xc->readPC() + disp; 1032580SN/A else 1042580SN/A handle_annul 1052482SN/A }}); 1062469SN/A } 1072482SN/A } 1082516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 1092516SN/A 0x4: SetHi::sethi({{Rd = imm;}}); 1102516SN/A 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 1112516SN/A 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 1122469SN/A } 1132944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1142516SN/A R15 = xc->readPC(); 1152516SN/A NNPC = R15 + disp; 1162469SN/A }}); 1172469SN/A 0x2: decode OP3 { 1182482SN/A format IntOp { 1192482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1202482SN/A 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 1212482SN/A 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 1222482SN/A 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 1232526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1242516SN/A 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 1252516SN/A 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 1262516SN/A 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 1272646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1282516SN/A 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 1292469SN/A 0x0A: umul({{ 1302516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1312646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1322482SN/A }}); 1332469SN/A 0x0B: smul({{ 1342516SN/A Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 1352646Ssaidi@eecs.umich.edu Y = Rd.sdw; 1362482SN/A }}); 1372954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1382469SN/A 0x0D: udivx({{ 1392516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1402516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1412482SN/A }}); 1422469SN/A 0x0E: udiv({{ 1432516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1442482SN/A else 1452482SN/A { 1462646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1472482SN/A if(Rd.udw >> 32 != 0) 1482482SN/A Rd.udw = 0xFFFFFFFF; 1492482SN/A } 1502482SN/A }}); 1512482SN/A 0x0F: sdiv({{ 1522615SN/A if(Rs2_or_imm13.sdw == 0) 1532469SN/A fault = new DivisionByZero; 1542469SN/A else 1552482SN/A { 1562646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1572482SN/A if(Rd.udw<63:31> != 0) 1582482SN/A Rd.udw = 0x7FFFFFFF; 1592482SN/A else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 1602588SN/A Rd.udw = 0xFFFFFFFF80000000ULL; 1612482SN/A } 1622526SN/A }}); 1632469SN/A } 1642482SN/A format IntOpCc { 1652469SN/A 0x10: addcc({{ 1662516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1672469SN/A Rd = resTemp = Rs1 + val2;}}, 1682580SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 1692469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1702580SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 1712469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1722526SN/A ); 1732482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 1742482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 1752482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 1762469SN/A 0x14: subcc({{ 1772580SN/A int64_t val2 = Rs2_or_imm13; 1782580SN/A Rd = Rs1 - val2;}}, 1792580SN/A {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 1802580SN/A {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 1812580SN/A {{(~(Rs1<63:1> + (~val2)<63:1> + 1822580SN/A (Rs1 | ~val2)<0:>))<63:>}}, 1832580SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 1842526SN/A ); 1852482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 1862482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 1872482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 1882469SN/A 0x18: addccc({{ 1892516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1902646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 1912469SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 1922580SN/A {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 1932469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1942580SN/A {{(Rs1<63:1> + val2<63:1> + 1952580SN/A ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 1962469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1972526SN/A ); 1982469SN/A 0x1A: umulcc({{ 1992615SN/A uint64_t resTemp; 2002615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2012646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2022526SN/A {{0}},{{0}},{{0}},{{0}}); 2032469SN/A 0x1B: smulcc({{ 2042615SN/A int64_t resTemp; 2052615SN/A Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 2062646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2072526SN/A {{0}},{{0}},{{0}},{{0}}); 2082469SN/A 0x1C: subccc({{ 2092516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2102646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2112954Sgblack@eecs.umich.edu Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 2122580SN/A {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 2132469SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2142580SN/A {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 2152469SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2162526SN/A ); 2172469SN/A 0x1D: udivxcc({{ 2182615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2192615SN/A else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 2202526SN/A ,{{0}},{{0}},{{0}},{{0}}); 2212469SN/A 0x1E: udivcc({{ 2222615SN/A uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2232516SN/A int32_t overflow; 2242469SN/A if(val2 == 0) fault = new DivisionByZero; 2252469SN/A else 2262224SN/A { 2272646Ssaidi@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2282516SN/A overflow = (resTemp<63:32> != 0); 2292516SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 2302516SN/A else Rd = resTemp; 2312469SN/A } }}, 2322469SN/A {{0}}, 2332469SN/A {{overflow}}, 2342469SN/A {{0}}, 2352469SN/A {{0}} 2362526SN/A ); 2372469SN/A 0x1F: sdivcc({{ 2382615SN/A int32_t resTemp, val2 = Rs2_or_imm13.sdw; 2392516SN/A int32_t overflow, underflow; 2402469SN/A if(val2 == 0) fault = new DivisionByZero; 2412469SN/A else 2422469SN/A { 2432646Ssaidi@eecs.umich.edu Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2442516SN/A overflow = (resTemp<63:31> != 0); 2452516SN/A underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 2462516SN/A if(overflow) Rd = resTemp = 0x7FFFFFFF; 2472588SN/A else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; 2482516SN/A else Rd = resTemp; 2492469SN/A } }}, 2502469SN/A {{0}}, 2512469SN/A {{overflow || underflow}}, 2522469SN/A {{0}}, 2532469SN/A {{0}} 2542526SN/A ); 2552469SN/A 0x20: taddcc({{ 2562516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2572469SN/A Rd = resTemp = Rs1 + val2; 2582469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2592469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2602469SN/A {{overflow}}, 2612469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2622469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2632526SN/A ); 2642469SN/A 0x21: tsubcc({{ 2652516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2662469SN/A Rd = resTemp = Rs1 + val2; 2672469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2682516SN/A {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 2692469SN/A {{overflow}}, 2702469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2712469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2722526SN/A ); 2732469SN/A 0x22: taddcctv({{ 2742516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2752954Sgblack@eecs.umich.edu Rd = Rs1 + val2; 2762954Sgblack@eecs.umich.edu int32_t overflow = Rs1<1:0> || val2<1:0> || 2772954Sgblack@eecs.umich.edu (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 2782469SN/A if(overflow) fault = new TagOverflow;}}, 2792469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2802469SN/A {{overflow}}, 2812469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2822469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2832526SN/A ); 2842469SN/A 0x23: tsubcctv({{ 2852516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2862469SN/A Rd = resTemp = Rs1 + val2; 2872469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 2882469SN/A if(overflow) fault = new TagOverflow;}}, 2892469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2902469SN/A {{overflow}}, 2912469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2922469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2932526SN/A ); 2942469SN/A 0x24: mulscc({{ 2952516SN/A int64_t resTemp, multiplicand = Rs2_or_imm13; 2962469SN/A int32_t multiplier = Rs1<31:0>; 2972469SN/A int32_t savedLSB = Rs1<0:>; 2982516SN/A multiplier = multiplier<31:1> | 2992646Ssaidi@eecs.umich.edu ((Ccr<3:3> 3002646Ssaidi@eecs.umich.edu ^ Ccr<1:1>) << 32); 3012646Ssaidi@eecs.umich.edu if(!Y<0:>) 3022469SN/A multiplicand = 0; 3032469SN/A Rd = resTemp = multiplicand + multiplier; 3042646Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 3052469SN/A {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 3062469SN/A {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 3072469SN/A {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 3082469SN/A {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 3092526SN/A ); 3102526SN/A } 3112526SN/A format IntOp 3122526SN/A { 3132526SN/A 0x25: decode X { 3142526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3152526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3162469SN/A } 3172526SN/A 0x26: decode X { 3182526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3192526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3202526SN/A } 3212526SN/A 0x27: decode X { 3222526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3232526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3242526SN/A } 3252646Ssaidi@eecs.umich.edu // XXX might want a format rdipr thing here 3262954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3272954Sgblack@eecs.umich.edu 0xF: decode I { 3282954Sgblack@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}); 3292954Sgblack@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}); 3302954Sgblack@eecs.umich.edu } 3312954Sgblack@eecs.umich.edu default: rdasr({{ 3322646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 3332954Sgblack@eecs.umich.edu }}); 3342954Sgblack@eecs.umich.edu } 3352938Sgblack@eecs.umich.edu 0x29: HPriv::rdhpr({{ 3362646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 3372646Ssaidi@eecs.umich.edu // access 3382646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 3392646Ssaidi@eecs.umich.edu }}); 3402938Sgblack@eecs.umich.edu 0x2A: Priv::rdpr({{ 3412646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 3422646Ssaidi@eecs.umich.edu // access 3432646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 3442646Ssaidi@eecs.umich.edu }}); 3452526SN/A 0x2B: BasicOperate::flushw({{ 3462526SN/A if(NWindows - 2 - Cansave == 0) 3472526SN/A { 3482526SN/A if(Otherwin) 3492646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 3502526SN/A else 3512646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 3522526SN/A } 3532526SN/A }}); 3542526SN/A 0x2C: decode MOVCC3 3552469SN/A { 3562526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 3572526SN/A 0x1: decode CC 3582526SN/A { 3592526SN/A 0x0: movcci({{ 3602646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 3612591SN/A Rd = Rs2_or_imm11; 3622591SN/A else 3632591SN/A Rd = Rd; 3642526SN/A }}); 3652526SN/A 0x2: movccx({{ 3662646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 3672591SN/A Rd = Rs2_or_imm11; 3682591SN/A else 3692591SN/A Rd = Rd; 3702526SN/A }}); 3712224SN/A } 3722526SN/A } 3732526SN/A 0x2D: sdivx({{ 3742615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 3752615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 3762526SN/A }}); 3772526SN/A 0x2E: decode RS1 { 3782526SN/A 0x0: IntOp::popc({{ 3792526SN/A int64_t count = 0; 3802526SN/A uint64_t temp = Rs2_or_imm13; 3812526SN/A //Count the 1s in the front 4bits until none are left 3822526SN/A uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 3832526SN/A while(temp) 3842469SN/A { 3852526SN/A count += oneBits[temp & 0xF]; 3862526SN/A temp = temp >> 4; 3872516SN/A } 3882591SN/A Rd = count; 3892516SN/A }}); 3902526SN/A } 3912526SN/A 0x2F: decode RCOND3 3922526SN/A { 3932615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 3942615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 3952615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 3962615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 3972615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 3982615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 3992526SN/A } 4002646Ssaidi@eecs.umich.edu 0x30: wrasr({{ 4012646Ssaidi@eecs.umich.edu xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 4022646Ssaidi@eecs.umich.edu }}); 4032526SN/A 0x31: decode FCN { 4042526SN/A 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 4052526SN/A 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 4062526SN/A } 4072938Sgblack@eecs.umich.edu 0x32: Priv::wrpr({{ 4082646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 4092646Ssaidi@eecs.umich.edu // access 4102938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 4112646Ssaidi@eecs.umich.edu }}); 4122938Sgblack@eecs.umich.edu 0x33: HPriv::wrhpr({{ 4132646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 4142646Ssaidi@eecs.umich.edu // access 4152938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 4162646Ssaidi@eecs.umich.edu }}); 4172954Sgblack@eecs.umich.edu 0x34: decode OPF{ 4182954Sgblack@eecs.umich.edu 0x01: Trap::fmovs({{fault = new FpDisabled;}}); 4192954Sgblack@eecs.umich.edu 0x02: Trap::fmovd({{fault = new FpDisabled;}}); 4202954Sgblack@eecs.umich.edu 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 4212954Sgblack@eecs.umich.edu 0x05: Trap::fnegs({{fault = new FpDisabled;}}); 4222954Sgblack@eecs.umich.edu 0x06: Trap::fnegd({{fault = new FpDisabled;}}); 4232954Sgblack@eecs.umich.edu 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 4242954Sgblack@eecs.umich.edu 0x09: Trap::fabss({{fault = new FpDisabled;}}); 4252954Sgblack@eecs.umich.edu 0x0A: Trap::fabsd({{fault = new FpDisabled;}}); 4262954Sgblack@eecs.umich.edu 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 4272954Sgblack@eecs.umich.edu 0x29: Trap::fsqrts({{fault = new FpDisabled;}}); 4282954Sgblack@eecs.umich.edu 0x2A: Trap::fsqrtd({{fault = new FpDisabled;}}); 4292954Sgblack@eecs.umich.edu 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 4302954Sgblack@eecs.umich.edu 0x41: Trap::fadds({{fault = new FpDisabled;}}); 4312954Sgblack@eecs.umich.edu 0x42: BasicOperate::faddd({{Frd = Frs1 + Frs2;}}); 4322954Sgblack@eecs.umich.edu 0x43: Trap::faddq({{fault = new FpDisabled;}}); 4332954Sgblack@eecs.umich.edu 0x45: Trap::fsubs({{fault = new FpDisabled;}}); 4342954Sgblack@eecs.umich.edu 0x46: Trap::fsubd({{fault = new FpDisabled;}}); 4352954Sgblack@eecs.umich.edu 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 4362954Sgblack@eecs.umich.edu 0x49: Trap::fmuls({{fault = new FpDisabled;}}); 4372954Sgblack@eecs.umich.edu 0x4A: BasicOperate::fmuld({{Frd = Frs1.sf * Frs2.sf;}}); 4382954Sgblack@eecs.umich.edu 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 4392954Sgblack@eecs.umich.edu 0x4D: Trap::fdivs({{fault = new FpDisabled;}}); 4402954Sgblack@eecs.umich.edu 0x4E: Trap::fdivd({{fault = new FpDisabled;}}); 4412954Sgblack@eecs.umich.edu 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 4422954Sgblack@eecs.umich.edu 0x69: Trap::fsmuld({{fault = new FpDisabled;}}); 4432954Sgblack@eecs.umich.edu 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 4442954Sgblack@eecs.umich.edu 0x81: Trap::fstox({{fault = new FpDisabled;}}); 4452954Sgblack@eecs.umich.edu 0x82: Trap::fdtox({{fault = new FpDisabled;}}); 4462954Sgblack@eecs.umich.edu 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 4472954Sgblack@eecs.umich.edu 0x84: Trap::fxtos({{fault = new FpDisabled;}}); 4482954Sgblack@eecs.umich.edu 0x88: Trap::fxtod({{fault = new FpDisabled;}}); 4492954Sgblack@eecs.umich.edu 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 4502954Sgblack@eecs.umich.edu 0xC4: Trap::fitos({{fault = new FpDisabled;}}); 4512954Sgblack@eecs.umich.edu 0xC6: Trap::fdtos({{fault = new FpDisabled;}}); 4522954Sgblack@eecs.umich.edu 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 4532954Sgblack@eecs.umich.edu 0xC8: Trap::fitod({{fault = new FpDisabled;}}); 4542954Sgblack@eecs.umich.edu 0xC9: Trap::fstod({{fault = new FpDisabled;}}); 4552954Sgblack@eecs.umich.edu 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 4562954Sgblack@eecs.umich.edu 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 4572954Sgblack@eecs.umich.edu 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 4582954Sgblack@eecs.umich.edu 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 4592954Sgblack@eecs.umich.edu 0xD1: Trap::fstoi({{fault = new FpDisabled;}}); 4602954Sgblack@eecs.umich.edu 0xD2: Trap::fdtoi({{fault = new FpDisabled;}}); 4612954Sgblack@eecs.umich.edu 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 4622954Sgblack@eecs.umich.edu default: Trap::fpop1({{fault = new FpDisabled;}}); 4632954Sgblack@eecs.umich.edu } 4642526SN/A 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 4652954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 4662954Sgblack@eecs.umich.edu //of instructions 4672954Sgblack@eecs.umich.edu 0x36: decode OPF{ 4682954Sgblack@eecs.umich.edu 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 4692954Sgblack@eecs.umich.edu 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 4702954Sgblack@eecs.umich.edu 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 4712954Sgblack@eecs.umich.edu 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 4722954Sgblack@eecs.umich.edu 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 4732954Sgblack@eecs.umich.edu 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 4742954Sgblack@eecs.umich.edu 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 4752954Sgblack@eecs.umich.edu 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 4762954Sgblack@eecs.umich.edu 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 4772954Sgblack@eecs.umich.edu 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 4782954Sgblack@eecs.umich.edu 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 4792954Sgblack@eecs.umich.edu 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 4802954Sgblack@eecs.umich.edu 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 4812954Sgblack@eecs.umich.edu 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 4822954Sgblack@eecs.umich.edu 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 4832954Sgblack@eecs.umich.edu 0x18: Trap::alignaddress({{fault = new IllegalInstruction;}}); 4842954Sgblack@eecs.umich.edu 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 4852954Sgblack@eecs.umich.edu 0x1A: Trap::alignaddresslittle({{fault = new IllegalInstruction;}}); 4862954Sgblack@eecs.umich.edu 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 4872954Sgblack@eecs.umich.edu 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 4882954Sgblack@eecs.umich.edu 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 4892954Sgblack@eecs.umich.edu 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 4902954Sgblack@eecs.umich.edu 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 4912954Sgblack@eecs.umich.edu 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 4922954Sgblack@eecs.umich.edu 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 4932954Sgblack@eecs.umich.edu 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 4942954Sgblack@eecs.umich.edu 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 4952954Sgblack@eecs.umich.edu 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 4962954Sgblack@eecs.umich.edu 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 4972954Sgblack@eecs.umich.edu 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 4982954Sgblack@eecs.umich.edu 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 4992954Sgblack@eecs.umich.edu 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 5002954Sgblack@eecs.umich.edu 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 5012954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 5022954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 5032954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 5042954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 5052954Sgblack@eecs.umich.edu 0x48: Trap::faligndata({{fault = new IllegalInstruction;}}); 5062954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 5072954Sgblack@eecs.umich.edu 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 5082954Sgblack@eecs.umich.edu 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 5092954Sgblack@eecs.umich.edu 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 5102954Sgblack@eecs.umich.edu 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 5112954Sgblack@eecs.umich.edu 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 5122954Sgblack@eecs.umich.edu 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 5132954Sgblack@eecs.umich.edu 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 5142954Sgblack@eecs.umich.edu 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 5152954Sgblack@eecs.umich.edu 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 5162954Sgblack@eecs.umich.edu 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 5172954Sgblack@eecs.umich.edu 0x60: BasicOperate::fzero({{Frd = 0;}}); 5182954Sgblack@eecs.umich.edu 0x61: Trap::fzeros({{fault = new IllegalInstruction;}}); 5192954Sgblack@eecs.umich.edu 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 5202954Sgblack@eecs.umich.edu 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 5212954Sgblack@eecs.umich.edu 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 5222954Sgblack@eecs.umich.edu 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 5232954Sgblack@eecs.umich.edu 0x66: Trap::fnot2({{fault = new IllegalInstruction;}}); 5242954Sgblack@eecs.umich.edu 0x67: Trap::fnot2s({{fault = new IllegalInstruction;}}); 5252954Sgblack@eecs.umich.edu 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 5262954Sgblack@eecs.umich.edu 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 5272954Sgblack@eecs.umich.edu 0x6A: Trap::fnot1({{fault = new IllegalInstruction;}}); 5282954Sgblack@eecs.umich.edu 0x6B: Trap::fnot1s({{fault = new IllegalInstruction;}}); 5292954Sgblack@eecs.umich.edu 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 5302954Sgblack@eecs.umich.edu 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 5312954Sgblack@eecs.umich.edu 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 5322954Sgblack@eecs.umich.edu 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 5332954Sgblack@eecs.umich.edu 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 5342954Sgblack@eecs.umich.edu 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 5352954Sgblack@eecs.umich.edu 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 5362954Sgblack@eecs.umich.edu 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 5372954Sgblack@eecs.umich.edu 0x74: Trap::fsrc1({{fault = new IllegalInstruction;}}); 5382954Sgblack@eecs.umich.edu 0x75: Trap::fsrc1s({{fault = new IllegalInstruction;}}); 5392954Sgblack@eecs.umich.edu 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 5402954Sgblack@eecs.umich.edu 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 5412954Sgblack@eecs.umich.edu 0x78: Trap::fsrc2({{fault = new IllegalInstruction;}}); 5422954Sgblack@eecs.umich.edu 0x79: Trap::fsrc2s({{fault = new IllegalInstruction;}}); 5432954Sgblack@eecs.umich.edu 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 5442954Sgblack@eecs.umich.edu 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 5452954Sgblack@eecs.umich.edu 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 5462954Sgblack@eecs.umich.edu 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 5472954Sgblack@eecs.umich.edu 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 5482954Sgblack@eecs.umich.edu 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 5492954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 5502954Sgblack@eecs.umich.edu 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 5512954Sgblack@eecs.umich.edu } 5522954Sgblack@eecs.umich.edu 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 5532526SN/A 0x38: Branch::jmpl({{ 5542526SN/A Addr target = Rs1 + Rs2_or_imm13; 5552526SN/A if(target & 0x3) 5562526SN/A fault = new MemAddressNotAligned; 5572526SN/A else 5582526SN/A { 5592526SN/A Rd = xc->readPC(); 5602526SN/A NNPC = target; 5612526SN/A } 5622526SN/A }}); 5632526SN/A 0x39: Branch::return({{ 5642561SN/A //If both MemAddressNotAligned and 5652561SN/A //a fill trap happen, it's not clear 5662561SN/A //which one should be returned. 5672526SN/A Addr target = Rs1 + Rs2_or_imm13; 5682526SN/A if(target & 0x3) 5692526SN/A fault = new MemAddressNotAligned; 5702526SN/A else 5712526SN/A NNPC = target; 5722561SN/A if(fault == NoFault) 5732561SN/A { 5742561SN/A //CWP should be set directly so that it always happens 5752561SN/A //Also, this will allow writing to the new window and 5762561SN/A //reading from the old one 5772561SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 5782561SN/A if(Canrestore == 0) 5792561SN/A { 5802561SN/A if(Otherwin) 5812646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 5822561SN/A else 5832646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 5842561SN/A } 5852561SN/A else 5862561SN/A { 5872561SN/A Rd = Rs1 + Rs2_or_imm13; 5882561SN/A Cansave = Cansave + 1; 5892561SN/A Canrestore = Canrestore - 1; 5902561SN/A } 5912561SN/A //This is here to make sure the CWP is written 5922561SN/A //no matter what. This ensures that the results 5932561SN/A //are written in the new window as well. 5942561SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 5952561SN/A } 5962526SN/A }}); 5972526SN/A 0x3A: decode CC 5982526SN/A { 5992526SN/A 0x0: Trap::tcci({{ 6002646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 6012561SN/A { 6022561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 6032561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 6042526SN/A#if FULL_SYSTEM 6052561SN/A fault = new TrapInstruction(lTrapNum); 6062526SN/A#else 6072561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 6082561SN/A xc->syscall(R1); 6092561SN/A#endif 6102561SN/A } 6112526SN/A }}); 6122526SN/A 0x2: Trap::tccx({{ 6132646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 6142561SN/A { 6152561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 6162561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 6172526SN/A#if FULL_SYSTEM 6182561SN/A fault = new TrapInstruction(lTrapNum); 6192526SN/A#else 6202561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 6212561SN/A xc->syscall(R1); 6222561SN/A#endif 6232526SN/A } 6242526SN/A }}); 6252526SN/A } 6262526SN/A 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 6272526SN/A 0x3C: save({{ 6282526SN/A //CWP should be set directly so that it always happens 6292526SN/A //Also, this will allow writing to the new window and 6302526SN/A //reading from the old one 6312526SN/A if(Cansave == 0) 6322526SN/A { 6332526SN/A if(Otherwin) 6342646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 6352526SN/A else 6362646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 6372526SN/A Cwp = (Cwp + 2) % NWindows; 6382526SN/A } 6392526SN/A else if(Cleanwin - Canrestore == 0) 6402526SN/A { 6412526SN/A Cwp = (Cwp + 1) % NWindows; 6422526SN/A fault = new CleanWindow; 6432526SN/A } 6442526SN/A else 6452526SN/A { 6462526SN/A Cwp = (Cwp + 1) % NWindows; 6472526SN/A Rd = Rs1 + Rs2_or_imm13; 6482561SN/A Cansave = Cansave - 1; 6492561SN/A Canrestore = Canrestore + 1; 6502526SN/A } 6512526SN/A //This is here to make sure the CWP is written 6522526SN/A //no matter what. This ensures that the results 6532526SN/A //are written in the new window as well. 6542526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 6552526SN/A }}); 6562526SN/A 0x3D: restore({{ 6572526SN/A //CWP should be set directly so that it always happens 6582526SN/A //Also, this will allow writing to the new window and 6592526SN/A //reading from the old one 6602526SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 6612526SN/A if(Canrestore == 0) 6622526SN/A { 6632526SN/A if(Otherwin) 6642646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 6652526SN/A else 6662646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 6672526SN/A } 6682526SN/A else 6692526SN/A { 6702526SN/A Rd = Rs1 + Rs2_or_imm13; 6712561SN/A Cansave = Cansave + 1; 6722561SN/A Canrestore = Canrestore - 1; 6732526SN/A } 6742526SN/A //This is here to make sure the CWP is written 6752526SN/A //no matter what. This ensures that the results 6762526SN/A //are written in the new window as well. 6772526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 6782526SN/A }}); 6792526SN/A 0x3E: decode FCN { 6802526SN/A 0x0: Priv::done({{ 6812526SN/A if(Tl == 0) 6822526SN/A return new IllegalInstruction; 6832646Ssaidi@eecs.umich.edu 6842646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 6852646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 6862646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 6872646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 6882646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 6892646Ssaidi@eecs.umich.edu NPC = Tnpc; 6902646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 6912526SN/A Tl = Tl - 1; 6922526SN/A }}); 6932938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 6942526SN/A if(Tl == 0) 6952526SN/A return new IllegalInstruction; 6962646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 6972646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 6982646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 6992646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 7002646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 7012646Ssaidi@eecs.umich.edu NPC = Tpc; 7022646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 7032526SN/A Tl = Tl - 1; 7042526SN/A }}); 7052526SN/A } 7062526SN/A } 7072469SN/A } 7082469SN/A 0x3: decode OP3 { 7092526SN/A format Load { 7102526SN/A 0x00: lduw({{Rd = Mem;}}, {{32}}); 7112526SN/A 0x01: ldub({{Rd = Mem;}}, {{8}}); 7122526SN/A 0x02: lduh({{Rd = Mem;}}, {{16}}); 7132526SN/A 0x03: ldd({{ 7142526SN/A uint64_t val = Mem; 7152526SN/A RdLow = val<31:0>; 7162526SN/A RdHigh = val<63:32>; 7172526SN/A }}, {{64}}); 7182526SN/A } 7192526SN/A format Store { 7202526SN/A 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 7212526SN/A 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 7222526SN/A 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 7232526SN/A 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 7242526SN/A } 7252526SN/A format Load { 7262526SN/A 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 7272526SN/A 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 7282526SN/A 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 7292526SN/A 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 7302526SN/A 0x0D: ldstub({{ 7312526SN/A Rd = Mem; 7322526SN/A Mem = 0xFF; 7332526SN/A }}, {{8}}); 7342526SN/A } 7352526SN/A 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 7362526SN/A 0x0F: LoadStore::swap({{ 7372526SN/A uint32_t temp = Rd; 7382526SN/A Rd = Mem; 7392526SN/A Mem = temp; 7402526SN/A }}, {{32}}); 7412526SN/A format Load { 7422526SN/A 0x10: lduwa({{Rd = Mem;}}, {{32}}); 7432526SN/A 0x11: lduba({{Rd = Mem;}}, {{8}}); 7442526SN/A 0x12: lduha({{Rd = Mem;}}, {{16}}); 7452526SN/A 0x13: ldda({{ 7462526SN/A uint64_t val = Mem; 7472526SN/A RdLow = val<31:0>; 7482526SN/A RdHigh = val<63:32>; 7492526SN/A }}, {{64}}); 7502526SN/A } 7512526SN/A format Store { 7522526SN/A 0x14: stwa({{Mem = Rd;}}, {{32}}); 7532526SN/A 0x15: stba({{Mem = Rd;}}, {{8}}); 7542526SN/A 0x16: stha({{Mem = Rd;}}, {{16}}); 7552526SN/A 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 7562526SN/A } 7572526SN/A format Load { 7582526SN/A 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 7592526SN/A 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 7602526SN/A 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 7612526SN/A 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 7622526SN/A } 7632526SN/A 0x1D: LoadStore::ldstuba({{ 7642526SN/A Rd = Mem; 7652526SN/A Mem = 0xFF; 7662526SN/A }}, {{8}}); 7672526SN/A 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 7682526SN/A 0x1F: LoadStore::swapa({{ 7692526SN/A uint32_t temp = Rd; 7702526SN/A Rd = Mem; 7712526SN/A Mem = temp; 7722526SN/A }}, {{32}}); 7732526SN/A format Trap { 7742526SN/A 0x20: ldf({{fault = new FpDisabled;}}); 7752526SN/A 0x21: decode X { 7762561SN/A 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 7772561SN/A 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 7782469SN/A } 7792526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 7802526SN/A 0x23: lddf({{fault = new FpDisabled;}}); 7812526SN/A 0x24: stf({{fault = new FpDisabled;}}); 7822526SN/A 0x25: decode X { 7832561SN/A 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 7842561SN/A 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 7852526SN/A } 7862526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 7872526SN/A 0x27: stdf({{fault = new FpDisabled;}}); 7882526SN/A 0x2D: Nop::prefetch({{ }}); 7892954Sgblack@eecs.umich.edu 0x30: ldfa({{fault = new FpDisabled;}}); 7902526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 7912526SN/A 0x33: lddfa({{fault = new FpDisabled;}}); 7922526SN/A 0x34: stfa({{fault = new FpDisabled;}}); 7932954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 7942954Sgblack@eecs.umich.edu //XXX need to work in the ASI thing 7952954Sgblack@eecs.umich.edu 0x37: Store::stdfa({{Mem = ((uint64_t)Frd);}}, {{64}}); 7962526SN/A 0x3C: Cas::casa({{ 7972526SN/A uint64_t val = Mem.uw; 7982526SN/A if(Rs2.uw == val) 7992526SN/A Mem.uw = Rd.uw; 8002526SN/A Rd.uw = val; 8012526SN/A }}); 8022526SN/A 0x3D: Nop::prefetcha({{ }}); 8032526SN/A 0x3E: Cas::casxa({{ 8042526SN/A uint64_t val = Mem.udw; 8052526SN/A if(Rs2 == val) 8062526SN/A Mem.udw = Rd; 8072526SN/A Rd = val; 8082526SN/A }}); 8092526SN/A } 8102469SN/A } 8112022SN/A} 812