decoder.isa revision 2938
12632Sstever@eecs.umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422516SN/A 0x1: decode BPCC 432482SN/A { 442516SN/A format Branch19 452469SN/A { 462486SN/A 0x0: bpcci({{ 472646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 482516SN/A NNPC = xc->readPC() + disp; 492580SN/A else 502580SN/A handle_annul 512486SN/A }}); 522486SN/A 0x2: bpccx({{ 532646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 542516SN/A NNPC = xc->readPC() + disp; 552580SN/A else 562580SN/A handle_annul 572486SN/A }}); 582482SN/A } 592516SN/A } 602516SN/A 0x2: Branch22::bicc({{ 612646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 622516SN/A NNPC = xc->readPC() + disp; 632580SN/A else 642580SN/A handle_annul 652516SN/A }}); 662516SN/A 0x3: decode RCOND2 672516SN/A { 682516SN/A format BranchSplit 692482SN/A { 702482SN/A 0x1: bpreq({{ 712591SN/A if(Rs1.sdw == 0) 722516SN/A NNPC = xc->readPC() + disp; 732580SN/A else 742580SN/A handle_annul 752482SN/A }}); 762482SN/A 0x2: bprle({{ 772591SN/A if(Rs1.sdw <= 0) 782516SN/A NNPC = xc->readPC() + disp; 792580SN/A else 802580SN/A handle_annul 812482SN/A }}); 822482SN/A 0x3: bprl({{ 832591SN/A if(Rs1.sdw < 0) 842516SN/A NNPC = xc->readPC() + disp; 852580SN/A else 862580SN/A handle_annul 872482SN/A }}); 882482SN/A 0x5: bprne({{ 892591SN/A if(Rs1.sdw != 0) 902516SN/A NNPC = xc->readPC() + disp; 912580SN/A else 922580SN/A handle_annul 932482SN/A }}); 942482SN/A 0x6: bprg({{ 952591SN/A if(Rs1.sdw > 0) 962516SN/A NNPC = xc->readPC() + disp; 972580SN/A else 982580SN/A handle_annul 992482SN/A }}); 1002482SN/A 0x7: bprge({{ 1012591SN/A if(Rs1.sdw >= 0) 1022516SN/A NNPC = xc->readPC() + disp; 1032580SN/A else 1042580SN/A handle_annul 1052482SN/A }}); 1062469SN/A } 1072482SN/A } 1082516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 1092516SN/A 0x4: SetHi::sethi({{Rd = imm;}}); 1102516SN/A 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 1112516SN/A 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 1122469SN/A } 1132516SN/A 0x1: Branch30::call({{ 1142516SN/A R15 = xc->readPC(); 1152516SN/A NNPC = R15 + disp; 1162469SN/A }}); 1172469SN/A 0x2: decode OP3 { 1182482SN/A format IntOp { 1192482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1202482SN/A 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 1212482SN/A 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 1222482SN/A 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 1232526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1242516SN/A 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 1252516SN/A 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 1262516SN/A 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 1272646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1282516SN/A 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 1292469SN/A 0x0A: umul({{ 1302516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1312646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1322482SN/A }}); 1332469SN/A 0x0B: smul({{ 1342516SN/A Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 1352646Ssaidi@eecs.umich.edu Y = Rd.sdw; 1362482SN/A }}); 1372646Ssaidi@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}}); 1382469SN/A 0x0D: udivx({{ 1392516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1402516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1412482SN/A }}); 1422469SN/A 0x0E: udiv({{ 1432516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1442482SN/A else 1452482SN/A { 1462646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1472482SN/A if(Rd.udw >> 32 != 0) 1482482SN/A Rd.udw = 0xFFFFFFFF; 1492482SN/A } 1502482SN/A }}); 1512482SN/A 0x0F: sdiv({{ 1522615SN/A if(Rs2_or_imm13.sdw == 0) 1532469SN/A fault = new DivisionByZero; 1542469SN/A else 1552482SN/A { 1562646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1572482SN/A if(Rd.udw<63:31> != 0) 1582482SN/A Rd.udw = 0x7FFFFFFF; 1592482SN/A else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 1602588SN/A Rd.udw = 0xFFFFFFFF80000000ULL; 1612482SN/A } 1622526SN/A }}); 1632469SN/A } 1642482SN/A format IntOpCc { 1652469SN/A 0x10: addcc({{ 1662516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1672469SN/A Rd = resTemp = Rs1 + val2;}}, 1682580SN/A {{(Rs1<31:0> + val2<31:0>)<32:>}}, 1692469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1702580SN/A {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 1712469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1722526SN/A ); 1732482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 1742482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 1752482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 1762469SN/A 0x14: subcc({{ 1772580SN/A int64_t val2 = Rs2_or_imm13; 1782580SN/A Rd = Rs1 - val2;}}, 1792580SN/A {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 1802580SN/A {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 1812580SN/A {{(~(Rs1<63:1> + (~val2)<63:1> + 1822580SN/A (Rs1 | ~val2)<0:>))<63:>}}, 1832580SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 1842526SN/A ); 1852482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 1862482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 1872482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 1882469SN/A 0x18: addccc({{ 1892516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 1902646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 1912469SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 1922580SN/A {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 1932469SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1942580SN/A {{(Rs1<63:1> + val2<63:1> + 1952580SN/A ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 1962469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1972526SN/A ); 1982469SN/A 0x1A: umulcc({{ 1992615SN/A uint64_t resTemp; 2002615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2012646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2022526SN/A {{0}},{{0}},{{0}},{{0}}); 2032469SN/A 0x1B: smulcc({{ 2042615SN/A int64_t resTemp; 2052615SN/A Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 2062646Ssaidi@eecs.umich.edu Y = resTemp<63:32>;}}, 2072526SN/A {{0}},{{0}},{{0}},{{0}}); 2082469SN/A 0x1C: subccc({{ 2092516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2102646Ssaidi@eecs.umich.edu int64_t carryin = Ccr<0:0>; 2112469SN/A Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 2122580SN/A {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 2132469SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2142580SN/A {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 2152469SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2162526SN/A ); 2172469SN/A 0x1D: udivxcc({{ 2182615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2192615SN/A else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 2202526SN/A ,{{0}},{{0}},{{0}},{{0}}); 2212469SN/A 0x1E: udivcc({{ 2222615SN/A uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2232516SN/A int32_t overflow; 2242469SN/A if(val2 == 0) fault = new DivisionByZero; 2252469SN/A else 2262224SN/A { 2272646Ssaidi@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2282516SN/A overflow = (resTemp<63:32> != 0); 2292516SN/A if(overflow) Rd = resTemp = 0xFFFFFFFF; 2302516SN/A else Rd = resTemp; 2312469SN/A } }}, 2322469SN/A {{0}}, 2332469SN/A {{overflow}}, 2342469SN/A {{0}}, 2352469SN/A {{0}} 2362526SN/A ); 2372469SN/A 0x1F: sdivcc({{ 2382615SN/A int32_t resTemp, val2 = Rs2_or_imm13.sdw; 2392516SN/A int32_t overflow, underflow; 2402469SN/A if(val2 == 0) fault = new DivisionByZero; 2412469SN/A else 2422469SN/A { 2432646Ssaidi@eecs.umich.edu Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2442516SN/A overflow = (resTemp<63:31> != 0); 2452516SN/A underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 2462516SN/A if(overflow) Rd = resTemp = 0x7FFFFFFF; 2472588SN/A else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; 2482516SN/A else Rd = resTemp; 2492469SN/A } }}, 2502469SN/A {{0}}, 2512469SN/A {{overflow || underflow}}, 2522469SN/A {{0}}, 2532469SN/A {{0}} 2542526SN/A ); 2552469SN/A 0x20: taddcc({{ 2562516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2572469SN/A Rd = resTemp = Rs1 + val2; 2582469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2592469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2602469SN/A {{overflow}}, 2612469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2622469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2632526SN/A ); 2642469SN/A 0x21: tsubcc({{ 2652516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2662469SN/A Rd = resTemp = Rs1 + val2; 2672469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2682516SN/A {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 2692469SN/A {{overflow}}, 2702469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2712469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2722526SN/A ); 2732469SN/A 0x22: taddcctv({{ 2742516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2752469SN/A Rd = resTemp = Rs1 + val2; 2762469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 2772469SN/A if(overflow) fault = new TagOverflow;}}, 2782469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2792469SN/A {{overflow}}, 2802469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2812469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2822526SN/A ); 2832469SN/A 0x23: tsubcctv({{ 2842516SN/A int64_t resTemp, val2 = Rs2_or_imm13; 2852469SN/A Rd = resTemp = Rs1 + val2; 2862469SN/A int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 2872469SN/A if(overflow) fault = new TagOverflow;}}, 2882469SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2892469SN/A {{overflow}}, 2902469SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2912469SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2922526SN/A ); 2932469SN/A 0x24: mulscc({{ 2942516SN/A int64_t resTemp, multiplicand = Rs2_or_imm13; 2952469SN/A int32_t multiplier = Rs1<31:0>; 2962469SN/A int32_t savedLSB = Rs1<0:>; 2972516SN/A multiplier = multiplier<31:1> | 2982646Ssaidi@eecs.umich.edu ((Ccr<3:3> 2992646Ssaidi@eecs.umich.edu ^ Ccr<1:1>) << 32); 3002646Ssaidi@eecs.umich.edu if(!Y<0:>) 3012469SN/A multiplicand = 0; 3022469SN/A Rd = resTemp = multiplicand + multiplier; 3032646Ssaidi@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31);}}, 3042469SN/A {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 3052469SN/A {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 3062469SN/A {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 3072469SN/A {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 3082526SN/A ); 3092526SN/A } 3102526SN/A format IntOp 3112526SN/A { 3122526SN/A 0x25: decode X { 3132526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3142526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3152469SN/A } 3162526SN/A 0x26: decode X { 3172526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3182526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3192526SN/A } 3202526SN/A 0x27: decode X { 3212526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3222526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3232526SN/A } 3242646Ssaidi@eecs.umich.edu // XXX might want a format rdipr thing here 3252646Ssaidi@eecs.umich.edu 0x28: rdasr({{ 3262646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 3272646Ssaidi@eecs.umich.edu }}); 3282938Sgblack@eecs.umich.edu 0x29: HPriv::rdhpr({{ 3292646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 3302646Ssaidi@eecs.umich.edu // access 3312646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 3322646Ssaidi@eecs.umich.edu }}); 3332938Sgblack@eecs.umich.edu 0x2A: Priv::rdpr({{ 3342646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 3352646Ssaidi@eecs.umich.edu // access 3362646Ssaidi@eecs.umich.edu Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 3372646Ssaidi@eecs.umich.edu }}); 3382526SN/A 0x2B: BasicOperate::flushw({{ 3392526SN/A if(NWindows - 2 - Cansave == 0) 3402526SN/A { 3412526SN/A if(Otherwin) 3422646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 3432526SN/A else 3442646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 3452526SN/A } 3462526SN/A }}); 3472526SN/A 0x2C: decode MOVCC3 3482469SN/A { 3492526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 3502526SN/A 0x1: decode CC 3512526SN/A { 3522526SN/A 0x0: movcci({{ 3532646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 3542591SN/A Rd = Rs2_or_imm11; 3552591SN/A else 3562591SN/A Rd = Rd; 3572526SN/A }}); 3582526SN/A 0x2: movccx({{ 3592646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 3602591SN/A Rd = Rs2_or_imm11; 3612591SN/A else 3622591SN/A Rd = Rd; 3632526SN/A }}); 3642224SN/A } 3652526SN/A } 3662526SN/A 0x2D: sdivx({{ 3672615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 3682615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 3692526SN/A }}); 3702526SN/A 0x2E: decode RS1 { 3712526SN/A 0x0: IntOp::popc({{ 3722526SN/A int64_t count = 0; 3732526SN/A uint64_t temp = Rs2_or_imm13; 3742526SN/A //Count the 1s in the front 4bits until none are left 3752526SN/A uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 3762526SN/A while(temp) 3772469SN/A { 3782526SN/A count += oneBits[temp & 0xF]; 3792526SN/A temp = temp >> 4; 3802516SN/A } 3812591SN/A Rd = count; 3822516SN/A }}); 3832526SN/A } 3842526SN/A 0x2F: decode RCOND3 3852526SN/A { 3862615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 3872615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 3882615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 3892615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 3902615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 3912615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 3922526SN/A } 3932646Ssaidi@eecs.umich.edu 0x30: wrasr({{ 3942646Ssaidi@eecs.umich.edu xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 3952646Ssaidi@eecs.umich.edu }}); 3962526SN/A 0x31: decode FCN { 3972526SN/A 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 3982526SN/A 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 3992526SN/A } 4002938Sgblack@eecs.umich.edu 0x32: Priv::wrpr({{ 4012646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv 4022646Ssaidi@eecs.umich.edu // access 4032938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 4042646Ssaidi@eecs.umich.edu }}); 4052938Sgblack@eecs.umich.edu 0x33: HPriv::wrhpr({{ 4062646Ssaidi@eecs.umich.edu // XXX Need to protect with format that traps non-priv/priv 4072646Ssaidi@eecs.umich.edu // access 4082938Sgblack@eecs.umich.edu fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 4092646Ssaidi@eecs.umich.edu }}); 4102526SN/A 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 4112526SN/A 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 4122526SN/A 0x38: Branch::jmpl({{ 4132526SN/A Addr target = Rs1 + Rs2_or_imm13; 4142526SN/A if(target & 0x3) 4152526SN/A fault = new MemAddressNotAligned; 4162526SN/A else 4172526SN/A { 4182526SN/A Rd = xc->readPC(); 4192526SN/A NNPC = target; 4202526SN/A } 4212526SN/A }}); 4222526SN/A 0x39: Branch::return({{ 4232561SN/A //If both MemAddressNotAligned and 4242561SN/A //a fill trap happen, it's not clear 4252561SN/A //which one should be returned. 4262526SN/A Addr target = Rs1 + Rs2_or_imm13; 4272526SN/A if(target & 0x3) 4282526SN/A fault = new MemAddressNotAligned; 4292526SN/A else 4302526SN/A NNPC = target; 4312561SN/A if(fault == NoFault) 4322561SN/A { 4332561SN/A //CWP should be set directly so that it always happens 4342561SN/A //Also, this will allow writing to the new window and 4352561SN/A //reading from the old one 4362561SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 4372561SN/A if(Canrestore == 0) 4382561SN/A { 4392561SN/A if(Otherwin) 4402646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 4412561SN/A else 4422646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 4432561SN/A } 4442561SN/A else 4452561SN/A { 4462561SN/A Rd = Rs1 + Rs2_or_imm13; 4472561SN/A Cansave = Cansave + 1; 4482561SN/A Canrestore = Canrestore - 1; 4492561SN/A } 4502561SN/A //This is here to make sure the CWP is written 4512561SN/A //no matter what. This ensures that the results 4522561SN/A //are written in the new window as well. 4532561SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 4542561SN/A } 4552526SN/A }}); 4562526SN/A 0x3A: decode CC 4572526SN/A { 4582526SN/A 0x0: Trap::tcci({{ 4592646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 4602561SN/A { 4612561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 4622561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 4632526SN/A#if FULL_SYSTEM 4642561SN/A fault = new TrapInstruction(lTrapNum); 4652526SN/A#else 4662561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 4672561SN/A xc->syscall(R1); 4682561SN/A#endif 4692561SN/A } 4702526SN/A }}); 4712526SN/A 0x2: Trap::tccx({{ 4722646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 4732561SN/A { 4742561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 4752561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 4762526SN/A#if FULL_SYSTEM 4772561SN/A fault = new TrapInstruction(lTrapNum); 4782526SN/A#else 4792561SN/A DPRINTF(Sparc, "The syscall number is %d\n", R1); 4802561SN/A xc->syscall(R1); 4812561SN/A#endif 4822526SN/A } 4832526SN/A }}); 4842526SN/A } 4852526SN/A 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 4862526SN/A 0x3C: save({{ 4872526SN/A //CWP should be set directly so that it always happens 4882526SN/A //Also, this will allow writing to the new window and 4892526SN/A //reading from the old one 4902526SN/A if(Cansave == 0) 4912526SN/A { 4922526SN/A if(Otherwin) 4932646Ssaidi@eecs.umich.edu fault = new SpillNOther(Wstate<5:3>); 4942526SN/A else 4952646Ssaidi@eecs.umich.edu fault = new SpillNNormal(Wstate<2:0>); 4962526SN/A Cwp = (Cwp + 2) % NWindows; 4972526SN/A } 4982526SN/A else if(Cleanwin - Canrestore == 0) 4992526SN/A { 5002526SN/A Cwp = (Cwp + 1) % NWindows; 5012526SN/A fault = new CleanWindow; 5022526SN/A } 5032526SN/A else 5042526SN/A { 5052526SN/A Cwp = (Cwp + 1) % NWindows; 5062526SN/A Rd = Rs1 + Rs2_or_imm13; 5072561SN/A Cansave = Cansave - 1; 5082561SN/A Canrestore = Canrestore + 1; 5092526SN/A } 5102526SN/A //This is here to make sure the CWP is written 5112526SN/A //no matter what. This ensures that the results 5122526SN/A //are written in the new window as well. 5132526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 5142526SN/A }}); 5152526SN/A 0x3D: restore({{ 5162526SN/A //CWP should be set directly so that it always happens 5172526SN/A //Also, this will allow writing to the new window and 5182526SN/A //reading from the old one 5192526SN/A Cwp = (Cwp - 1 + NWindows) % NWindows; 5202526SN/A if(Canrestore == 0) 5212526SN/A { 5222526SN/A if(Otherwin) 5232646Ssaidi@eecs.umich.edu fault = new FillNOther(Wstate<5:3>); 5242526SN/A else 5252646Ssaidi@eecs.umich.edu fault = new FillNNormal(Wstate<2:0>); 5262526SN/A } 5272526SN/A else 5282526SN/A { 5292526SN/A Rd = Rs1 + Rs2_or_imm13; 5302561SN/A Cansave = Cansave + 1; 5312561SN/A Canrestore = Canrestore - 1; 5322526SN/A } 5332526SN/A //This is here to make sure the CWP is written 5342526SN/A //no matter what. This ensures that the results 5352526SN/A //are written in the new window as well. 5362526SN/A xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 5372526SN/A }}); 5382526SN/A 0x3E: decode FCN { 5392526SN/A 0x0: Priv::done({{ 5402526SN/A if(Tl == 0) 5412526SN/A return new IllegalInstruction; 5422646Ssaidi@eecs.umich.edu 5432646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 5442646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 5452646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 5462646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 5472646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 5482646Ssaidi@eecs.umich.edu NPC = Tnpc; 5492646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 5502526SN/A Tl = Tl - 1; 5512526SN/A }}); 5522938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 5532526SN/A if(Tl == 0) 5542526SN/A return new IllegalInstruction; 5552646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 5562646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 5572646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 5582646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 5592646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 5602646Ssaidi@eecs.umich.edu NPC = Tpc; 5612646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 5622526SN/A Tl = Tl - 1; 5632526SN/A }}); 5642526SN/A } 5652526SN/A } 5662469SN/A } 5672469SN/A 0x3: decode OP3 { 5682526SN/A format Load { 5692526SN/A 0x00: lduw({{Rd = Mem;}}, {{32}}); 5702526SN/A 0x01: ldub({{Rd = Mem;}}, {{8}}); 5712526SN/A 0x02: lduh({{Rd = Mem;}}, {{16}}); 5722526SN/A 0x03: ldd({{ 5732526SN/A uint64_t val = Mem; 5742526SN/A RdLow = val<31:0>; 5752526SN/A RdHigh = val<63:32>; 5762526SN/A }}, {{64}}); 5772526SN/A } 5782526SN/A format Store { 5792526SN/A 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 5802526SN/A 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 5812526SN/A 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 5822526SN/A 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 5832526SN/A } 5842526SN/A format Load { 5852526SN/A 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 5862526SN/A 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 5872526SN/A 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 5882526SN/A 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 5892526SN/A 0x0D: ldstub({{ 5902526SN/A Rd = Mem; 5912526SN/A Mem = 0xFF; 5922526SN/A }}, {{8}}); 5932526SN/A } 5942526SN/A 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 5952526SN/A 0x0F: LoadStore::swap({{ 5962526SN/A uint32_t temp = Rd; 5972526SN/A Rd = Mem; 5982526SN/A Mem = temp; 5992526SN/A }}, {{32}}); 6002526SN/A format Load { 6012526SN/A 0x10: lduwa({{Rd = Mem;}}, {{32}}); 6022526SN/A 0x11: lduba({{Rd = Mem;}}, {{8}}); 6032526SN/A 0x12: lduha({{Rd = Mem;}}, {{16}}); 6042526SN/A 0x13: ldda({{ 6052526SN/A uint64_t val = Mem; 6062526SN/A RdLow = val<31:0>; 6072526SN/A RdHigh = val<63:32>; 6082526SN/A }}, {{64}}); 6092526SN/A } 6102526SN/A format Store { 6112526SN/A 0x14: stwa({{Mem = Rd;}}, {{32}}); 6122526SN/A 0x15: stba({{Mem = Rd;}}, {{8}}); 6132526SN/A 0x16: stha({{Mem = Rd;}}, {{16}}); 6142526SN/A 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 6152526SN/A } 6162526SN/A format Load { 6172526SN/A 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 6182526SN/A 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 6192526SN/A 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 6202526SN/A 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 6212526SN/A } 6222526SN/A 0x1D: LoadStore::ldstuba({{ 6232526SN/A Rd = Mem; 6242526SN/A Mem = 0xFF; 6252526SN/A }}, {{8}}); 6262526SN/A 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 6272526SN/A 0x1F: LoadStore::swapa({{ 6282526SN/A uint32_t temp = Rd; 6292526SN/A Rd = Mem; 6302526SN/A Mem = temp; 6312526SN/A }}, {{32}}); 6322526SN/A format Trap { 6332526SN/A 0x20: ldf({{fault = new FpDisabled;}}); 6342526SN/A 0x21: decode X { 6352561SN/A 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 6362561SN/A 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 6372469SN/A } 6382526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 6392526SN/A 0x23: lddf({{fault = new FpDisabled;}}); 6402526SN/A 0x24: stf({{fault = new FpDisabled;}}); 6412526SN/A 0x25: decode X { 6422561SN/A 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 6432561SN/A 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 6442526SN/A } 6452526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 6462526SN/A 0x27: stdf({{fault = new FpDisabled;}}); 6472526SN/A 0x2D: Nop::prefetch({{ }}); 6482526SN/A 0x30: ldfa({{return new FpDisabled;}}); 6492526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 6502526SN/A 0x33: lddfa({{fault = new FpDisabled;}}); 6512526SN/A 0x34: stfa({{fault = new FpDisabled;}}); 6522526SN/A 0x35: stqfa({{fault = new FpDisabled;}}); 6532526SN/A 0x36: stdfa({{fault = new FpDisabled;}}); 6542526SN/A 0x3C: Cas::casa({{ 6552526SN/A uint64_t val = Mem.uw; 6562526SN/A if(Rs2.uw == val) 6572526SN/A Mem.uw = Rd.uw; 6582526SN/A Rd.uw = val; 6592526SN/A }}); 6602526SN/A 0x3D: Nop::prefetcha({{ }}); 6612526SN/A 0x3E: Cas::casxa({{ 6622526SN/A uint64_t val = Mem.udw; 6632526SN/A if(Rs2 == val) 6642526SN/A Mem.udw = Rd; 6652526SN/A Rd = val; 6662526SN/A }}); 6672526SN/A } 6682469SN/A } 6692022SN/A} 670