decoder.isa revision 2588
1//////////////////////////////////////////////////////////////////// 2// 3// The actual decoder specification 4// 5 6decode OP default Unknown::unknown() 7{ 8 0x0: decode OP2 9 { 10 //Throw an illegal instruction acception 11 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 12 0x1: decode BPCC 13 { 14 format Branch19 15 { 16 0x0: bpcci({{ 17 if(passesCondition(CcrIcc, COND2)) 18 NNPC = xc->readPC() + disp; 19 else 20 handle_annul 21 }}); 22 0x2: bpccx({{ 23 if(passesCondition(CcrXcc, COND2)) 24 NNPC = xc->readPC() + disp; 25 else 26 handle_annul 27 }}); 28 } 29 } 30 0x2: Branch22::bicc({{ 31 if(passesCondition(CcrIcc, COND2)) 32 NNPC = xc->readPC() + disp; 33 else 34 handle_annul 35 }}); 36 0x3: decode RCOND2 37 { 38 format BranchSplit 39 { 40 0x1: bpreq({{ 41 if(Rs1 == 0) 42 NNPC = xc->readPC() + disp; 43 else 44 handle_annul 45 }}); 46 0x2: bprle({{ 47 if(Rs1 <= 0) 48 NNPC = xc->readPC() + disp; 49 else 50 handle_annul 51 }}); 52 0x3: bprl({{ 53 if(Rs1 < 0) 54 NNPC = xc->readPC() + disp; 55 else 56 handle_annul 57 }}); 58 0x5: bprne({{ 59 if(Rs1 != 0) 60 NNPC = xc->readPC() + disp; 61 else 62 handle_annul 63 }}); 64 0x6: bprg({{ 65 if(Rs1 > 0) 66 NNPC = xc->readPC() + disp; 67 else 68 handle_annul 69 }}); 70 0x7: bprge({{ 71 if(Rs1 >= 0) 72 NNPC = xc->readPC() + disp; 73 else 74 handle_annul 75 }}); 76 } 77 } 78 //SETHI (or NOP if rd == 0 and imm == 0) 79 0x4: SetHi::sethi({{Rd = imm;}}); 80 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 81 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 82 } 83 0x1: Branch30::call({{ 84 R15 = xc->readPC(); 85 NNPC = R15 + disp; 86 }}); 87 0x2: decode OP3 { 88 format IntOp { 89 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 90 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 91 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 92 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 93 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 94 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 95 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 96 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 97 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); 98 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 99 0x0A: umul({{ 100 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 101 YValue = Rd<63:32>; 102 }}); 103 0x0B: smul({{ 104 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 105 YValue = Rd.sdw; 106 }}); 107 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); 108 0x0D: udivx({{ 109 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 110 else Rd.udw = Rs1.udw / Rs2_or_imm13; 111 }}); 112 0x0E: udiv({{ 113 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 114 else 115 { 116 Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 117 if(Rd.udw >> 32 != 0) 118 Rd.udw = 0xFFFFFFFF; 119 } 120 }}); 121 0x0F: sdiv({{ 122 if(Rs2_or_imm13 == 0) 123 fault = new DivisionByZero; 124 else 125 { 126 Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13; 127 if(Rd.udw<63:31> != 0) 128 Rd.udw = 0x7FFFFFFF; 129 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 130 Rd.udw = 0xFFFFFFFF80000000ULL; 131 } 132 }}); 133 } 134 format IntOpCc { 135 0x10: addcc({{ 136 int64_t resTemp, val2 = Rs2_or_imm13; 137 Rd = resTemp = Rs1 + val2;}}, 138 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 139 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 140 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 141 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 142 ); 143 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 144 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 145 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 146 0x14: subcc({{ 147 int64_t val2 = Rs2_or_imm13; 148 Rd = Rs1 - val2;}}, 149 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 150 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 151 {{(~(Rs1<63:1> + (~val2)<63:1> + 152 (Rs1 | ~val2)<0:>))<63:>}}, 153 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 154 ); 155 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 156 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 157 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 158 0x18: addccc({{ 159 int64_t resTemp, val2 = Rs2_or_imm13; 160 int64_t carryin = CcrIccC; 161 Rd = resTemp = Rs1 + val2 + carryin;}}, 162 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 163 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 164 {{(Rs1<63:1> + val2<63:1> + 165 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 166 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 167 ); 168 0x1A: umulcc({{ 169 uint64_t resTemp, val2 = Rs2_or_imm13; 170 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 171 YValue = resTemp<63:32>;}}, 172 {{0}},{{0}},{{0}},{{0}}); 173 0x1B: smulcc({{ 174 int64_t resTemp, val2 = Rs2_or_imm13; 175 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 176 YValue = resTemp<63:32>;}}, 177 {{0}},{{0}},{{0}},{{0}}); 178 0x1C: subccc({{ 179 int64_t resTemp, val2 = Rs2_or_imm13; 180 int64_t carryin = CcrIccC; 181 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 182 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 183 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 184 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 185 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 186 ); 187 0x1D: udivxcc({{ 188 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 189 else Rd = Rs1.udw / Rs2_or_imm13;}} 190 ,{{0}},{{0}},{{0}},{{0}}); 191 0x1E: udivcc({{ 192 uint32_t resTemp, val2 = Rs2_or_imm13; 193 int32_t overflow; 194 if(val2 == 0) fault = new DivisionByZero; 195 else 196 { 197 resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; 198 overflow = (resTemp<63:32> != 0); 199 if(overflow) Rd = resTemp = 0xFFFFFFFF; 200 else Rd = resTemp; 201 } }}, 202 {{0}}, 203 {{overflow}}, 204 {{0}}, 205 {{0}} 206 ); 207 0x1F: sdivcc({{ 208 int32_t resTemp, val2 = Rs2_or_imm13; 209 int32_t overflow, underflow; 210 if(val2 == 0) fault = new DivisionByZero; 211 else 212 { 213 Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; 214 overflow = (resTemp<63:31> != 0); 215 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 216 if(overflow) Rd = resTemp = 0x7FFFFFFF; 217 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; 218 else Rd = resTemp; 219 } }}, 220 {{0}}, 221 {{overflow || underflow}}, 222 {{0}}, 223 {{0}} 224 ); 225 0x20: taddcc({{ 226 int64_t resTemp, val2 = Rs2_or_imm13; 227 Rd = resTemp = Rs1 + val2; 228 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 229 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 230 {{overflow}}, 231 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 232 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 233 ); 234 0x21: tsubcc({{ 235 int64_t resTemp, val2 = Rs2_or_imm13; 236 Rd = resTemp = Rs1 + val2; 237 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 238 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 239 {{overflow}}, 240 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 241 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 242 ); 243 0x22: taddcctv({{ 244 int64_t resTemp, val2 = Rs2_or_imm13; 245 Rd = resTemp = Rs1 + val2; 246 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 247 if(overflow) fault = new TagOverflow;}}, 248 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 249 {{overflow}}, 250 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 251 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 252 ); 253 0x23: tsubcctv({{ 254 int64_t resTemp, val2 = Rs2_or_imm13; 255 Rd = resTemp = Rs1 + val2; 256 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 257 if(overflow) fault = new TagOverflow;}}, 258 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 259 {{overflow}}, 260 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 261 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 262 ); 263 0x24: mulscc({{ 264 int64_t resTemp, multiplicand = Rs2_or_imm13; 265 int32_t multiplier = Rs1<31:0>; 266 int32_t savedLSB = Rs1<0:>; 267 multiplier = multiplier<31:1> | 268 ((CcrIccN 269 ^ CcrIccV) << 32); 270 if(!YValue<0:>) 271 multiplicand = 0; 272 Rd = resTemp = multiplicand + multiplier; 273 YValue = YValue<31:1> | (savedLSB << 31);}}, 274 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 275 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 276 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 277 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 278 ); 279 } 280 format IntOp 281 { 282 0x25: decode X { 283 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 284 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 285 } 286 0x26: decode X { 287 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 288 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 289 } 290 0x27: decode X { 291 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 292 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 293 } 294 0x28: decode RS1 { 295 0x0: rdy({{Rd = YValue;}}); 296 0x2: rdccr({{Rd = Ccr;}}); 297 0x3: rdasi({{Rd = Asi;}}); 298 0x4: PrivTick::rdtick({{Rd = Tick;}}); 299 0x5: rdpc({{Rd = xc->readPC();}}); 300 0x6: rdfprs({{Rd = Fprs;}}); 301 0xF: decode I { 302 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); 303 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); 304 } 305 } 306 0x2A: decode RS1 { 307 format Priv 308 { 309 0x0: rdprtpc({{ 310 Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 311 }}); 312 0x1: rdprtnpc({{ 313 Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 314 }}); 315 0x2: rdprtstate({{ 316 Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); 317 }}); 318 0x3: rdprtt({{ 319 Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); 320 }}); 321 0x4: rdprtick({{Rd = Tick;}}); 322 0x5: rdprtba({{Rd = Tba;}}); 323 0x6: rdprpstate({{Rd = Pstate;}}); 324 0x7: rdprtl({{Rd = Tl;}}); 325 0x8: rdprpil({{Rd = Pil;}}); 326 0x9: rdprcwp({{Rd = Cwp;}}); 327 0xA: rdprcansave({{Rd = Cansave;}}); 328 0xB: rdprcanrestore({{Rd = Canrestore;}}); 329 0xC: rdprcleanwin({{Rd = Cleanwin;}}); 330 0xD: rdprotherwin({{Rd = Otherwin;}}); 331 0xE: rdprwstate({{Rd = Wstate;}}); 332 } 333 //The floating point queue isn't implemented right now. 334 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); 335 0x1F: Priv::rdprver({{Rd = Ver;}}); 336 } 337 0x2B: BasicOperate::flushw({{ 338 if(NWindows - 2 - Cansave == 0) 339 { 340 if(Otherwin) 341 fault = new SpillNOther(WstateOther); 342 else 343 fault = new SpillNNormal(WstateNormal); 344 } 345 }}); 346 0x2C: decode MOVCC3 347 { 348 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 349 0x1: decode CC 350 { 351 0x0: movcci({{ 352 if(passesCondition(CcrIcc, COND4)) 353 Rd = (I ? SIMM11 : RS2); 354 }}); 355 0x2: movccx({{ 356 if(passesCondition(CcrXcc, COND4)) 357 Rd = (I ? SIMM11 : RS2); 358 }}); 359 } 360 } 361 0x2D: sdivx({{ 362 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 363 else Rd.sdw = Rs1.sdw / Rs2_or_imm13; 364 }}); 365 0x2E: decode RS1 { 366 0x0: IntOp::popc({{ 367 int64_t count = 0; 368 uint64_t temp = Rs2_or_imm13; 369 //Count the 1s in the front 4bits until none are left 370 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 371 while(temp) 372 { 373 count += oneBits[temp & 0xF]; 374 temp = temp >> 4; 375 } 376 }}); 377 } 378 0x2F: decode RCOND3 379 { 380 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); 381 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); 382 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); 383 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); 384 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); 385 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); 386 } 387 0x30: decode RD { 388 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 389 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 390 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 391 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); 392 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); 393 } 394 0x31: decode FCN { 395 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 396 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 397 } 398 0x32: decode RD { 399 format Priv 400 { 401 0x0: wrprtpc({{ 402 xc->setMiscReg(MISCREG_TPC_BASE + Tl, 403 Rs1 ^ Rs2_or_imm13); 404 }}); 405 0x1: wrprtnpc({{ 406 xc->setMiscReg(MISCREG_TNPC_BASE + Tl, 407 Rs1 ^ Rs2_or_imm13); 408 }}); 409 0x2: wrprtstate({{ 410 xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, 411 Rs1 ^ Rs2_or_imm13); 412 }}); 413 0x3: wrprtt({{ 414 xc->setMiscReg(MISCREG_TT_BASE + Tl, 415 Rs1 ^ Rs2_or_imm13); 416 }}); 417 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 418 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 419 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 420 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); 421 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 422 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 423 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 424 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 425 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 426 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 427 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 428 } 429 } 430 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 431 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 432 0x38: Branch::jmpl({{ 433 Addr target = Rs1 + Rs2_or_imm13; 434 if(target & 0x3) 435 fault = new MemAddressNotAligned; 436 else 437 { 438 Rd = xc->readPC(); 439 NNPC = target; 440 } 441 }}); 442 0x39: Branch::return({{ 443 //If both MemAddressNotAligned and 444 //a fill trap happen, it's not clear 445 //which one should be returned. 446 Addr target = Rs1 + Rs2_or_imm13; 447 if(target & 0x3) 448 fault = new MemAddressNotAligned; 449 else 450 NNPC = target; 451 if(fault == NoFault) 452 { 453 //CWP should be set directly so that it always happens 454 //Also, this will allow writing to the new window and 455 //reading from the old one 456 Cwp = (Cwp - 1 + NWindows) % NWindows; 457 if(Canrestore == 0) 458 { 459 if(Otherwin) 460 fault = new FillNOther(WstateOther); 461 else 462 fault = new FillNNormal(WstateNormal); 463 } 464 else 465 { 466 Rd = Rs1 + Rs2_or_imm13; 467 Cansave = Cansave + 1; 468 Canrestore = Canrestore - 1; 469 } 470 //This is here to make sure the CWP is written 471 //no matter what. This ensures that the results 472 //are written in the new window as well. 473 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 474 } 475 }}); 476 0x3A: decode CC 477 { 478 0x0: Trap::tcci({{ 479 if(passesCondition(CcrIcc, COND2)) 480 { 481 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 482 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 483#if FULL_SYSTEM 484 fault = new TrapInstruction(lTrapNum); 485#else 486 DPRINTF(Sparc, "The syscall number is %d\n", R1); 487 xc->syscall(R1); 488#endif 489 } 490 else 491 { 492 DPRINTF(Sparc, "Didn't fire on %s\n", CondTestAbbrev[machInst<25:28>]); 493 } 494 }}); 495 0x2: Trap::tccx({{ 496 if(passesCondition(CcrXcc, COND2)) 497 { 498 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 499 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 500#if FULL_SYSTEM 501 fault = new TrapInstruction(lTrapNum); 502#else 503 DPRINTF(Sparc, "The syscall number is %d\n", R1); 504 xc->syscall(R1); 505#endif 506 } 507 }}); 508 } 509 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 510 0x3C: save({{ 511 //CWP should be set directly so that it always happens 512 //Also, this will allow writing to the new window and 513 //reading from the old one 514 if(Cansave == 0) 515 { 516 if(Otherwin) 517 fault = new SpillNOther(WstateOther); 518 else 519 fault = new SpillNNormal(WstateNormal); 520 Cwp = (Cwp + 2) % NWindows; 521 } 522 else if(Cleanwin - Canrestore == 0) 523 { 524 Cwp = (Cwp + 1) % NWindows; 525 fault = new CleanWindow; 526 } 527 else 528 { 529 Cwp = (Cwp + 1) % NWindows; 530 Rd = Rs1 + Rs2_or_imm13; 531 Cansave = Cansave - 1; 532 Canrestore = Canrestore + 1; 533 } 534 //This is here to make sure the CWP is written 535 //no matter what. This ensures that the results 536 //are written in the new window as well. 537 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 538 }}); 539 0x3D: restore({{ 540 //CWP should be set directly so that it always happens 541 //Also, this will allow writing to the new window and 542 //reading from the old one 543 Cwp = (Cwp - 1 + NWindows) % NWindows; 544 if(Canrestore == 0) 545 { 546 if(Otherwin) 547 fault = new FillNOther(WstateOther); 548 else 549 fault = new FillNNormal(WstateNormal); 550 } 551 else 552 { 553 Rd = Rs1 + Rs2_or_imm13; 554 Cansave = Cansave + 1; 555 Canrestore = Canrestore - 1; 556 } 557 //This is here to make sure the CWP is written 558 //no matter what. This ensures that the results 559 //are written in the new window as well. 560 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 561 }}); 562 0x3E: decode FCN { 563 0x0: Priv::done({{ 564 if(Tl == 0) 565 return new IllegalInstruction; 566 Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); 567 Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); 568 Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); 569 Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); 570 NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 571 NNPC = NPC + 4; 572 Tl = Tl - 1; 573 }}); 574 0x1: BasicOperate::retry({{ 575 if(Tl == 0) 576 return new IllegalInstruction; 577 Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); 578 Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); 579 Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); 580 Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); 581 NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 582 NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 583 Tl = Tl - 1; 584 }}); 585 } 586 } 587 } 588 0x3: decode OP3 { 589 format Load { 590 0x00: lduw({{Rd = Mem;}}, {{32}}); 591 0x01: ldub({{Rd = Mem;}}, {{8}}); 592 0x02: lduh({{Rd = Mem;}}, {{16}}); 593 0x03: ldd({{ 594 uint64_t val = Mem; 595 RdLow = val<31:0>; 596 RdHigh = val<63:32>; 597 }}, {{64}}); 598 } 599 format Store { 600 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 601 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 602 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 603 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 604 } 605 format Load { 606 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 607 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 608 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 609 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 610 0x0D: ldstub({{ 611 Rd = Mem; 612 Mem = 0xFF; 613 }}, {{8}}); 614 } 615 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 616 0x0F: LoadStore::swap({{ 617 uint32_t temp = Rd; 618 Rd = Mem; 619 Mem = temp; 620 }}, {{32}}); 621 format Load { 622 0x10: lduwa({{Rd = Mem;}}, {{32}}); 623 0x11: lduba({{Rd = Mem;}}, {{8}}); 624 0x12: lduha({{Rd = Mem;}}, {{16}}); 625 0x13: ldda({{ 626 uint64_t val = Mem; 627 RdLow = val<31:0>; 628 RdHigh = val<63:32>; 629 }}, {{64}}); 630 } 631 format Store { 632 0x14: stwa({{Mem = Rd;}}, {{32}}); 633 0x15: stba({{Mem = Rd;}}, {{8}}); 634 0x16: stha({{Mem = Rd;}}, {{16}}); 635 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 636 } 637 format Load { 638 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 639 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 640 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 641 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 642 } 643 0x1D: LoadStore::ldstuba({{ 644 Rd = Mem; 645 Mem = 0xFF; 646 }}, {{8}}); 647 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 648 0x1F: LoadStore::swapa({{ 649 uint32_t temp = Rd; 650 Rd = Mem; 651 Mem = temp; 652 }}, {{32}}); 653 format Trap { 654 0x20: ldf({{fault = new FpDisabled;}}); 655 0x21: decode X { 656 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 657 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 658 } 659 0x22: ldqf({{fault = new FpDisabled;}}); 660 0x23: lddf({{fault = new FpDisabled;}}); 661 0x24: stf({{fault = new FpDisabled;}}); 662 0x25: decode X { 663 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 664 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 665 } 666 0x26: stqf({{fault = new FpDisabled;}}); 667 0x27: stdf({{fault = new FpDisabled;}}); 668 0x2D: Nop::prefetch({{ }}); 669 0x30: ldfa({{return new FpDisabled;}}); 670 0x32: ldqfa({{fault = new FpDisabled;}}); 671 0x33: lddfa({{fault = new FpDisabled;}}); 672 0x34: stfa({{fault = new FpDisabled;}}); 673 0x35: stqfa({{fault = new FpDisabled;}}); 674 0x36: stdfa({{fault = new FpDisabled;}}); 675 0x3C: Cas::casa({{ 676 uint64_t val = Mem.uw; 677 if(Rs2.uw == val) 678 Mem.uw = Rd.uw; 679 Rd.uw = val; 680 }}); 681 0x3D: Nop::prefetcha({{ }}); 682 0x3E: Cas::casxa({{ 683 uint64_t val = Mem.udw; 684 if(Rs2 == val) 685 Mem.udw = Rd; 686 Rd = val; 687 }}); 688 } 689 } 690} 691