decoder.isa revision 2516
1//////////////////////////////////////////////////////////////////// 2// 3// The actual decoder specification 4// 5 6decode OP default Unknown::unknown() 7{ 8 0x0: decode OP2 9 { 10 //Throw an illegal instruction acception 11 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 12 0x1: decode BPCC 13 { 14 format Branch19 15 { 16 0x0: bpcci({{ 17 NNPC = xc->readNextNPC(); 18 if(passesCondition(CcrIcc, COND2)) 19 NNPC = xc->readPC() + disp; 20 }}); 21 0x2: bpccx({{ 22 if(passesCondition(CcrXcc, COND2)) 23 NNPC = xc->readPC() + disp; 24 }}); 25 } 26 } 27 0x2: Branch22::bicc({{ 28 if(passesCondition(CcrIcc, COND2)) 29 NNPC = xc->readPC() + disp; 30 }}); 31 0x3: decode RCOND2 32 { 33 format BranchSplit 34 { 35 0x1: bpreq({{ 36 if(Rs1 == 0) 37 NNPC = xc->readPC() + disp; 38 }}); 39 0x2: bprle({{ 40 if(Rs1 <= 0) 41 NNPC = xc->readPC() + disp; 42 }}); 43 0x3: bprl({{ 44 if(Rs1 < 0) 45 NNPC = xc->readPC() + disp; 46 }}); 47 0x5: bprne({{ 48 if(Rs1 != 0) 49 NNPC = xc->readPC() + disp; 50 }}); 51 0x6: bprg({{ 52 if(Rs1 > 0) 53 NNPC = xc->readPC() + disp; 54 }}); 55 0x7: bprge({{ 56 if(Rs1 >= 0) 57 NNPC = xc->readPC() + disp; 58 }}); 59 } 60 } 61 //SETHI (or NOP if rd == 0 and imm == 0) 62 0x4: SetHi::sethi({{Rd = imm;}}); 63 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 64 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 65 } 66 0x1: Branch30::call({{ 67 //branch here 68 R15 = xc->readPC(); 69 NNPC = R15 + disp; 70 }}); 71 0x2: decode OP3 { 72 format IntOp { 73 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 74 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 75 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 76 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 77 0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm13)+1;}}); 78 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 79 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 80 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 81 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); 82 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 83 0x0A: umul({{ 84 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 85 YValue = Rd<63:32>; 86 }}); 87 0x0B: smul({{ 88 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 89 YValue = Rd.sdw; 90 }}); 91 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); 92 0x0D: udivx({{ 93 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 94 else Rd.udw = Rs1.udw / Rs2_or_imm13; 95 }}); 96 0x0E: udiv({{ 97 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 98 else 99 { 100 Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 101 if(Rd.udw >> 32 != 0) 102 Rd.udw = 0xFFFFFFFF; 103 } 104 }}); 105 0x0F: sdiv({{ 106 if(Rs2_or_imm13 == 0) 107 fault = new DivisionByZero; 108 else 109 { 110 Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13; 111 if(Rd.udw<63:31> != 0) 112 Rd.udw = 0x7FFFFFFF; 113 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 114 Rd.udw = 0xFFFFFFFF80000000; 115 } 116 }});//SDIV 117 } 118 format IntOpCc { 119 0x10: addcc({{ 120 int64_t resTemp, val2 = Rs2_or_imm13; 121 Rd = resTemp = Rs1 + val2;}}, 122 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 123 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 124 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 125 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 126 );//ADDcc 127 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 128 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 129 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 130 0x14: subcc({{ 131 int64_t resTemp, val2 = Rs2_or_imm13; 132 Rd = resTemp = Rs1 - val2;}}, 133 {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, 134 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 135 {{(((Rs1 >> 1) + (~val2) >> 1) + 136 ((Rs1 | ~val2) & 0x1))<63:>}}, 137 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 138 );//SUBcc 139 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 140 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 141 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 142 0x18: addccc({{ 143 int64_t resTemp, val2 = Rs2_or_imm13; 144 int64_t carryin = CcrIccC; 145 Rd = resTemp = Rs1 + val2 + carryin;}}, 146 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 147 + carryin)}}, 148 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 149 {{((Rs1 >> 1) + (val2 >> 1) + 150 ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, 151 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 152 );//ADDCcc 153 0x1A: umulcc({{ 154 uint64_t resTemp, val2 = Rs2_or_imm13; 155 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 156 YValue = resTemp<63:32>;}}, 157 {{0}},{{0}},{{0}},{{0}});//UMULcc 158 0x1B: smulcc({{ 159 int64_t resTemp, val2 = Rs2_or_imm13; 160 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 161 YValue = resTemp<63:32>;}} 162 ,{{0}},{{0}},{{0}},{{0}});//SMULcc 163 0x1C: subccc({{ 164 int64_t resTemp, val2 = Rs2_or_imm13; 165 int64_t carryin = CcrIccC; 166 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 167 {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, 168 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 169 {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, 170 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 171 );//SUBCcc 172 0x1D: udivxcc({{ 173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 174 else Rd = Rs1.udw / Rs2_or_imm13;}} 175 ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc 176 0x1E: udivcc({{ 177 uint32_t resTemp, val2 = Rs2_or_imm13; 178 int32_t overflow; 179 if(val2 == 0) fault = new DivisionByZero; 180 else 181 { 182 resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; 183 overflow = (resTemp<63:32> != 0); 184 if(overflow) Rd = resTemp = 0xFFFFFFFF; 185 else Rd = resTemp; 186 } }}, 187 {{0}}, 188 {{overflow}}, 189 {{0}}, 190 {{0}} 191 );//UDIVcc 192 0x1F: sdivcc({{ 193 int32_t resTemp, val2 = Rs2_or_imm13; 194 int32_t overflow, underflow; 195 if(val2 == 0) fault = new DivisionByZero; 196 else 197 { 198 Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; 199 overflow = (resTemp<63:31> != 0); 200 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 201 if(overflow) Rd = resTemp = 0x7FFFFFFF; 202 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000; 203 else Rd = resTemp; 204 } }}, 205 {{0}}, 206 {{overflow || underflow}}, 207 {{0}}, 208 {{0}} 209 );//SDIVcc 210 0x20: taddcc({{ 211 int64_t resTemp, val2 = Rs2_or_imm13; 212 Rd = resTemp = Rs1 + val2; 213 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 214 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 215 {{overflow}}, 216 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 217 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 218 );//TADDcc 219 0x21: tsubcc({{ 220 int64_t resTemp, val2 = Rs2_or_imm13; 221 Rd = resTemp = Rs1 + val2; 222 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 223 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 224 {{overflow}}, 225 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 226 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 227 );//TSUBcc 228 0x22: taddcctv({{ 229 int64_t resTemp, val2 = Rs2_or_imm13; 230 Rd = resTemp = Rs1 + val2; 231 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 232 if(overflow) fault = new TagOverflow;}}, 233 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 234 {{overflow}}, 235 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 236 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 237 );//TADDccTV 238 0x23: tsubcctv({{ 239 int64_t resTemp, val2 = Rs2_or_imm13; 240 Rd = resTemp = Rs1 + val2; 241 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 242 if(overflow) fault = new TagOverflow;}}, 243 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 244 {{overflow}}, 245 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 246 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 247 );//TSUBccTV 248 0x24: mulscc({{ 249 int64_t resTemp, multiplicand = Rs2_or_imm13; 250 int32_t multiplier = Rs1<31:0>; 251 int32_t savedLSB = Rs1<0:>; 252 multiplier = multiplier<31:1> | 253 ((CcrIccN 254 ^ CcrIccV) << 32); 255 if(!YValue<0:>) 256 multiplicand = 0; 257 Rd = resTemp = multiplicand + multiplier; 258 YValue = YValue<31:1> | (savedLSB << 31);}}, 259 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 260 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 261 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 262 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 263 );//MULScc 264 } 265 format IntOp 266 { 267 0x25: decode X { 268 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 269 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 270 } 271 0x26: decode X { 272 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 273 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 274 } 275 0x27: decode X { 276 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA 277 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 278 } 279 0x28: decode RS1 { 280 0x0: rdy({{Rd = YValue;}}); //RDY 281 0x2: rdccr({{Rd = Ccr;}}); //RDCCR 282 0x3: rdasi({{Rd = Asi;}}); //RDASI 283 0x4: PrivTick::rdtick({{Rd = Tick;}}); 284 0x5: rdpc({{Rd = xc->readPC();}}); //RDPC 285 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS 286 0xF: decode I { 287 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); 288 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); 289 } 290 } 291 0x2A: decode RS1 { 292 format Priv 293 { 294 0x0: rdprtpc({{ 295 Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 296 }}); 297 0x1: rdprtnpc({{ 298 Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 299 }}); 300 0x2: rdprtstate({{ 301 Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); 302 }}); 303 0x3: rdprtt({{ 304 Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); 305 }}); 306 0x4: rdprtick({{Rd = Tick;}}); 307 0x5: rdprtba({{Rd = Tba;}}); 308 0x6: rdprpstate({{Rd = Pstate;}}); 309 0x7: rdprtl({{Rd = Tl;}}); 310 0x8: rdprpil({{Rd = Pil;}}); 311 0x9: rdprcwp({{Rd = Cwp;}}); 312 0xA: rdprcansave({{Rd = Cansave;}}); 313 0xB: rdprcanrestore({{Rd = Canrestore;}}); 314 0xC: rdprcleanwin({{Rd = Cleanwin;}}); 315 0xD: rdprotherwin({{Rd = Otherwin;}}); 316 0xE: rdprwstate({{Rd = Wstate;}}); 317 } 318 //The floating point queue isn't implemented right now. 319 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); 320 0x1F: Priv::rdprver({{Rd = Ver;}}); 321 } 322 0x2B: BasicOperate::flushw({{/*window toilet*/}}); 323 0x2C: decode MOVCC3 324 { 325 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 326 0x1: decode CC 327 { 328 0x0: movcci({{ 329 if(passesCondition(CcrIcc, COND4)) 330 Rd = (I ? SIMM11 : RS2); 331 }}); 332 0x2: movccx({{ 333 if(passesCondition(CcrXcc, COND4)) 334 Rd = (I ? SIMM11 : RS2); 335 }}); 336 } 337 } 338 0x2D: sdivx({{ 339 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 340 else Rd.sdw = Rs1.sdw / Rs2_or_imm13; 341 }});//SDIVX 342 0x2E: decode RS1 { 343 0x0: IntOp::popc({{ 344 int64_t count = 0; 345 uint64_t temp = Rs2_or_imm13; 346 //Count the 1s in the front 4bits until none are left 347 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 348 while(temp) 349 { 350 count += oneBits[temp & 0xF]; 351 temp = temp >> 4; 352 } 353 }});//POPC 354 } 355 0x2F: decode RCOND3 356 { 357 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); 358 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); 359 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); 360 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); 361 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); 362 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); 363 } 364 0x30: decode RD { 365 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 366 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 367 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 368 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); 369 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); 370 } 371 0x31: decode FCN { 372 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 373 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 374 } 375 0x32: decode RD { 376 format Priv 377 { 378 0x0: wrprtpc({{ 379 xc->setMiscReg(MISCREG_TPC_BASE + Tl, 380 Rs1 ^ Rs2_or_imm13); 381 }}); 382 0x1: wrprtnpc({{ 383 xc->setMiscReg(MISCREG_TNPC_BASE + Tl, 384 Rs1 ^ Rs2_or_imm13); 385 }}); 386 0x2: wrprtstate({{ 387 xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, 388 Rs1 ^ Rs2_or_imm13); 389 }}); 390 0x3: wrprtt({{ 391 xc->setMiscReg(MISCREG_TT_BASE + Tl, 392 Rs1 ^ Rs2_or_imm13); 393 }}); 394 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 395 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 396 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 397 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); 398 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 399 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 400 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 401 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 402 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 403 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 404 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 405 } 406 } 407 408 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 409 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 410 411 0x38: Branch::jmpl({{ 412 Addr target = Rs1 + Rs2_or_imm13; 413 if(target && 0x3) 414 fault = new MemAddressNotAligned; 415 else 416 { 417 Rd = xc->readPC(); 418 NNPC = target; 419 } 420 }}); 421 0x39: Branch::return({{ 422 Addr target = Rs1 + Rs2_or_imm13; 423 if(target && 0x3) 424 fault = new MemAddressNotAligned; 425 else 426 NNPC = target; 427 //This needs to change the register window 428 //like restore does 429 }}); 430 0x3A: decode CC 431 { 432 0x0: Trap::tcci({{ 433#if FULL_SYSTEM 434 fault = new TrapInstruction; 435#else 436 if(passesCondition(CcrIcc, machInst<25:28>)) 437 // At least glibc only uses trap 0, 438 // solaris/sunos may use others 439 assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); 440 xc->syscall(); 441#endif 442 }}); 443 0x2: Trap::tccx({{ 444#if FULL_SYSTEM 445 fault = new TrapInstruction; 446#else 447 if(passesCondition(CcrXcc, machInst<25:28>)) 448 // At least glibc only uses trap 0, 449 // solaris/sunos may use others 450 assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); 451 xc->syscall(); 452#endif 453 }}); 454 } 455 0x3B: BasicOperate::flush({{/*Lala*/}}); 456 0x3C: BasicOperate::save({{/*leprechauns*/}}); 457 0x3D: BasicOperate::restore({{/*Eat my short int*/}}); 458 0x3E: decode FCN { 459 0x1: BasicOperate::done({{/*Done thing*/}}); 460 0x2: BasicOperate::retry({{/*Retry thing*/}}); 461 } 462 } 463 } 464 0x3: decode OP3 { 465 format Mem { 466 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 467 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 468 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 469 0x03: ldd({{ 470 uint64_t val = Mem.udw; 471 RdLow = val<31:0>; 472 RdHigh = val<63:32>; 473 }});//LDD 474 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 475 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 476 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 477 0x07: std({{ 478 Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; 479 }});//STD 480 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 481 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB 482 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 483 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 484 485 0x0D: ldstub({{ 486 Rd.ub = Mem.ub; 487 Mem.ub = 0xFF; 488 }}); //LDSTUB 489 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX 490 0x0F: swap({{ 491 uint32_t temp = Rd.uw; 492 Rd.uw = Mem.uw; 493 Mem.uw = temp; 494 }}); //SWAP 495 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA 496 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA 497 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 498 0x13: ldda({{ 499 uint64_t val = Mem.udw; 500 RdLow = val<31:0>; 501 RdHigh = val<63:32>; 502 }}); //LDDA 503 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 504 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 505 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 506 0x17: stda({{ 507 Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; 508 }}); //STDA 509 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 510 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 511 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 512 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA 513 514 0x1D: ldstuba({{ 515 Rd.ub = Mem.ub; 516 Mem.ub = 0xFF; 517 }}); //LDSTUBA 518 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA 519 0x1F: swapa({{ 520 uint32_t temp = Rd.uw; 521 Rd.uw = Mem.uw; 522 Mem.uw = temp; 523 }}); //SWAPA 524 0x20: Trap::ldf({{fault = new FpDisabled;}}); 525 0x21: decode X { 526 0x0: Trap::ldfsr({{fault = new FpDisabled;}}); 527 0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); 528 } 529 0x22: Trap::ldqf({{fault = new FpDisabled;}}); 530 0x23: Trap::lddf({{fault = new FpDisabled;}}); 531 0x24: Trap::stf({{fault = new FpDisabled;}}); 532 0x25: decode X { 533 0x0: Trap::stfsr({{fault = new FpDisabled;}}); 534 0x1: Trap::stxfsr({{fault = new FpDisabled;}}); 535 } 536 0x26: Trap::stqf({{fault = new FpDisabled;}}); 537 0x27: Trap::stdf({{fault = new FpDisabled;}}); 538 539 0x2D: Nop::prefetch({{ }}); //PREFETCH 540 541 0x30: Trap::ldfa({{return new FpDisabled;}}); 542 543 0x32: Trap::ldqfa({{fault = new FpDisabled;}}); 544 0x33: Trap::lddfa({{fault = new FpDisabled;}}); 545 0x34: Trap::stfa({{fault = new FpDisabled;}}); 546 0x35: Trap::stqfa({{fault = new FpDisabled;}}); 547 0x36: Trap::stdfa({{fault = new FpDisabled;}}); 548 549 0x3C: Cas::casa( 550 {{uint64_t val = Mem.uw; 551 if(Rs2.uw == val) 552 Mem.uw = Rd.uw; 553 Rd.uw = val; 554 }}); //CASA 555 0x3D: Nop::prefetcha({{ }}); //PREFETCHA 556 0x3E: Cas::casxa({{ 557 uint64_t val = Mem.udw; 558 if(Rs2 == val) 559 Mem.udw = Rd; 560 Rd = val; 561 }}); //CASXA 562 } 563 } 564} 565