decoder.isa revision 2486
1//////////////////////////////////////////////////////////////////// 2// 3// The actual decoder specification 4// 5 6decode OP default Unknown::unknown() 7{ 8 0x0: decode OP2 9 { 10 format Branch 11 { 12 //Throw an illegal instruction acception 13 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 14 0x1: decode BPCC 15 { 16 0x0: bpcci({{ 17 if(passesCondition(CcrIcc, COND2)) 18 ;//branchHere 19 }}); 20 0x2: bpccx({{ 21 if(passesCondition(CcrXcc, COND2)) 22 ;//branchHere 23 }}); 24 } 25 0x2: bicc({{ 26 if(passesCondition(CcrIcc, COND2)) 27 ;//branchHere 28 }}); 29 0x3: decode RCOND2 30 { 31 0x1: bpreq({{ 32 if(Rs1 == 0) 33 ;//branchHere 34 }}); 35 0x2: bprle({{ 36 if(Rs1 <= 0) 37 ;//branchHere 38 }}); 39 0x3: bprl({{ 40 if(Rs1 < 0) 41 ;//branchHere 42 }}); 43 0x5: bprne({{ 44 if(Rs1 != 0) 45 ;//branchHere 46 }}); 47 0x6: bprg({{ 48 if(Rs1 > 0) 49 ;//branchHere 50 }}); 51 0x7: bprge({{ 52 if(Rs1 >= 0) 53 ;//branchHere 54 }}); 55 } 56 //SETHI (or NOP if rd == 0 and imm == 0) 57 0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); 58 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 59 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 60 } 61 } 62 0x1: Branch::call({{ 63 //branch here 64 Rd = xc->readPC(); 65 }}); 66 0x2: decode OP3 { 67 format IntOp { 68 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 69 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 70 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 71 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 72 0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}}); 73 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}}); 74 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}}); 75 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}}); 76 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}}); 77 0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}}); 78 0x0A: umul({{ 79 Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>; 80 YValue = Rd<63:32>; 81 }}); 82 0x0B: smul({{ 83 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>; 84 YValue = Rd.sdw; 85 }}); 86 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}}); 87 0x0D: udivx({{ 88 if(val2 == 0) fault = new DivisionByZero; 89 else Rd.udw = Rs1.udw / Rs2_or_imm; 90 }}); 91 0x0E: udiv({{ 92 uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); 93 if(Rs2_or_imm.udw == 0) fault = new DivisionByZero; 94 else 95 { 96 Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw; 97 if(Rd.udw >> 32 != 0) 98 Rd.udw = 0xFFFFFFFF; 99 } 100 }}); 101 0x0F: sdiv({{ 102 if(val2 == 0) 103 fault = new DivisionByZero; 104 else 105 { 106 Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm; 107 if(Rd.udw<63:31> != 0) 108 Rd.udw = 0x7FFFFFFF; 109 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 110 Rd.udw = 0xFFFFFFFF80000000; 111 } 112 }});//SDIV 113 } 114 format IntOpCc { 115 0x10: addcc({{ 116 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 117 Rd = resTemp = Rs1 + val2;}}, 118 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 119 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 120 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 121 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 122 );//ADDcc 123 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 124 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 125 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 126 0x14: subcc({{ 127 int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); 128 Rd = resTemp = Rs1 - val2;}}, 129 {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, 130 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 131 {{((Rs1 >> 1) + (~val2) >> 1) + 132 ((Rs1 | ~val2) & 0x1))<63:>}}, 133 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 134 );//SUBcc 135 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 136 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 137 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 138 0x18: addccc({{ 139 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 140 int64_t carryin = CcrIccC; 141 Rd = resTemp = Rs1 + val2 + carryin;}}, 142 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 143 + carryin)}}, 144 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 145 {{((Rs1 >> 1) + (val2 >> 1) + 146 ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, 147 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 148 );//ADDCcc 149 0x1A: umulcc({{ 150 uint64_t resTemp, val2 = (I ? SIMM13 : Rs2); 151 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 152 YValue = resTemp<63:32>;}}, 153 {{0}},{{0}},{{0}},{{0}});//UMULcc 154 0x1B: smulcc({{ 155 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 156 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 157 YValue = resTemp<63:32>;}} 158 ,{{0}},{{0}},{{0}},{{0}});//SMULcc 159 0x1C: subccc({{ 160 int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); 161 int64_t carryin = CcrIccC; 162 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 163 {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, 164 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 165 {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, 166 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 167 );//SUBCcc 168 0x1D: udivxcc({{ 169 uint64_t val2 = (I ? SIMM13 : Rs2.udw); 170 if(val2 == 0) fault = new DivisionByZero; 171 else Rd.udw = Rs1.udw / val2;}} 172 ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc 173 0x1E: udivcc({{ 174 uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); 175 if(val2 == 0) fault = new DivisionByZero; 176 else 177 { 178 resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; 179 int32_t overflow = (resTemp<63:32> != 0); 180 if(overflow) rd.udw = resTemp = 0xFFFFFFFF; 181 else rd.udw = resTemp; 182 } }}, 183 {{0}}, 184 {{overflow}}, 185 {{0}}, 186 {{0}} 187 );//UDIVcc 188 0x1F: sdivcc({{ 189 int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>); 190 if(val2 == 0) fault = new DivisionByZero; 191 else 192 { 193 Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; 194 int32_t overflow = (resTemp<63:31> != 0); 195 int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 196 if(overflow) rd.udw = resTemp = 0x7FFFFFFF; 197 else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; 198 else rd.udw = resTemp; 199 } }}, 200 {{0}}, 201 {{overflow || underflow}}, 202 {{0}}, 203 {{0}} 204 );//SDIVcc 205 0x20: taddcc({{ 206 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 207 Rd = resTemp = Rs1 + val2; 208 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 209 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 210 {{overflow}}, 211 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 212 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 213 );//TADDcc 214 0x21: tsubcc({{ 215 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 216 Rd = resTemp = Rs1 + val2; 217 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 218 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 219 {{overflow}}, 220 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 222 );//TSUBcc 223 0x22: taddcctv({{ 224 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 225 Rd = resTemp = Rs1 + val2; 226 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 227 if(overflow) fault = new TagOverflow;}}, 228 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 229 {{overflow}}, 230 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 231 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 232 );//TADDccTV 233 0x23: tsubcctv({{ 234 int64_t resTemp, val2 = (I ? SIMM13 : Rs2); 235 Rd = resTemp = Rs1 + val2; 236 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 237 if(overflow) fault = new TagOverflow;}}, 238 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 239 {{overflow}}, 240 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 241 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 242 );//TSUBccTV 243 0x24: mulscc({{ 244 int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2); 245 int32_t multiplier = Rs1<31:0>; 246 int32_t savedLSB = Rs1<0:>; 247 multiplier = multipler<31:1> | 248 ((CcrIccN 249 ^ CcrIccV) << 32); 250 if(!YValue<0:>) 251 multiplicand = 0; 252 Rd = resTemp = multiplicand + multiplier; 253 YValue = YValue<31:1> | (savedLSB << 31);}}, 254 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 255 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 256 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 257 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 258 );//MULScc 259 } 260 format IntOp 261 { 262 0x25: decode X { 263 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 264 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 265 } 266 0x26: decode X { 267 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 268 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 269 } 270 0x27: decode X { 271 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA 272 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 273 } 274 0x28: decode RS1 { 275 0x0: rdy({{Rd = YValue;}}); //RDY 276 0x2: rdccr({{Rd = Ccr;}}); //RDCCR 277 0x3: rdasi({{Rd = Asi;}}); //RDASI 278 0x4: PrivTick::rdtick({{Rd = Tick;}}); 279 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC 280 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS 281 0xF: decode I { 282 0x0: Noop::membar({{//Membar isn't needed yet}}); 283 0x1: Noop::stbar({{//Stbar isn't needed yet}}); 284 } 285 } 286 0x2A: decode RS1 { 287 format Priv 288 { 289 0x0: rdprtpc({{ 290 Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 291 }}); 292 0x1: rdprtnpc({{ 293 Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 294 }}); 295 0x2: rdprtstate({{ 296 Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); 297 }}); 298 0x3: rdprtt({{ 299 Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); 300 }}); 301 0x4: rdprtick({{Rd = Tick;}}); 302 0x5: rdprtba({{Rd = Tba;}}); 303 0x6: rdprpstate({{Rd = Pstate;}}); 304 0x7: rdprtl({{Rd = Tl;}}); 305 0x8: rdprpil({{Rd = Pil;}}); 306 0x9: rdprcwp({{Rd = Cwp;}}); 307 0xA: rdprcansave({{Rd = Cansave;}}); 308 0xB: rdprcanrestore({{Rd = CanRestore;}}); 309 0xC: rdprcleanwin({{Rd = Cleanwin;}}); 310 0xD: rdprotherwin({{Rd = Otherwin;}}); 311 0xE: rdprwstate({{Rd = Wstate;}}); 312 } 313 //The floating point queue isn't implemented right now. 314 0xF: Trap::rdprfq({{fault = IllegalInstruction;}}); 315 0x1F: Priv::rdprver({{Rd = Ver;}}); 316 } 317 0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW 318 0x2C: decode MOVCC3 319 { 320 0x0: Trap::movccfcc({{fault = new FpDisabled}}); 321 0x1: decode CC 322 { 323 0x0: movcci({{ 324 if(passesCondition(CcrIcc, COND4)) 325 Rd = (I ? SIMM11 : RS2); 326 }}); 327 0x2: movccx({{ 328 if(passesCondition(CcrXcc, COND4)) 329 Rd = (I ? SIMM11 : RS2); 330 }}); 331 } 332 } 333 0x2D: sdivx({{ 334 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 335 else Rd.sdw = Rs1.sdw / Rs2_or_imm13; 336 }});//SDIVX 337 0x2E: decode RS1 { 338 0x0: IntOp::popc({{ 339 int64_t count = 0, val2 = Rs2_or_imm; 340 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 341 for(unsigned int x = 0; x < 16; x++) 342 { 343 count += oneBits[Rs2_or_imm13 & 0xF]; 344 val2 >> 4; 345 } 346 }});//POPC 347 } 348 0x2F: decode RCOND3 349 { 350 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); 351 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); 352 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); 353 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); 354 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); 355 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); 356 } 357 0x30: decode RD { 358 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 359 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 360 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 361 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); 362 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); 363 } 364 0x31: decode FCN { 365 0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED 366 0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED 367 } 368 0x32: decode RD { 369 format Priv 370 { 371 0x0: wrprtpc({{ 372 xc->setMiscReg(MISCREG_TPC_BASE + Tl, 373 Rs1 ^ Rs2_or_imm13); 374 }}); 375 0x1: wrprtnpc({{ 376 xc->setMiscReg(MISCREG_TNPC_BASE + Tl, 377 Rs1 ^ Rs2_or_imm13); 378 }}); 379 0x2: wrprtstate({{ 380 xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, 381 Rs1 ^ Rs2_or_imm13); 382 }}); 383 0x3: wrprtt({{ 384 xc->setMiscReg(MISCREG_TT_BASE + Tl, 385 Rs1 ^ Rs2_or_imm13); 386 }}); 387 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 388 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 389 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 390 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); 391 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 392 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 393 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 394 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 395 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 396 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 397 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 398 } 399 } 400 401 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 402 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 403 404 0x38: Branch::jmpl({{//Stuff}}); //JMPL 405 0x39: Branch::return({{//Other Stuff}}); //RETURN 406 0x3A: decode CC 407 { 408 0x0: Trap::tcci({{ 409#if FULL_SYSTEM 410 fault = new TrapInstruction; 411#else 412 if(passesCondition(CcrIcc, machInst<25:28>)) 413 // At least glibc only uses trap 0, 414 // solaris/sunos may use others 415 assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); 416 xc->syscall(); 417#endif 418 }}); 419 0x2: Trap::tccx({{ 420#if FULL_SYSTEM 421 fault = new TrapInstruction; 422#else 423 if(passesCondition(CcrXcc, machInst<25:28>)) 424 // At least glibc only uses trap 0, 425 // solaris/sunos may use others 426 assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); 427 xc->syscall(); 428#endif 429 }}); 430 } 431 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH 432 0x3C: BasicOperate::save({{//leprechauns); //SAVE 433 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE 434 0x3E: decode FCN { 435 0x1: BasicOperate::done({{//Done thing}}); //DONE 436 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY 437 } 438 } 439 } 440 0x3: decode OP3 { 441 format Mem { 442 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 443 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 444 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 445 0x03: ldd({{ 446 uint64_t val = Mem.udw; 447 setIntReg(RD & (~1), val<31:0>); 448 setIntReg(RD | 1, val<63:32>); 449 }});//LDD 450 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 451 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 452 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 453 0x07: std({{ 454 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 455 }});//STD 456 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 457 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB 458 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 459 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 460 461 0x0D: ldstub({{ 462 Rd.ub = Mem.ub; 463 Mem.ub = 0xFF; 464 }}); //LDSTUB 465 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX 466 0x0F: swap({{ 467 uint32_t temp = Rd.uw; 468 Rd.uw = Mem.uw; 469 Mem.uw = temp; 470 }}); //SWAP 471 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA 472 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA 473 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 474 0x13: ldda({{ 475 uint64_t val = Mem.udw; 476 setIntReg(RD & (~1), val<31:0>); 477 setIntReg(RD | 1, val<63:32>); 478 }}); //LDDA 479 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 480 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 481 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 482 0x17: stda({{ 483 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 484 }}); //STDA 485 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 486 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 487 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 488 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA 489 490 0x1D: ldstuba({{ 491 Rd.ub = Mem.ub; 492 Mem.ub = 0xFF; 493 }}); //LDSTUBA 494 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA 495 0x1F: swapa({{ 496 uint32_t temp = Rd.uw; 497 Rd.uw = Mem.uw; 498 Mem.uw = temp; 499 }}); //SWAPA 500 0x20: Trap::ldf({{fault = new FpDisabled;}}); 501 0x21: decode X { 502 0x0: Trap::ldfsr({{fault = new FpDisabled;}}); 503 0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); 504 } 505 0x22: Trap::ldqf({{fault = new FpDisabled;}}); 506 0x23: Trap::lddf({{fault = new FpDisabled;}}); 507 0x24: Trap::stf({{fault = new FpDisabled;}}); 508 0x25: decode X { 509 0x0: Trap::stfsr({{fault = new FpDisabled;}}); 510 0x1: Trap::stxfsr({{fault = new FpDisabled;}}); 511 } 512 0x26: Trap::stqf({{fault = new FpDisabled;}}); 513 0x27: Trap::stdf({{fault = new FpDisabled;}}); 514 515 0x2D: Noop::prefetch({{ }}); //PREFETCH 516 517 0x30: Trap::ldfa({{return new FpDisabled;}}); 518 519 0x32: Trap::ldqfa({{fault = new FpDisabled;}}); 520 0x33: Trap::lddfa({{fault = new FpDisabled;}}); 521 0x34: Trap::stfa({{fault = new FpDisabled;}}); 522 0x35: Trap::stqfa({{fault = new FpDisabled;}}); 523 0x36: Trap::stdfa({{fault = new FpDisabled;}}); 524 525 0x3C: Cas::casa( 526 {{uint64_t val = Mem.uw; 527 if(Rs2.uw == val) 528 Mem.uw = Rd.uw; 529 Rd.uw = val; 530 }}); //CASA 531 0x3D: Noop::prefetcha({{ }}); //PREFETCHA 532 0x3E: Cas::casxa({{ 533 uint64_t val = Mem.udw; 534 if(Rs2 == val) 535 Mem.udw = Rd; 536 Rd = val; 537 }}); //CASXA 538 } 539 } 540} 541