decoder.isa revision 2482 
1////////////////////////////////////////////////////////////////////
2//
3// The actual decoder specification
4//
5
6decode OP default Unknown::unknown()
7{
8    0x0: decode OP2
9    {
10        format Branch
11        {
12            //Throw an illegal instruction acception
13            0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
14            0x1: decode CC02
15            {
16                0x0: decode CC12
17                {
18                    0x0: bpcci({{
19                        if(passesCondition(CcrIcc, COND2))
20                            ;//branchHere
21                    }});
22                    0x1: bpccx({{
23                    if(passesCondition(CcrXcc, COND2))
24                        ;//branchHere
25                    }});
26                }
27            }
28            0x2: bicc({{
29                if(passesCondition(CcrIcc, COND2))
30                    ;//branchHere
31            }});
32            0x3: decode RCOND2
33            {
34                0x1: bpreq({{
35                    if(Rs1 == 0)
36                        ;//branchHere
37                }});
38                0x2: bprle({{
39                    if(Rs1 <= 0)
40                        ;//branchHere
41                }});
42                0x3: bprl({{
43                    if(Rs1 < 0)
44                        ;//branchHere
45                }});
46                0x5: bprne({{
47                    if(Rs1 != 0)
48                        ;//branchHere
49                }});
50                0x6: bprg({{
51                    if(Rs1 > 0)
52                        ;//branchHere
53                }});
54                0x7: bprge({{
55                    if(Rs1 >= 0)
56                        ;//branchHere
57                }});
58            }
59            //SETHI (or NOP if rd == 0 and imm == 0)
60            0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
61            0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
62            0x6: Trap::fbfcc({{fault = new FpDisabled;}});
63        }
64    }
65    0x1: Branch::call({{
66            //branch here
67            Rd = xc->readPC();
68    }});
69    0x2: decode OP3 {
70        format IntOp {
71            0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
72            0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
73            0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
74            0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
75            0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}});
76            0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}});
77            0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}});
78            0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}});
79            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}});
80            0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}});
81            0x0A: umul({{
82                Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>;
83                YValue = Rd<63:32>;
84            }});
85            0x0B: smul({{
86                Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>;
87                YValue = Rd.sdw;
88            }});
89            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}});
90            0x0D: udivx({{
91                if(val2 == 0) fault = new DivisionByZero;
92                else Rd.udw = Rs1.udw / Rs2_or_imm;
93            }});
94            0x0E: udiv({{
95                uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
96                if(Rs2_or_imm.udw == 0) fault = new DivisionByZero;
97                else
98                {
99                    Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw;
100                    if(Rd.udw >> 32 != 0)
101                        Rd.udw = 0xFFFFFFFF;
102                }
103            }});
104            0x0F: sdiv({{
105                if(val2 == 0)
106                    fault = new DivisionByZero;
107                else
108                {
109                    Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm;
110                    if(Rd.udw<63:31> != 0)
111                        Rd.udw = 0x7FFFFFFF;
112                    else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
113                        Rd.udw = 0xFFFFFFFF80000000;
114                }
115            }});//SDIV
116        }
117        format IntOpCc {
118            0x10: addcc({{
119                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
120                Rd = resTemp = Rs1 + val2;}},
121                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
122                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
123                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
124                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
125                );//ADDcc
126            0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
127            0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
128            0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
129            0x14: subcc({{
130                int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
131                Rd = resTemp = Rs1 - val2;}},
132                {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
133                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
134                {{((Rs1 >> 1) + (~val2) >> 1) +
135                    ((Rs1 | ~val2) & 0x1))<63:>}},
136                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
137            );//SUBcc
138            0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
139            0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
140            0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
141            0x18: addccc({{
142                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
143                int64_t carryin = CcrIccC;
144                Rd = resTemp = Rs1 + val2 + carryin;}},
145                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
146                    + carryin)}},
147                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
148                {{((Rs1 >> 1) + (val2 >> 1) +
149                    ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
150                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
151            );//ADDCcc
152            0x1A: umulcc({{
153                uint64_t resTemp, val2 = (I ? SIMM13 : Rs2);
154                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
155                YValue = resTemp<63:32>;}},
156                {{0}},{{0}},{{0}},{{0}});//UMULcc
157            0x1B: smulcc({{
158                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
159                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
160                YValue = resTemp<63:32>;}}
161                ,{{0}},{{0}},{{0}},{{0}});//SMULcc
162            0x1C: subccc({{
163                int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
164                int64_t carryin = CcrIccC;
165                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
166                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
167                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
168                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
169                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
170            );//SUBCcc
171            0x1D: udivxcc({{
172                uint64_t val2 = (I ? SIMM13 : Rs2.udw);
173                if(val2 == 0) fault = new DivisionByZero;
174                else Rd.udw = Rs1.udw / val2;}}
175                ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
176            0x1E: udivcc({{
177                uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
178                if(val2 == 0) fault = new DivisionByZero;
179                else
180                {
181                    resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
182                    int32_t overflow = (resTemp<63:32> != 0);
183                    if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
184                    else rd.udw = resTemp;
185                } }},
186                {{0}},
187                {{overflow}},
188                {{0}},
189                {{0}}
190            );//UDIVcc
191            0x1F: sdivcc({{
192                int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>);
193                if(val2 == 0) fault = new DivisionByZero;
194                else
195                {
196                    Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
197                    int32_t overflow = (resTemp<63:31> != 0);
198                    int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
199                    if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
200                    else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
201                    else rd.udw = resTemp;
202                } }},
203                {{0}},
204                {{overflow || underflow}},
205                {{0}},
206                {{0}}
207            );//SDIVcc
208            0x20: taddcc({{
209                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
210                Rd = resTemp = Rs1 + val2;
211                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
212                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
213                {{overflow}},
214                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
215                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
216            );//TADDcc
217            0x21: tsubcc({{
218                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
219                Rd = resTemp = Rs1 + val2;
220                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
221                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
222                {{overflow}},
223                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
224                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
225            );//TSUBcc
226            0x22: taddcctv({{
227                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
228                Rd = resTemp = Rs1 + val2;
229                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
230                if(overflow) fault = new TagOverflow;}},
231                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
232                {{overflow}},
233                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
234                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
235            );//TADDccTV
236            0x23: tsubcctv({{
237                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
238                Rd = resTemp = Rs1 + val2;
239                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
240                if(overflow) fault = new TagOverflow;}},
241                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
242                {{overflow}},
243                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
244                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
245            );//TSUBccTV
246            0x24: mulscc({{
247                int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2);
248                int32_t multiplier = Rs1<31:0>;
249                int32_t savedLSB = Rs1<0:>;
250                multiplier = multipler<31:1> |
251                    ((CcrIccN
252                    ^ CcrIccV) << 32);
253                if(!YValue<0:>)
254                    multiplicand = 0;
255                Rd = resTemp = multiplicand + multiplier;
256                YValue = YValue<31:1> | (savedLSB << 31);}},
257                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
258                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
259                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
260                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
261            );//MULScc
262            }
263            format IntOp
264            {
265                0x25: decode X {
266                    0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
267                    0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
268                }
269                0x26: decode X {
270                    0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
271                    0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
272                }
273                0x27: decode X {
274                    0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
275                    0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
276                }
277                0x28: decode RS1 {
278                    0x0: rdy({{Rd = YValue;}}); //RDY
279                    0x2: rdccr({{Rd = Ccr;}}); //RDCCR
280                    0x3: rdasi({{Rd = Asi;}}); //RDASI
281                    0x4: PrivTick::rdtick({{Rd = Tick;}});
282                    0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
283                    0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
284                    0xF: decode I {
285                        0x0: Noop::membar({{//Membar isn't needed yet}});
286                        0x1: Noop::stbar({{//Stbar isn't needed yet}});
287                    }
288                }
289                0x2A: decode RS1 {
290                    format Priv
291                    {
292                        0x0: rdprtpc({{
293                            Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
294                            }});
295                        0x1: rdprtnpc({{
296                            Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
297                            }});
298                        0x2: rdprtstate({{
299                            Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
300                            }});
301                        0x3: rdprtt({{
302                            Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
303                            }});
304                        0x4: rdprtick({{Rd = Tick;}});
305                        0x5: rdprtba({{Rd = Tba;}});
306                        0x6: rdprpstate({{Rd = Pstate;}});
307                        0x7: rdprtl({{Rd = Tl;}});
308                        0x8: rdprpil({{Rd = Pil;}});
309                        0x9: rdprcwp({{Rd = Cwp;}});
310                        0xA: rdprcansave({{Rd = Cansave;}});
311                        0xB: rdprcanrestore({{Rd = CanRestore;}});
312                        0xC: rdprcleanwin({{Rd = Cleanwin;}});
313                        0xD: rdprotherwin({{Rd = Otherwin;}});
314                        0xE: rdprwstate({{Rd = Wstate;}});
315                    }
316                    //The floating point queue isn't implemented right now.
317                    0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
318                    0x1F: Priv::rdprver({{Rd = Ver;}});
319                }
320                0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
321                0x2C: decode CC2
322                {
323                    0x0: Trap::movccfcc({{fault = new FpDisabled}});
324                    0x1: decode CC04
325                    {
326                        0x0: decode CC14
327                        {
328                            0x0: movcci({{
329                                if(passesCondition(CcrIcc, COND4))
330                                    Rd = (I ? SIMM11 : RS2);
331                            }});
332                            0x1: movccx({{
333                                if(passesCondition(CcrXcc, COND4))
334                                    Rd = (I ? SIMM11 : RS2);
335                            }});
336                        }
337                    }
338                }
339                0x2D: sdivx({{
340                        if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
341                        else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
342                }});//SDIVX
343                0x2E: decode RS1 {
344                        0x0: IntOp::popc({{
345                        int64_t count = 0, val2 = Rs2_or_imm;
346                        uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
347                        for(unsigned int x = 0; x < 16; x++)
348                        {
349                                count += oneBits[Rs2_or_imm13 & 0xF];
350                                val2 >> 4;
351                        }
352                        }});//POPC
353                }
354                0x2F: decode RCOND3
355                {
356                    0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
357                    0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
358                    0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
359                    0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
360                    0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
361                    0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
362                }
363                0x30: decode RD {
364                        0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
365                        0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
366                        0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
367                        0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
368                        0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
369                }
370                0x31: decode FCN {
371                        0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
372                        0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
373                }
374                0x32: decode RD {
375                    format Priv
376                    {
377                        0x0: wrprtpc({{
378                            xc->setMiscReg(MISCREG_TPC_BASE + Tl,
379                                Rs1 ^ Rs2_or_imm13);
380                        }});
381                        0x1: wrprtnpc({{
382                            xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
383                                Rs1 ^ Rs2_or_imm13);
384                        }});
385                        0x2: wrprtstate({{
386                            xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
387                                Rs1 ^ Rs2_or_imm13);
388                        }});
389                        0x3: wrprtt({{
390                            xc->setMiscReg(MISCREG_TT_BASE + Tl,
391                                Rs1 ^ Rs2_or_imm13);
392                        }});
393                        0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
394                        0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
395                        0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
396                        0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
397                        0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
398                        0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
399                        0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
400                        0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
401                        0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
402                        0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
403                        0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
404                    }
405                }
406
407                0x34: Trap::fpop1({{fault = new FpDisabled;}});
408                0x35: Trap::fpop2({{fault = new FpDisabled;}});
409
410                0x38: Branch::jmpl({{//Stuff}}); //JMPL
411                0x39: Branch::return({{//Other Stuff}}); //RETURN
412                0x3A: decode CC04
413                {
414                    // If CC04 == 1, it's an illegal instruction
415                    0x0: decode CC14
416                    {
417                        0x0: Trap::tcci({{
418                            if(passesCondition(CcrIcc, machInst<25:28>))
419                                fault = new TrapInstruction;
420                        }});
421                        0x1: Trap::tccx({{
422                            if(passesCondition(CcrXcc, machInst<25:28>))
423                                fault = new TrapInstruction;
424                        }});
425                    }
426                }
427                0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
428                0x3C: BasicOperate::save({{//leprechauns); //SAVE
429                0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
430                0x3E: decode FCN {
431                    0x1: BasicOperate::done({{//Done thing}}); //DONE
432                    0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
433                }
434            }
435    }
436    0x3: decode OP3 {
437            format Mem {
438                    0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
439                    0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
440                    0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
441                    0x03: ldd({{
442                        uint64_t val = Mem.udw;
443                        setIntReg(RD & (~1), val<31:0>);
444                        setIntReg(RD | 1, val<63:32>);
445                    }});//LDD
446                    0x04: stw({{Mem.sw = Rd.sw;}}); //STW
447                    0x05: stb({{Mem.sb = Rd.sb;}}); //STB
448                    0x06: sth({{Mem.shw = Rd.shw;}}); //STH
449                    0x07: std({{
450                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
451                    }});//STD
452                    0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
453                    0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
454                    0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
455                    0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
456
457                    0x0D: ldstub({{
458                            Rd.ub = Mem.ub;
459                            Mem.ub = 0xFF;
460                    }}); //LDSTUB
461                    0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
462                    0x0F: swap({{
463                            uint32_t temp = Rd.uw;
464                            Rd.uw = Mem.uw;
465                            Mem.uw = temp;
466                    }}); //SWAP
467                    0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
468                    0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
469                    0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
470                    0x13: ldda({{
471                            uint64_t val = Mem.udw;
472                            setIntReg(RD & (~1), val<31:0>);
473                            setIntReg(RD | 1, val<63:32>);
474                    }}); //LDDA
475                    0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
476                    0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
477                    0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
478                    0x17: stda({{
479                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
480                    }}); //STDA
481                    0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
482                    0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
483                    0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
484                    0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
485
486                    0x1D: ldstuba({{
487                            Rd.ub = Mem.ub;
488                            Mem.ub = 0xFF;
489                    }}); //LDSTUBA
490                    0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
491                    0x1F: swapa({{
492                            uint32_t temp = Rd.uw;
493                            Rd.uw = Mem.uw;
494                            Mem.uw = temp;
495                    }}); //SWAPA
496                    0x20: Trap::ldf({{fault = new FpDisabled;}});
497                    0x21: decode X {
498                        0x0: Trap::ldfsr({{fault = new FpDisabled;}});
499                        0x1: Trap::ldxfsr({{fault = new FpDisabled;}});
500                    }
501                    0x22: Trap::ldqf({{fault = new FpDisabled;}});
502                    0x23: Trap::lddf({{fault = new FpDisabled;}});
503                    0x24: Trap::stf({{fault = new FpDisabled;}});
504                    0x25: decode X {
505                        0x0: Trap::stfsr({{fault = new FpDisabled;}});
506                        0x1: Trap::stxfsr({{fault = new FpDisabled;}});
507                    }
508                    0x26: Trap::stqf({{fault = new FpDisabled;}});
509                    0x27: Trap::stdf({{fault = new FpDisabled;}});
510
511                    0x2D: Noop::prefetch({{ }}); //PREFETCH
512
513                    0x30: Trap::ldfa({{return new FpDisabled;}});
514
515                    0x32: Trap::ldqfa({{fault = new FpDisabled;}});
516                    0x33: Trap::lddfa({{fault = new FpDisabled;}});
517                    0x34: Trap::stfa({{fault = new FpDisabled;}});
518                    0x35: Trap::stqfa({{fault = new FpDisabled;}});
519                    0x36: Trap::stdfa({{fault = new FpDisabled;}});
520
521                    0x3C: Cas::casa(
522                            {{uint64_t val = Mem.uw;
523                            if(Rs2.uw == val)
524                                    Mem.uw = Rd.uw;
525                            Rd.uw = val;
526                    }}); //CASA
527                    0x3D: Noop::prefetcha({{ }}); //PREFETCHA
528                    0x3E: Cas::casxa({{
529                            uint64_t val = Mem.udw;
530                            if(Rs2 == val)
531                                    Mem.udw = Rd;
532                            Rd = val;
533                    }}); //CASXA
534            }
535    }
536}
537