decoder.isa revision 2469
15081Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 25081Sgblack@eecs.umich.edu// 35081Sgblack@eecs.umich.edu// The actual decoder specification 47087Snate@binkert.org// 57087Snate@binkert.org 67087Snate@binkert.orgdecode OP default Unknown::unknown() 77087Snate@binkert.org{ 87087Snate@binkert.org 0x0: decode OP2 97087Snate@binkert.org { 107087Snate@binkert.org //Throw an illegal instruction acception 117087Snate@binkert.org 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 125081Sgblack@eecs.umich.edu 0x1: Branch::bpcc({{ 137087Snate@binkert.org switch((CC12 << 1) | CC02) 147087Snate@binkert.org { 157087Snate@binkert.org case 1: 167087Snate@binkert.org case 3: 177087Snate@binkert.org fault = new IllegalInstruction; 187087Snate@binkert.org case 0: 197087Snate@binkert.org if(passesCondition(CcrIcc, COND2)) 207087Snate@binkert.org ;//branchHere 215081Sgblack@eecs.umich.edu break; 227087Snate@binkert.org case 2: 235081Sgblack@eecs.umich.edu if(passesCondition(CcrXcc, COND2)) 245081Sgblack@eecs.umich.edu ;//branchHere 255081Sgblack@eecs.umich.edu break; 265081Sgblack@eecs.umich.edu } 275081Sgblack@eecs.umich.edu }});//BPcc 285081Sgblack@eecs.umich.edu 0x2: Branch::bicc({{ 295081Sgblack@eecs.umich.edu if(passesCondition(CcrIcc, COND2)) 305081Sgblack@eecs.umich.edu ;//branchHere 315081Sgblack@eecs.umich.edu }});//Bicc 325081Sgblack@eecs.umich.edu 0x3: Branch::bpr({{ 335081Sgblack@eecs.umich.edu switch(RCOND2) 345081Sgblack@eecs.umich.edu { 355081Sgblack@eecs.umich.edu case 0: 365081Sgblack@eecs.umich.edu case 4: 375081Sgblack@eecs.umich.edu fault = new IllegalInstruction; 385081Sgblack@eecs.umich.edu case 1: 395081Sgblack@eecs.umich.edu if(Rs1 == 0) 405081Sgblack@eecs.umich.edu ;//branchHere 419372Snilay@cs.wisc.edu break; 429372Snilay@cs.wisc.edu case 2: 439372Snilay@cs.wisc.edu if(Rs1 <= 0) 449372Snilay@cs.wisc.edu ;//branchHere 459372Snilay@cs.wisc.edu break; 469372Snilay@cs.wisc.edu case 3: 479372Snilay@cs.wisc.edu if(Rs1 < 0) 489372Snilay@cs.wisc.edu ;//branchHere 499372Snilay@cs.wisc.edu break; 509372Snilay@cs.wisc.edu case 5: 519372Snilay@cs.wisc.edu if(Rs1 != 0) 525081Sgblack@eecs.umich.edu ;//branchHere 53 break; 54 case 6: 55 if(Rs1 > 0) 56 ;//branchHere 57 break; 58 case 7: 59 if(Rs1 >= 0) 60 ;//branchHere 61 break; 62 } 63 }}); //BPr 64 //SETHI (or NOP if rd == 0 and imm == 0) 65 0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); 66 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 67 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 68 } 69 0x1: Branch::call({{ 70 //branch here 71 Rd = xc->pc; 72 }}); 73 0x2: decode OP3 { 74 format IntegerOp { 75 0x00: add({{ 76 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 77 Rd = Rs1.sdw + val2; 78 }});//ADD 79 0x01: and({{ 80 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 81 Rd = Rs1.udw & val2; 82 }});//AND 83 0x02: or({{ 84 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 85 Rd = Rs1.udw | val2; 86 }});//OR 87 0x03: xor({{ 88 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 89 Rd = Rs1.udw ^ val2; 90 }});//XOR 91 0x04: sub({{ 92 int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1; 93 Rd = Rs1.sdw + val2; 94 }});//SUB 95 0x05: andn({{ 96 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 97 Rd = Rs1.udw & ~val2; 98 }});//ANDN 99 0x06: orn({{ 100 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 101 Rd = Rs1.udw | ~val2; 102 }});//ORN 103 0x07: xnor({{ 104 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 105 Rd = ~(Rs1.udw ^ val2); 106 }});//XNOR 107 0x08: addc({{ 108 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 109 int64_t carryin = CcrIccC; 110 Rd = Rs1.sdw + val2 + carryin; 111 }});//ADDC 112 0x09: mulx({{ 113 int64_t val2 = (I ? SIMM13.sdw : Rs2); 114 Rd = Rs1 * val2; 115 }});//MULX 116 0x0A: umul({{ 117 uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw); 118 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 119 YValue = resTemp<63:32>; 120 }});//UMUL 121 0x0B: smul({{ 122 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw); 123 rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>; 124 YValue = resTemp<63:32>; 125 }});//SMUL 126 0x0C: subc({{ 127 int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1; 128 int64_t carryin = CcrIccC; 129 Rd.sdw = Rs1.sdw + val2 + carryin; 130 }});//SUBC 131 0x0D: udivx({{ 132 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 133 if(val2 == 0) fault = new DivisionByZero; 134 else Rd.udw = Rs1.udw / val2; 135 }});//UDIVX 136 0x0E: udiv({{ 137 uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 138 if(val2 == 0) 139 fault = new DivisionByZero; 140 resTemp = (uint64_t)((YValue << 32) 141 | Rs1.udw<31:0>) / val2; 142 int32_t overflow = (resTemp<63:32> != 0); 143 if(overflow) 144 rd.udw = resTemp = 0xFFFFFFFF; 145 else 146 rd.udw = resTemp; 147 }}); //UDIV 148 0x0F: sdiv({{ 149 int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 150 if(val2 == 0) 151 fault = new DivisionByZero; 152 153 Rd.sdw = (int64_t)((YValue << 32) | 154 Rs1.sdw<31:0>) / val2; 155 resTemp = Rd.sdw; 156 int32_t overflow = (resTemp<63:31> != 0); 157 int32_t underflow = 158 (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 159 if(overflow) 160 rd.udw = resTemp = 0x7FFFFFFF; 161 else if(underflow) 162 rd.udw = resTemp = 0xFFFFFFFF80000000; 163 else 164 rd.udw = resTemp; 165 }});//SDIV 166 } 167 format IntegerOpCc { 168 0x10: addcc({{ 169 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 170 Rd = resTemp = Rs1 + val2;}}, 171 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 172 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 173 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 174 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 175 );//ADDcc 176 0x11: andcc({{ 177 int64_t val2 = (I ? SIMM13.sdw : Rs2); 178 Rd = Rs1 & val2;}}, 179 {{0}},{{0}},{{0}},{{0}});//ANDcc 180 0x12: orcc({{ 181 int64_t val2 = (I ? SIMM13.sdw : Rs2); 182 Rd = Rs1 | val2;}}, 183 {{0}},{{0}},{{0}},{{0}});//ORcc 184 0x13: xorcc({{ 185 int64_t val2 = (I ? SIMM13.sdw : Rs2); 186 Rd = Rs1 ^ val2;}}, 187 {{0}},{{0}},{{0}},{{0}});//XORcc 188 0x14: subcc({{ 189 int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2); 190 Rd = resTemp = Rs1 - val2;}}, 191 {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, 192 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 193 {{((Rs1 >> 1) + (~val2) >> 1) + 194 ((Rs1 | ~val2) & 0x1))<63:>}}, 195 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 196 );//SUBcc 197 0x15: andncc({{ 198 int64_t val2 = (I ? SIMM13.sdw : Rs2); 199 Rd = Rs1 & ~val2;}}, 200 {{0}},{{0}},{{0}},{{0}});//ANDNcc 201 0x16: orncc({{ 202 int64_t val2 = (I ? SIMM13.sdw : Rs2); 203 Rd = Rs1 | ~val2;}}, 204 {{0}},{{0}},{{0}},{{0}});//ORNcc 205 0x17: xnorcc({{ 206 int64_t val2 = (I ? SIMM13.sdw : Rs2); 207 Rd = ~(Rs1 ^ val2);}}, 208 {{0}},{{0}},{{0}},{{0}});//XNORcc 209 0x18: addccc({{ 210 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 211 int64_t carryin = CcrIccC; 212 Rd = resTemp = Rs1 + val2 + carryin;}}, 213 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 214 + carryin)}}, 215 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 216 {{((Rs1 >> 1) + (val2 >> 1) + 217 ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, 218 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 219 );//ADDCcc 220 0x1A: umulcc({{ 221 uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 222 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 223 YValue = resTemp<63:32>;}}, 224 {{0}},{{0}},{{0}},{{0}});//UMULcc 225 0x1B: smulcc({{ 226 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 227 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 228 YValue = resTemp<63:32>;}} 229 ,{{0}},{{0}},{{0}},{{0}});//SMULcc 230 0x1C: subccc({{ 231 int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2); 232 int64_t carryin = CcrIccC; 233 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 234 {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, 235 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 236 {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, 237 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 238 );//SUBCcc 239 0x1D: udivxcc({{ 240 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 241 if(val2 == 0) fault = new DivisionByZero; 242 else Rd.udw = Rs1.udw / val2;}} 243 ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc 244 0x1E: udivcc({{ 245 uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 246 if(val2 == 0) fault = new DivisionByZero; 247 else 248 { 249 resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; 250 int32_t overflow = (resTemp<63:32> != 0); 251 if(overflow) rd.udw = resTemp = 0xFFFFFFFF; 252 else rd.udw = resTemp; 253 } }}, 254 {{0}}, 255 {{overflow}}, 256 {{0}}, 257 {{0}} 258 );//UDIVcc 259 0x1F: sdivcc({{ 260 int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 261 if(val2 == 0) fault = new DivisionByZero; 262 else 263 { 264 Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; 265 int32_t overflow = (resTemp<63:31> != 0); 266 int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 267 if(overflow) rd.udw = resTemp = 0x7FFFFFFF; 268 else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; 269 else rd.udw = resTemp; 270 } }}, 271 {{0}}, 272 {{overflow || underflow}}, 273 {{0}}, 274 {{0}} 275 );//SDIVcc 276 0x20: taddcc({{ 277 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 278 Rd = resTemp = Rs1 + val2; 279 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 280 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 281 {{overflow}}, 282 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 283 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 284 );//TADDcc 285 0x21: tsubcc({{ 286 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 287 Rd = resTemp = Rs1 + val2; 288 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 289 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 290 {{overflow}}, 291 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 292 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 293 );//TSUBcc 294 0x22: taddcctv({{ 295 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 296 Rd = resTemp = Rs1 + val2; 297 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 298 if(overflow) fault = new TagOverflow;}}, 299 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 300 {{overflow}}, 301 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 302 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 303 );//TADDccTV 304 0x23: tsubcctv({{ 305 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 306 Rd = resTemp = Rs1 + val2; 307 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 308 if(overflow) fault = new TagOverflow;}}, 309 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 310 {{overflow}}, 311 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 312 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 313 );//TSUBccTV 314 0x24: mulscc({{ 315 int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2); 316 int32_t multiplier = Rs1<31:0>; 317 int32_t savedLSB = Rs1<0:>; 318 multiplier = multipler<31:1> | 319 ((CcrIccN 320 ^ CcrIccV) << 32); 321 if(!YValue<0:>) 322 multiplicand = 0; 323 Rd = resTemp = multiplicand + multiplier; 324 YValue = YValue<31:1> | (savedLSB << 31);}}, 325 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 326 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 327 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 328 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 329 );//MULScc 330 } 331 format IntegerOp 332 { 333 0x25: decode X { 334 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL 335 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX 336 } 337 0x26: decode X { 338 0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL 339 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX 340 } 341 0x27: decode X { 342 0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA 343 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 344 } 345 0x28: decode RS1 { 346 0x0: rdy({{Rd = YValue;}}); //RDY 347 0x2: rdccr({{Rd = Ccr;}}); //RDCCR 348 0x3: rdasi({{Rd = Asi;}}); //RDASI 349 0x4: PrivTick::rdtick({{Rd = Tick;}}); 350 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC 351 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS 352 0xF: decode I { 353 0x0: Noop::membar({{//Membar isn't needed yet}}); 354 0x1: Noop::stbar({{//Stbar isn't needed yet}}); 355 } 356 } 357 0x2A: decode RS1 { 358 format Priv 359 { 360 0x0: rdprtpc({{ 361 Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl); 362 }}); 363 0x1: rdprtnpc({{ 364 Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl); 365 }}); 366 0x2: rdprtstate({{ 367 Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl); 368 }}); 369 0x3: rdprtt({{ 370 Rd = xc->readMiscReg(MISCREG_TT_BASE + tl); 371 }}); 372 0x4: rdprtick({{Rd = Tick;}}); 373 0x5: rdprtba({{Rd = Tba;}}); 374 0x6: rdprpstate({{Rd = Pstate;}}); 375 0x7: rdprtl({{Rd = Tl;}}); 376 0x8: rdprpil({{Rd = Pil;}}); 377 0x9: rdprcwp({{Rd = Cwp;}}); 378 0xA: rdprcansave({{Rd = Cansave;}}); 379 0xB: rdprcanrestore({{Rd = CanRestore;}}); 380 0xC: rdprcleanwin({{Rd = Cleanwin;}}); 381 0xD: rdprotherwin({{Rd = Otherwin;}}); 382 0xE: rdprwstate({{Rd = Wstate;}}); 383 } 384 //The floating point queue isn't implemented right now. 385 0xF: Trap::rdprfq({{fault = IllegalInstruction;}}); 386 0x1F: Priv::rdprver({{Rd = Ver;}}); 387 } 388 0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW 389 0x2C: movcc({{ 390 ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0); 391 switch(ccBank) 392 { 393 case 0: case 1: case 2: case 3: 394 fault = new FpDisabled; 395 break; 396 case 5: case 7: 397 fault = new IllegalInstruction; 398 break; 399 case 4: 400 if(passesCondition(CcrIcc, COND4)) 401 Rd = (I ? SIMM11.sdw : RS2); 402 break; 403 case 6: 404 if(passesCondition(CcrXcc, COND4)) 405 Rd = (I ? SIMM11.sdw : RS2); 406 break; 407 } 408 }});//MOVcc 409 0x2D: sdivx({{ 410 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 411 if(val2 == 0) fault = new DivisionByZero; 412 else Rd.sdw = Rs1.sdw / val2; 413 }});//SDIVX 414 0x2E: decode RS1 { 415 0x0: IntegerOp::popc({{ 416 int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw); 417 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4} 418 for(unsigned int x = 0; x < 16; x++) 419 { 420 count += oneBits[val2 & 0xF]; 421 val2 >> 4; 422 } 423 }});//POPC 424 } 425 0x2F: movr({{ 426 uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw); 427 switch(RCOND3) 428 { 429 case 0: case 4: 430 fault = IllegalInstruction; 431 break; 432 case 1: 433 if(Rs1 == 0) Rd = val2; 434 break; 435 case 2: 436 if(Rs1 <= 0) Rd = val2; 437 break; 438 case 3: 439 if(Rs1 = 0) Rd = val2; 440 break; 441 case 5: 442 if(Rs1 != 0) Rd = val2; 443 break; 444 case 6: 445 if(Rs1 > 0) Rd = val2; 446 break; 447 case 7: 448 if(Rs1 >= 0) Rd = val2; 449 break; 450 } 451 }});//MOVR 452 0x30: decode RD { 453 0x0: wry({{ 454 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 455 Y = Rs1 ^ val2; 456 }});//WRY 457 0x2: wrccr({{ 458 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 459 Ccr = Rs1 ^ val2; 460 }});//WRCCR 461 0x3: wrasi({{ 462 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 463 Asi = Rs1 ^ val2; 464 }});//WRASI 465 0x6: wrfprs({{ 466 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 467 Asi = Rs1 ^ val2; 468 }});//WRFPRS 469 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); 470 } 471 0x31: decode FCN { 472 0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED 473 0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED 474 } 475 0x32: decode RD { 476 format Priv 477 { 478 0x0: wrprtpc({{ 479 xc->setMiscReg(MISCREG_TPC_BASE + tl, 480 Rs1 ^ Rs2_or_imm13); 481 }}); 482 0x1: wrprtnpc({{ 483 xc->setMiscReg(MISCREG_TNPC_BASE + tl, 484 Rs1 ^ Rs2_or_imm13); 485 }}); 486 0x2: wrprtstate({{ 487 xc->setMiscReg(MISCREG_TSTATE_BASE + tl, 488 Rs1 ^ Rs2_or_imm13); 489 }}); 490 0x3: wrprtt({{ 491 xc->setMiscReg(MISCREG_TT_BASE + tl, 492 Rs1 ^ Rs2_or_imm13); 493 }}); 494 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 495 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 496 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 497 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); 498 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 499 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 500 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 501 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 502 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 503 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 504 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 505 } 506 } 507 508 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 509 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 510 511 512 0x38: Branch::jmpl({{//Stuff}}); //JMPL 513 0x39: Branch::return({{//Other Stuff}}); //RETURN 514 0x3A: decode CC04 515 { 516 // If CC04 == 1, it's an illegal instruction 517 0x0: decode CC14 518 { 519 0x0: Trap::tcci({{ 520 if(passesCondition(ccr_icc, machInst<25:28>)) 521 fault = new TrapInstruction; 522 }}); 523 0x1: Trap::tccx({{ 524 if(passesCondition(ccr_xcc, machInst<25:28>)) 525 fault = new TrapInstruction; 526 }}); 527 } 528 } 529 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH 530 0x3C: BasicOperate::save({{//leprechauns); //SAVE 531 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE 532 0x3E: decode FCN { 533 0x1: BasicOperate::done({{//Done thing}}); //DONE 534 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY 535 } 536 } 537 } 538 0x3: decode OP3 { 539 format Mem { 540 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 541 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 542 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 543 0x03: ldd({{ 544 uint64_t val = Mem.udw; 545 setIntReg(RD & (~1), val<31:0>); 546 setIntReg(RD | 1, val<63:32>); 547 }});//LDD 548 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 549 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 550 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 551 0x07: std({{ 552 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 553 }});//STD 554 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 555 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB 556 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 557 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 558 559 0x0D: ldstub({{ 560 Rd.ub = Mem.ub; 561 Mem.ub = 0xFF; 562 }}); //LDSTUB 563 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX 564 0x0F: swap({{ 565 uint32_t temp = Rd.uw; 566 Rd.uw = Mem.uw; 567 Mem.uw = temp; 568 }}); //SWAP 569 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA 570 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA 571 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 572 0x13: ldda({{ 573 uint64_t val = Mem.udw; 574 setIntReg(RD & (~1), val<31:0>); 575 setIntReg(RD | 1, val<63:32>); 576 }}); //LDDA 577 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 578 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 579 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 580 0x17: stda({{ 581 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 582 }}); //STDA 583 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 584 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 585 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 586 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA 587 588 0x1D: ldstuba({{ 589 Rd.ub = Mem.ub; 590 Mem.ub = 0xFF; 591 }}); //LDSTUBA 592 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA 593 0x1F: swapa({{ 594 uint32_t temp = Rd.uw; 595 Rd.uw = Mem.uw; 596 Mem.uw = temp; 597 }}); //SWAPA 598 0x20: Trap::ldf({{fault = new FpDisabled;}}); 599 0x21: decode X { 600 0x0: Trap::ldfsr({{fault = new FpDisabled;}}); 601 0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); 602 } 603 0x22: Trap::ldqf({{fault = new FpDisabled;}}); 604 0x23: Trap::lddf({{fault = new FpDisabled;}}); 605 0x24: Trap::stf({{fault = new FpDisabled;}}); 606 0x25: decode X { 607 0x0: Trap::stfsr({{fault = new FpDisabled;}}); 608 0x1: Trap::stxfsr({{fault = new FpDisabled;}}); 609 } 610 0x26: Trap::stqf({{fault = new FpDisabled;}}); 611 0x27: Trap::stdf({{fault = new FpDisabled;}}); 612 613 0x2D: Noop::prefetch({{ }}); //PREFETCH 614 615 0x30: Trap::ldfa({{return new FpDisabled;}}); 616 617 0x32: Trap::ldqfa({{fault = new FpDisabled;}}); 618 0x33: Trap::lddfa({{fault = new FpDisabled;}}); 619 0x34: Trap::stfa({{fault = new FpDisabled;}}); 620 0x35: Trap::stqfa({{fault = new FpDisabled;}}); 621 0x36: Trap::stdfa({{fault = new FpDisabled;}}); 622 623 0x3C: Cas::casa( 624 {{uint64_t val = Mem.uw; 625 if(Rs2.uw == val) 626 Mem.uw = Rd.uw; 627 Rd.uw = val; 628 }}); //CASA 629 0x3D: Noop::prefetcha({{ }}); //PREFETCHA 630 0x3E: Cas::casxa( 631 {{uint64_t val = Mem.udw; 632 if(Rs2 == val) 633 Mem.udw = Rd; 634 Rd = val; 635 }}); //CASXA 636 } 637 } 638} 639