decoder.isa revision 2224
1//////////////////////////////////////////////////////////////////// 2// 3// The actual decoder specification 4// 5 6decode OP default Trap::unknown({{IllegalInstruction}}) { 7 8 0x0: decode OP2 { 9 0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP 10 0x1: Branch::bpcc({{ 11 switch((CC12 << 1) | CC02) 12 { 13 case 1: 14 case 3: 15 fault = new IllegalInstruction; 16 case 0: 17 if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) 18 ;//branchHere 19 break; 20 case 2: 21 if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2)) 22 ;//branchHere 23 break; 24 } 25 }});//BPcc 26 0x2: Branch::bicc({{ 27 if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) 28 ;//branchHere 29 }});//Bicc 30 0x3: Branch::bpr({{ 31 switch(RCOND) 32 { 33 case 0: 34 case 4: 35 fault = new IllegalInstruction; 36 case 1: 37 if(Rs1 == 0) 38 ;//branchHere 39 break; 40 case 2: 41 if(Rs1 <= 0) 42 ;//branchHere 43 break; 44 case 3: 45 if(Rs1 < 0) 46 ;//branchHere 47 break; 48 case 5: 49 if(Rs1 != 0) 50 ;//branchHere 51 break; 52 case 6: 53 if(Rs1 > 0) 54 ;//branchHere 55 break; 56 case 7: 57 if(Rs1 >= 0) 58 ;//branchHere 59 break; 60 } 61 }}); //BPr 62 //SETHI (or NOP if rd == 0 and imm == 0) 63 0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); 64 0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc 65 0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc 66 } 67 0x1: Branch::call({{ 68 //branch here 69 Rd = xc->pc; 70 }}); 71 0x2: decode OP3 { 72 format IntegerOp { 73 0x00: add({{ 74 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 75 Rd = Rs1.sdw + val2; 76 }});//ADD 77 0x01: and({{ 78 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 79 Rd = Rs1.udw & val2; 80 }});//AND 81 0x02: or({{ 82 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 83 Rd = Rs1.udw | val2; 84 }});//OR 85 0x03: xor({{ 86 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 87 Rd = Rs1.udw ^ val2; 88 }});//XOR 89 0x04: sub({{ 90 int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1; 91 Rd = Rs1.sdw + val2; 92 }});//SUB 93 0x05: andn({{ 94 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 95 Rd = Rs1.udw & ~val2; 96 }});//ANDN 97 0x06: orn({{ 98 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 99 Rd = Rs1.udw | ~val2; 100 }});//ORN 101 0x07: xnor({{ 102 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 103 Rd = ~(Rs1.udw ^ val2); 104 }});//XNOR 105 0x08: addc({{ 106 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 107 int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 108 Rd = Rs1.sdw + val2 + carryin; 109 }});//ADDC 110 0x09: mulx({{ 111 int64_t val2 = (I ? SIMM13.sdw : Rs2); 112 Rd = Rs1 * val2; 113 }});//MULX 114 0x0A: umul({{ 115 uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw); 116 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 117 xc->regs.MiscRegs.yFields.value = resTemp<63:32>; 118 }});//UMUL 119 0x0B: smul({{ 120 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw); 121 rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>; 122 xc->regs.MiscRegs.yFields.value = resTemp<63:32>; 123 }});//SMUL 124 0x0C: subc({{ 125 int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1; 126 int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 127 Rd.sdw = Rs1.sdw + val2 + carryin; 128 }});//SUBC 129 0x0D: udivx({{ 130 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 131 if(val2 == 0) throw division_by_zero; 132 Rd.udw = Rs1.udw / val2; 133 }});//UDIVX 134 0x0E: udiv({{ 135 uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 136 if(val2 == 0) 137 fault = new DivisionByZero; 138 resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) 139 | Rs1.udw<31:0>) / val2; 140 int32_t overflow = (resTemp<63:32> != 0); 141 if(overflow) 142 rd.udw = resTemp = 0xFFFFFFFF; 143 else 144 rd.udw = resTemp; 145 }}); //UDIV 146 0x0F: sdiv({{ 147 int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 148 if(val2 == 0) 149 fault = new DivisionByZero; 150 151 Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | 152 Rs1.sdw<31:0>) / val2; 153 resTemp = Rd.sdw; 154 int32_t overflow = (resTemp<63:31> != 0); 155 int32_t underflow = 156 (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 157 if(overflow) 158 rd.udw = resTemp = 0x7FFFFFFF; 159 else if(underflow) 160 rd.udw = resTemp = 0xFFFFFFFF80000000; 161 else 162 rd.udw = resTemp; 163 }});//SDIV 164 } 165 format IntegerOpCc { 166 0x10: addcc({{ 167 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 168 Rd = resTemp = Rs1 + val2;}}, 169 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 170 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 171 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 172 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 173 );//ADDcc 174 0x11: andcc({{ 175 int64_t val2 = (I ? SIMM13.sdw : Rs2); 176 Rd = Rs1 & val2;}}, 177 {{0}},{{0}},{{0}},{{0}});//ANDcc 178 0x12: orcc({{ 179 int64_t val2 = (I ? SIMM13.sdw : Rs2); 180 Rd = Rs1 | val2;}}, 181 {{0}},{{0}},{{0}},{{0}});//ORcc 182 0x13: xorcc({{ 183 int64_t val2 = (I ? SIMM13.sdw : Rs2); 184 Rd = Rs1 ^ val2;}}, 185 {{0}},{{0}},{{0}},{{0}});//XORcc 186 0x14: subcc({{ 187 int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2); 188 Rd = resTemp = Rs1 - val2;}}, 189 {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, 190 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 191 {{((Rs1 >> 1) + (~val2) >> 1) + 192 ((Rs1 | ~val2) & 0x1))<63:>}}, 193 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 194 );//SUBcc 195 0x15: andncc({{ 196 int64_t val2 = (I ? SIMM13.sdw : Rs2); 197 Rd = Rs1 & ~val2;}}, 198 {{0}},{{0}},{{0}},{{0}});//ANDNcc 199 0x16: orncc({{ 200 int64_t val2 = (I ? SIMM13.sdw : Rs2); 201 Rd = Rs1 | ~val2;}}, 202 {{0}},{{0}},{{0}},{{0}});//ORNcc 203 0x17: xnorcc({{ 204 int64_t val2 = (I ? SIMM13.sdw : Rs2); 205 Rd = ~(Rs1 ^ val2);}}, 206 {{0}},{{0}},{{0}},{{0}});//XNORcc 207 0x18: addccc({{ 208 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 209 int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 210 Rd = resTemp = Rs1 + val2 + carryin;}}, 211 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 212 + carryin)}}, 213 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 214 {{((Rs1 >> 1) + (val2 >> 1) + 215 ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, 216 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 217 );//ADDCcc 218 0x1A: umulcc({{ 219 uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 220 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 221 xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}, 222 {{0}},{{0}},{{0}},{{0}});//UMULcc 223 0x1B: smulcc({{ 224 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 225 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 226 xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} 227 ,{{0}},{{0}},{{0}},{{0}});//SMULcc 228 0x1C: subccc({{ 229 int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2); 230 int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 231 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 232 {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, 233 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 234 {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, 235 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 236 );//SUBCcc 237 0x1D: udivxcc({{ 238 uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); 239 if(val2 == 0) throw division_by_zero; 240 Rd.udw = Rs1.udw / val2;}} 241 ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc 242 0x1E: udivcc({{ 243 uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 244 if(val2 == 0) throw division_by_zero; 245 resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; 246 int32_t overflow = (resTemp<63:32> != 0); 247 if(overflow) rd.udw = resTemp = 0xFFFFFFFF; 248 else rd.udw = resTemp;}}, 249 {{0}}, 250 {{overflow}}, 251 {{0}}, 252 {{0}} 253 );//UDIVcc 254 0x1F: sdivcc({{ 255 int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 256 if(val2 == 0) throw division_by_zero; 257 Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; 258 int32_t overflow = (resTemp<63:31> != 0); 259 int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 260 if(overflow) rd.udw = resTemp = 0x7FFFFFFF; 261 else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; 262 else rd.udw = resTemp;}}, 263 {{0}}, 264 {{overflow || underflow}}, 265 {{0}}, 266 {{0}} 267 );//SDIVcc 268 0x20: taddcc({{ 269 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 270 Rd = resTemp = Rs1 + val2; 271 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 272 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 273 {{overflow}}, 274 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 275 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 276 );//TADDcc 277 0x21: tsubcc({{ 278 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 279 Rd = resTemp = Rs1 + val2; 280 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 281 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 282 {{overflow}}, 283 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 284 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 285 );//TSUBcc 286 0x22: taddcctv({{ 287 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 288 Rd = resTemp = Rs1 + val2; 289 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 290 if(overflow) throw tag_overflow;}}, 291 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 292 {{overflow}}, 293 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 294 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 295 );//TADDccTV 296 0x23: tsubcctv({{ 297 int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); 298 Rd = resTemp = Rs1 + val2; 299 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 300 if(overflow) throw tag_overflow;}}, 301 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 302 {{overflow}}, 303 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 304 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 305 );//TSUBccTV 306 0x24: mulscc({{ 307 int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2); 308 int32_t multiplier = Rs1<31:0>; 309 int32_t savedLSB = Rs1<0:>; 310 multiplier = multipler<31:1> | 311 ((xc->regs.MiscRegs.ccrFields.iccFields.n 312 ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32); 313 if(!xc->regs.MiscRegs.yFields.value<0:>) 314 multiplicand = 0; 315 Rd = resTemp = multiplicand + multiplier; 316 xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}}, 317 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 318 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 319 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 320 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 321 );//MULScc 322 } 323 format IntegerOp 324 { 325 0x25: decode X { 326 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL 327 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX 328 } 329 0x26: decode X { 330 0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL 331 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX 332 } 333 0x27: decode X { 334 0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA 335 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 336 } 337 0x28: decode RS1 { 338 0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY 339 0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR 340 0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI 341 0x4: rdtick({{ 342 if(xc->regs.MiscRegs.pstateFields.priv == 0 && 343 xc->regs.MiscRegs.tickFields.npt == 1) 344 throw privileged_action; 345 Rd = xc->regs.MiscRegs.tick; 346 }});//RDTICK 347 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC 348 0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS 349 0xF: decode I { 350 0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR 351 0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR 352 } 353 } 354 355 0x2A: decode RS1 { 356 0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}}); 357 0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}}); 358 0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}}); 359 0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}}); 360 0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}}); 361 0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}}); 362 0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}}); 363 0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}}); 364 0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}}); 365 0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}}); 366 0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}}); 367 0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}}); 368 0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}}); 369 0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}}); 370 0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}}); 371 0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now. 372 } 373 0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW 374 0x2C: movcc({{ 375 ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0); 376 switch(ccBank) 377 { 378 case 0: case 1: case 2: case 3: 379 throw fp_disabled; 380 break; 381 case 5: case 7: 382 throw illegal_instruction; 383 break; 384 case 4: 385 if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4)) 386 Rd = (I ? SIMM11.sdw : RS2); 387 break; 388 case 6: 389 if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4)) 390 Rd = (I ? SIMM11.sdw : RS2); 391 break; 392 } 393 }});//MOVcc 394 0x2D: sdivx({{ 395 int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 396 if(val2 == 0) throw division_by_zero; 397 Rd.sdw = Rs1.sdw / val2; 398 }});//SDIVX 399 0x2E: decode RS1 { 400 0x0: IntegerOp::popc({{ 401 int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw); 402 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4} 403 for(unsigned int x = 0; x < 16; x++) 404 { 405 count += oneBits[val2 & 0xF]; 406 val2 >> 4; 407 } 408 }});//POPC 409 } 410 0x2F: movr({{ 411 uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw); 412 switch(RCOND) 413 { 414 case 0: case 4: 415 throw illegal_instruction; 416 break; 417 case 1: 418 if(Rs1 == 0) Rd = val2; 419 break; 420 case 2: 421 if(Rs1 <= 0) Rd = val2; 422 break; 423 case 3: 424 if(Rs1 = 0) Rd = val2; 425 break; 426 case 5: 427 if(Rs1 != 0) Rd = val2; 428 break; 429 case 6: 430 if(Rs1 > 0) Rd = val2; 431 break; 432 case 7: 433 if(Rs1 >= 0) Rd = val2; 434 break; 435 } 436 }});//MOVR 437 0x30: decode RD { 438 0x0: wry({{ 439 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 440 xc->regs.MiscRegs.y = Rs1 ^ val2; 441 }});//WRY 442 0x2: wrccr({{ 443 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 444 xc->regs.MiscRegs.ccr = Rs1 ^ val2; 445 }});//WRCCR 446 0x3: wrasi({{ 447 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 448 xc->regs.MiscRegs.asi = Rs1 ^ val2; 449 }});//WRASI 450 0x6: wrfprs({{ 451 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 452 xc->regs.MiscRegs.asi = Rs1 ^ val2; 453 }});//WRFPRS 454 0xF: Trap::sir({{software_initiated_reset}}); //SIR 455 } 456 0x31: decode FCN { 457 0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED 458 0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED 459 } 460 0x32: decode RD { 461 0x0: wrprtpc({{checkPriv 462 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 463 xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 464 }}); 465 0x1: wrprtnpc({{checkPriv 466 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 467 xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 468 }}); 469 0x2: wrprtstate({{checkPriv 470 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 471 xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 472 }}); 473 0x3: wrprtt({{checkPriv 474 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 475 xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 476 }}); 477 0x4: wrprtick({{checkPriv 478 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 479 xc->regs.MiscRegs.tick = Rs1 ^ val2; 480 }}); 481 0x5: wrprtba({{checkPriv 482 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 483 xc->regs.MiscRegs.tba = Rs1 ^ val2; 484 }}); 485 0x6: wrprpstate({{checkPriv 486 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 487 xc->regs.MiscRegs.pstate = Rs1 ^ val2; 488 }}); 489 0x7: wrprtl({{checkPriv 490 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 491 xc->regs.MiscRegs.tl = Rs1 ^ val2; 492 }}); 493 0x8: wrprpil({{checkPriv 494 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 495 xc->regs.MiscRegs.pil = Rs1 ^ val2; 496 }}); 497 0x9: wrprcwp({{checkPriv 498 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 499 xc->regs.MiscRegs.cwp = Rs1 ^ val2; 500 }}); 501 0xA: wrprcansave({{checkPriv 502 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 503 xc->regs.MiscRegs.cansave = Rs1 ^ val2; 504 }}); 505 0xB: wrprcanrestore({{checkPriv 506 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 507 xc->regs.MiscRegs.canrestore = Rs1 ^ val2; 508 }}); 509 0xC: wrprcleanwin({{checkPriv 510 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 511 xc->regs.MiscRegs.cleanwin = Rs1 ^ val2; 512 }}); 513 0xD: wrprotherwin({{checkPriv 514 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 515 xc->regs.MiscRegs.otherwin = Rs1 ^ val2; 516 }}); 517 0xE: wrprwstate({{checkPriv 518 uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); 519 xc->regs.MiscRegs.wstate = Rs1 ^ val2; 520 }}); 521 } 522 523 0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1 524 0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2 525 526 527 0x38: Branch::jmpl({{//Stuff}}); //JMPL 528 0x39: Branch::return({{//Other Stuff}}); //RETURN 529 0x3A: Trap::tcc({{ 530 switch((CC14 << 1) | (CC04 << 0)) 531 { 532 case 1: case 3: 533 throw illegal_instruction; 534 case 0: 535 if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) 536 throw trap_instruction; 537 break; 538 case 2: 539 if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) 540 throw trap_instruction; 541 break; 542 } 543 }}); //Tcc 544 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH 545 0x3C: BasicOperate::save({{//leprechauns); //SAVE 546 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE 547 0x3E: decode FCN { 548 0x1: BasicOperate::done({{//Done thing}}); //DONE 549 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY 550 } 551 } 552 } 553 0x3: decode OP3 { 554 format Mem { 555 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 556 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 557 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 558 0x03: ldd({{ 559 uint64_t val = Mem.udw; 560 setIntReg(RD & (~1), val<31:0>); 561 setIntReg(RD | 1, val<63:32>); 562 }});//LDD 563 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 564 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 565 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 566 0x07: std({{ 567 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 568 }});//STD 569 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 570 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB 571 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 572 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 573 574 0x0D: ldstub({{ 575 Rd.ub = Mem.ub; 576 Mem.ub = 0xFF; 577 }}); //LDSTUB 578 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX 579 0x0F: swap({{ 580 uint32_t temp = Rd.uw; 581 Rd.uw = Mem.uw; 582 Mem.uw = temp; 583 }}); //SWAP 584 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA 585 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA 586 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 587 0x13: ldda({{ 588 uint64_t val = Mem.udw; 589 setIntReg(RD & (~1), val<31:0>); 590 setIntReg(RD | 1, val<63:32>); 591 }}); //LDDA 592 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 593 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 594 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 595 0x17: stda({{ 596 Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 597 }}); //STDA 598 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 599 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 600 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 601 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA 602 603 0x1D: ldstuba({{ 604 Rd.ub = Mem.ub; 605 Mem.ub = 0xFF; 606 }}); //LDSTUBA 607 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA 608 0x1F: swapa({{ 609 uint32_t temp = Rd.uw; 610 Rd.uw = Mem.uw; 611 Mem.uw = temp; 612 }}); //SWAPA 613 0x20: Trap::ldf({{throw fp_disabled;}}); //LDF 614 0x21: decode X { 615 0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR 616 0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR 617 } 618 0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF 619 0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF 620 0x24: Trap::stf({{throw fp_disabled;}}); //STF 621 0x25: decode X { 622 0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR 623 0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR 624 } 625 0x26: Trap::stqf({{throw fp_disabled;}}); //STQF 626 0x27: Trap::stdf({{throw fp_disabled;}}); //STDF 627 628 629 630 631 632 0x2D: Noop::prefetch({{ }}); //PREFETCH 633 634 635 0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA 636 637 0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA 638 0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA 639 0x34: Trap::stfa({{throw fp_disabled;}}); //STFA 640 0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA 641 0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA 642 643 644 645 646 647 0x3C: Cas::casa( 648 {{uint64_t val = Mem.uw; 649 if(Rs2.uw == val) 650 Mem.uw = Rd.uw; 651 Rd.uw = val; 652 }}); //CASA 653 0x3D: Noop::prefetcha({{ }}); //PREFETCHA 654 0x3E: Cas::casxa( 655 {{uint64_t val = Mem.udw; 656 if(Rs2 == val) 657 Mem.udw = Rd; 658 Rd = val; 659 }}); //CASXA 660 } 661 } 662} 663