xref: /gem5/src/arch/sparc/isa/bitfields.isa

// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Ali Saidi
//          Gabe Black
//          Steve Reinhardt

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

// Bitfields are shared liberally between instruction formats, so they are
// simply defined alphabetically

def bitfield A		<29>;
def bitfield BPCC       <21:20>; // for BPcc & FBPcc
def bitfield FCMPCC     <26:25>; // for FCMP & FCMPEa
def bitfield FMOVCC     <13:11>; // for FMOVcc
def bitfield CC         <12:11>; // for MOVcc & Tcc
def bitfield MOVCC3     <18>; // also for MOVcc
def bitfield CMASK	<6:4>;
def bitfield COND2	<28:25>;
def bitfield COND4	<17:14>;
def bitfield D16HI	<21:20>;
def bitfield D16LO	<13:0>;
def bitfield DISP19	<18:0>;
def bitfield DISP22	<21:0>;
def bitfield DISP30	<29:0>;
def bitfield FCN	<29:25>;
def bitfield I		<13>;
def bitfield IMM_ASI	<12:5>;
def bitfield IMM22	<21:0>;
def bitfield M5FUNC     <15:7>;
def bitfield MMASK	<3:0>;
def bitfield OP		<31:30>;
def bitfield OP2	<24:22>;
def bitfield OP3	<24:19>;
def bitfield OPF	<13:5>;
def bitfield OPF_CC	<13:11>;
def bitfield OPF_LOW5	<9:5>;
def bitfield OPF_LOW6	<10:5>;
def bitfield P		<19>;
def bitfield RCOND2	<27:25>;
def bitfield RCOND3	<12:10>;
def bitfield RCOND4	<12:10>;
def bitfield RD		<29:25>;
def bitfield RS1	<18:14>;
def bitfield RS2	<4:0>;
def bitfield SHCNT32	<4:0>;
def bitfield SHCNT64	<5:0>;
def bitfield SIMM10	<9:0>;
def bitfield SIMM11	<10:0>;
def bitfield SIMM13	<12:0>;
def bitfield SW_TRAP	<7:0>;
def bitfield X		<12>;

// Extended bitfields which aren't part of the actual instruction.

def bitfield EXT_ASI	<39:32>;