base.isa revision 5202
13931Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312030SN/A//////////////////////////////////////////////////////////////////// 322030SN/A// 332030SN/A// Base class for sparc instructions, and some support functions 342030SN/A// 352030SN/A 362030SN/Aoutput header {{ 372224SN/A 382482SN/A union CondCodes 392224SN/A { 402482SN/A struct 412482SN/A { 422482SN/A uint8_t c:1; 432482SN/A uint8_t v:1; 442482SN/A uint8_t z:1; 452482SN/A uint8_t n:1; 462482SN/A }; 472482SN/A uint32_t bits; 482458SN/A }; 492224SN/A 502482SN/A enum CondTest 512224SN/A { 522224SN/A Always=0x8, 532224SN/A Never=0x0, 542224SN/A NotEqual=0x9, 552224SN/A Equal=0x1, 562224SN/A Greater=0xA, 572224SN/A LessOrEqual=0x2, 582224SN/A GreaterOrEqual=0xB, 592224SN/A Less=0x3, 602224SN/A GreaterUnsigned=0xC, 612224SN/A LessOrEqualUnsigned=0x4, 622224SN/A CarryClear=0xD, 632224SN/A CarrySet=0x5, 642224SN/A Positive=0xE, 652224SN/A Negative=0x6, 662224SN/A OverflowClear=0xF, 672224SN/A OverflowSet=0x7 682458SN/A }; 692224SN/A 704004Sgblack@eecs.umich.edu enum FpCondTest 714004Sgblack@eecs.umich.edu { 724004Sgblack@eecs.umich.edu FAlways=0x8, 734004Sgblack@eecs.umich.edu FNever=0x0, 744004Sgblack@eecs.umich.edu FUnordered=0x7, 754004Sgblack@eecs.umich.edu FGreater=0x6, 764004Sgblack@eecs.umich.edu FUnorderedOrGreater=0x5, 774004Sgblack@eecs.umich.edu FLess=0x4, 784004Sgblack@eecs.umich.edu FUnorderedOrLess=0x3, 794004Sgblack@eecs.umich.edu FLessOrGreater=0x2, 804004Sgblack@eecs.umich.edu FNotEqual=0x1, 814004Sgblack@eecs.umich.edu FEqual=0x9, 824004Sgblack@eecs.umich.edu FUnorderedOrEqual=0xA, 834004Sgblack@eecs.umich.edu FGreaterOrEqual=0xB, 844004Sgblack@eecs.umich.edu FUnorderedOrGreaterOrEqual=0xC, 854004Sgblack@eecs.umich.edu FLessOrEqual=0xD, 864004Sgblack@eecs.umich.edu FUnorderedOrLessOrEqual=0xE, 874004Sgblack@eecs.umich.edu FOrdered=0xF 884004Sgblack@eecs.umich.edu }; 894004Sgblack@eecs.umich.edu 905202Sstever@gmail.com extern const char *CondTestAbbrev[]; 912561SN/A 922030SN/A /** 932030SN/A * Base class for all SPARC static instructions. 942030SN/A */ 952224SN/A class SparcStaticInst : public StaticInst 962030SN/A { 972224SN/A protected: 982224SN/A // Constructor. 992224SN/A SparcStaticInst(const char *mnem, 1003278Sgblack@eecs.umich.edu ExtMachInst _machInst, OpClass __opClass) 1012224SN/A : StaticInst(mnem, _machInst, __opClass) 1022030SN/A { 1032030SN/A } 1042030SN/A 1052224SN/A std::string generateDisassembly(Addr pc, 1062224SN/A const SymbolTable *symtab) const; 1072469SN/A 1082951Sgblack@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 1092944Sgblack@eecs.umich.edu void printSrcReg(std::ostream &os, int reg) const; 1102944Sgblack@eecs.umich.edu void printDestReg(std::ostream &os, int reg) const; 1112944Sgblack@eecs.umich.edu 1122944Sgblack@eecs.umich.edu void printRegArray(std::ostream &os, 1132944Sgblack@eecs.umich.edu const RegIndex indexArray[], int num) const; 1142030SN/A }; 1152030SN/A 1164004Sgblack@eecs.umich.edu bool passesFpCondition(uint32_t fcc, uint32_t condition); 1174004Sgblack@eecs.umich.edu 1182482SN/A bool passesCondition(uint32_t codes, uint32_t condition); 1192516SN/A 1202516SN/A inline int64_t sign_ext(uint64_t data, int origWidth) 1212516SN/A { 1222526SN/A int shiftAmount = 64 - origWidth; 1232516SN/A return (((int64_t)data) << shiftAmount) >> shiftAmount; 1242516SN/A } 1252482SN/A}}; 1262482SN/A 1272561SN/Aoutput decoder {{ 1282561SN/A 1295202Sstever@gmail.com const char *CondTestAbbrev[] = 1302561SN/A { 1312561SN/A "nev", //Never 1322561SN/A "e", //Equal 1332561SN/A "le", //Less or Equal 1342561SN/A "l", //Less 1352561SN/A "leu", //Less or Equal Unsigned 1362561SN/A "c", //Carry set 1372561SN/A "n", //Negative 1382561SN/A "o", //Overflow set 1392561SN/A "a", //Always 1402561SN/A "ne", //Not Equal 1412561SN/A "g", //Greater 1422561SN/A "ge", //Greater or Equal 1432561SN/A "gu", //Greater Unsigned 1442561SN/A "cc", //Carry clear 1452561SN/A "p", //Positive 1462561SN/A "oc" //Overflow Clear 1472561SN/A }; 1482561SN/A}}; 1492561SN/A 1502482SN/Adef template ROrImmDecode {{ 1512482SN/A { 1522482SN/A return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst)) 1532482SN/A : (SparcStaticInst *)(new %(class_name)s(machInst))); 1542482SN/A } 1552482SN/A}}; 1562482SN/A 1574362Sgblack@eecs.umich.eduoutput header {{ 1584362Sgblack@eecs.umich.edu union DoubleSingle 1594362Sgblack@eecs.umich.edu { 1604362Sgblack@eecs.umich.edu double d; 1614362Sgblack@eecs.umich.edu uint64_t ui; 1624362Sgblack@eecs.umich.edu uint32_t s[2]; 1634362Sgblack@eecs.umich.edu DoubleSingle(double _d) : d(_d) 1644362Sgblack@eecs.umich.edu {} 1654362Sgblack@eecs.umich.edu DoubleSingle(uint64_t _ui) : ui(_ui) 1664362Sgblack@eecs.umich.edu {} 1674362Sgblack@eecs.umich.edu DoubleSingle(uint32_t _s0, uint32_t _s1) 1684362Sgblack@eecs.umich.edu { 1694362Sgblack@eecs.umich.edu s[0] = _s0; 1704362Sgblack@eecs.umich.edu s[1] = _s1; 1714362Sgblack@eecs.umich.edu } 1724362Sgblack@eecs.umich.edu }; 1734362Sgblack@eecs.umich.edu}}; 1744362Sgblack@eecs.umich.edu 1754362Sgblack@eecs.umich.edulet {{ 1764362Sgblack@eecs.umich.edu def filterDoubles(code): 1774362Sgblack@eecs.umich.edu assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE) 1784362Sgblack@eecs.umich.edu for opName in ("Frd", "Frs1", "Frs2", "Frd_N"): 1794362Sgblack@eecs.umich.edu next_pos = 0 1804362Sgblack@eecs.umich.edu operandsREString = (r''' 1814362Sgblack@eecs.umich.edu (?<![\w\.]) # neg. lookbehind assertion: prevent partial matches 1824362Sgblack@eecs.umich.edu ((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix 1834362Sgblack@eecs.umich.edu (?![\w\.]) # neg. lookahead assertion: prevent partial matches 1844362Sgblack@eecs.umich.edu ''' % opName) 1854362Sgblack@eecs.umich.edu operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE) 1864362Sgblack@eecs.umich.edu is_src = False 1874362Sgblack@eecs.umich.edu is_dest = False 1884362Sgblack@eecs.umich.edu extension = None 1894362Sgblack@eecs.umich.edu foundOne = False 1904362Sgblack@eecs.umich.edu while 1: 1914362Sgblack@eecs.umich.edu match = operandsRE.search(code, next_pos) 1924362Sgblack@eecs.umich.edu if not match: 1934362Sgblack@eecs.umich.edu break 1944362Sgblack@eecs.umich.edu foundOne = True 1954362Sgblack@eecs.umich.edu op = match.groups() 1964362Sgblack@eecs.umich.edu (op_full, op_base, op_ext) = op 1974362Sgblack@eecs.umich.edu is_dest_local = (assignRE.match(code, match.end()) != None) 1984362Sgblack@eecs.umich.edu is_dest = is_dest or is_dest_local 1994362Sgblack@eecs.umich.edu is_src = is_src or not is_dest_local 2004362Sgblack@eecs.umich.edu if extension and extension != op_ext: 2014362Sgblack@eecs.umich.edu raise Exception, "Inconsistent extensions in double filter." 2024362Sgblack@eecs.umich.edu extension = op_ext 2034362Sgblack@eecs.umich.edu next_pos = match.end() 2044362Sgblack@eecs.umich.edu if foundOne: 2054362Sgblack@eecs.umich.edu # Get rid of any unwanted extension 2064362Sgblack@eecs.umich.edu code = operandsRE.sub(op_base, code) 2074362Sgblack@eecs.umich.edu is_int = False 2084362Sgblack@eecs.umich.edu member = "d" 2094362Sgblack@eecs.umich.edu if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"): 2104362Sgblack@eecs.umich.edu is_int = True 2114362Sgblack@eecs.umich.edu member = "ui" 2124362Sgblack@eecs.umich.edu if is_src: 2134362Sgblack@eecs.umich.edu code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \ 2144362Sgblack@eecs.umich.edu (opName, opName, opName, member)) + code 2154362Sgblack@eecs.umich.edu if is_dest: 2164362Sgblack@eecs.umich.edu code += ''' 2174362Sgblack@eecs.umich.edu %s_low = DoubleSingle(%s).s[1]; 2184362Sgblack@eecs.umich.edu %s_high = DoubleSingle(%s).s[0];''' % \ 2194362Sgblack@eecs.umich.edu (opName, opName, opName, opName) 2204362Sgblack@eecs.umich.edu if is_int: 2214362Sgblack@eecs.umich.edu code = ("uint64_t %s;" % opName) + code 2224362Sgblack@eecs.umich.edu else: 2234362Sgblack@eecs.umich.edu code = ("double %s;" % opName) + code 2244362Sgblack@eecs.umich.edu return code 2254362Sgblack@eecs.umich.edu}}; 2264362Sgblack@eecs.umich.edu 2272482SN/Alet {{ 2282482SN/A def splitOutImm(code): 2292614SN/A matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?') 2302482SN/A rOrImmMatch = matcher.search(code) 2312482SN/A if (rOrImmMatch == None): 2322516SN/A return (False, code, '', '', '') 2332516SN/A rString = rOrImmMatch.group("rNum") 2342614SN/A if (rOrImmMatch.group("typeQual") != None): 2352614SN/A rString += rOrImmMatch.group("typeQual") 2362516SN/A iString = rOrImmMatch.group("iNum") 2372482SN/A orig_code = code 2382614SN/A code = matcher.sub('Rs' + rString, orig_code) 2392482SN/A imm_code = matcher.sub('imm', orig_code) 2402516SN/A return (True, code, imm_code, rString, iString) 2412030SN/A}}; 2422030SN/A 2432030SN/Aoutput decoder {{ 2442030SN/A 2452516SN/A inline void printMnemonic(std::ostream &os, const char * mnemonic) 2462516SN/A { 2472516SN/A ccprintf(os, "\t%s ", mnemonic); 2482516SN/A } 2492516SN/A 2502944Sgblack@eecs.umich.edu void SparcStaticInst::printRegArray(std::ostream &os, 2512944Sgblack@eecs.umich.edu const RegIndex indexArray[], int num) const 2522944Sgblack@eecs.umich.edu { 2532944Sgblack@eecs.umich.edu if(num <= 0) 2542944Sgblack@eecs.umich.edu return; 2552944Sgblack@eecs.umich.edu printReg(os, indexArray[0]); 2562944Sgblack@eecs.umich.edu for(int x = 1; x < num; x++) 2572944Sgblack@eecs.umich.edu { 2582944Sgblack@eecs.umich.edu os << ", "; 2592944Sgblack@eecs.umich.edu printReg(os, indexArray[x]); 2602944Sgblack@eecs.umich.edu } 2612944Sgblack@eecs.umich.edu } 2622944Sgblack@eecs.umich.edu 2632469SN/A void 2642944Sgblack@eecs.umich.edu SparcStaticInst::printSrcReg(std::ostream &os, int reg) const 2652944Sgblack@eecs.umich.edu { 2662944Sgblack@eecs.umich.edu if(_numSrcRegs > reg) 2672944Sgblack@eecs.umich.edu printReg(os, _srcRegIdx[reg]); 2682944Sgblack@eecs.umich.edu } 2692944Sgblack@eecs.umich.edu 2702944Sgblack@eecs.umich.edu void 2712944Sgblack@eecs.umich.edu SparcStaticInst::printDestReg(std::ostream &os, int reg) const 2722944Sgblack@eecs.umich.edu { 2732944Sgblack@eecs.umich.edu if(_numDestRegs > reg) 2742944Sgblack@eecs.umich.edu printReg(os, _destRegIdx[reg]); 2752944Sgblack@eecs.umich.edu } 2762944Sgblack@eecs.umich.edu 2772944Sgblack@eecs.umich.edu void 2782951Sgblack@eecs.umich.edu SparcStaticInst::printReg(std::ostream &os, int reg) const 2792469SN/A { 2802516SN/A const int MaxGlobal = 8; 2812516SN/A const int MaxOutput = 16; 2822516SN/A const int MaxLocal = 24; 2832516SN/A const int MaxInput = 32; 2843978Sgblack@eecs.umich.edu const int MaxMicroReg = 40; 2853978Sgblack@eecs.umich.edu if (reg < FP_Base_DepTag) { 2863978Sgblack@eecs.umich.edu //If we used a register from the next or previous window, 2873978Sgblack@eecs.umich.edu //take out the offset. 2883978Sgblack@eecs.umich.edu while (reg >= MaxMicroReg) 2893978Sgblack@eecs.umich.edu reg -= MaxMicroReg; 2903978Sgblack@eecs.umich.edu if (reg == FramePointerReg) 2913978Sgblack@eecs.umich.edu ccprintf(os, "%%fp"); 2923978Sgblack@eecs.umich.edu else if (reg == StackPointerReg) 2933978Sgblack@eecs.umich.edu ccprintf(os, "%%sp"); 2943978Sgblack@eecs.umich.edu else if(reg < MaxGlobal) 2953978Sgblack@eecs.umich.edu ccprintf(os, "%%g%d", reg); 2963978Sgblack@eecs.umich.edu else if(reg < MaxOutput) 2973978Sgblack@eecs.umich.edu ccprintf(os, "%%o%d", reg - MaxGlobal); 2983978Sgblack@eecs.umich.edu else if(reg < MaxLocal) 2993978Sgblack@eecs.umich.edu ccprintf(os, "%%l%d", reg - MaxOutput); 3003978Sgblack@eecs.umich.edu else if(reg < MaxInput) 3013978Sgblack@eecs.umich.edu ccprintf(os, "%%i%d", reg - MaxLocal); 3023978Sgblack@eecs.umich.edu else if(reg < MaxMicroReg) 3033978Sgblack@eecs.umich.edu ccprintf(os, "%%u%d", reg - MaxInput); 3043978Sgblack@eecs.umich.edu //The fake int regs that are really control regs 3053978Sgblack@eecs.umich.edu else { 3063978Sgblack@eecs.umich.edu switch (reg - MaxMicroReg) { 3073978Sgblack@eecs.umich.edu case 1: 3083978Sgblack@eecs.umich.edu ccprintf(os, "%%y"); 3093978Sgblack@eecs.umich.edu break; 3103978Sgblack@eecs.umich.edu case 2: 3113978Sgblack@eecs.umich.edu ccprintf(os, "%%ccr"); 3123978Sgblack@eecs.umich.edu break; 3133978Sgblack@eecs.umich.edu case 3: 3143978Sgblack@eecs.umich.edu ccprintf(os, "%%cansave"); 3153978Sgblack@eecs.umich.edu break; 3163978Sgblack@eecs.umich.edu case 4: 3173978Sgblack@eecs.umich.edu ccprintf(os, "%%canrestore"); 3183978Sgblack@eecs.umich.edu break; 3193978Sgblack@eecs.umich.edu case 5: 3203978Sgblack@eecs.umich.edu ccprintf(os, "%%cleanwin"); 3213978Sgblack@eecs.umich.edu break; 3223978Sgblack@eecs.umich.edu case 6: 3233978Sgblack@eecs.umich.edu ccprintf(os, "%%otherwin"); 3243978Sgblack@eecs.umich.edu break; 3253978Sgblack@eecs.umich.edu case 7: 3263978Sgblack@eecs.umich.edu ccprintf(os, "%%wstate"); 3273978Sgblack@eecs.umich.edu break; 3283978Sgblack@eecs.umich.edu } 3293978Sgblack@eecs.umich.edu } 3303978Sgblack@eecs.umich.edu } else if (reg < Ctrl_Base_DepTag) { 3313978Sgblack@eecs.umich.edu ccprintf(os, "%%f%d", reg - FP_Base_DepTag); 3323978Sgblack@eecs.umich.edu } else { 3333978Sgblack@eecs.umich.edu switch (reg - Ctrl_Base_DepTag) { 3343978Sgblack@eecs.umich.edu case MISCREG_ASI: 3353978Sgblack@eecs.umich.edu ccprintf(os, "%%asi"); 3363978Sgblack@eecs.umich.edu break; 3373978Sgblack@eecs.umich.edu case MISCREG_FPRS: 3383978Sgblack@eecs.umich.edu ccprintf(os, "%%fprs"); 3393978Sgblack@eecs.umich.edu break; 3403978Sgblack@eecs.umich.edu case MISCREG_PCR: 3413978Sgblack@eecs.umich.edu ccprintf(os, "%%pcr"); 3423978Sgblack@eecs.umich.edu break; 3433978Sgblack@eecs.umich.edu case MISCREG_PIC: 3443978Sgblack@eecs.umich.edu ccprintf(os, "%%pic"); 3453978Sgblack@eecs.umich.edu break; 3463978Sgblack@eecs.umich.edu case MISCREG_GSR: 3473978Sgblack@eecs.umich.edu ccprintf(os, "%%gsr"); 3483978Sgblack@eecs.umich.edu break; 3493978Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 3503978Sgblack@eecs.umich.edu ccprintf(os, "%%softint"); 3513978Sgblack@eecs.umich.edu break; 3523978Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 3533978Sgblack@eecs.umich.edu ccprintf(os, "%%softint_set"); 3543978Sgblack@eecs.umich.edu break; 3553978Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 3563978Sgblack@eecs.umich.edu ccprintf(os, "%%softint_clr"); 3573978Sgblack@eecs.umich.edu break; 3583978Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 3593978Sgblack@eecs.umich.edu ccprintf(os, "%%tick_cmpr"); 3603978Sgblack@eecs.umich.edu break; 3613978Sgblack@eecs.umich.edu case MISCREG_STICK: 3623978Sgblack@eecs.umich.edu ccprintf(os, "%%stick"); 3633978Sgblack@eecs.umich.edu break; 3643978Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 3653978Sgblack@eecs.umich.edu ccprintf(os, "%%stick_cmpr"); 3663978Sgblack@eecs.umich.edu break; 3673978Sgblack@eecs.umich.edu case MISCREG_TPC: 3683978Sgblack@eecs.umich.edu ccprintf(os, "%%tpc"); 3693978Sgblack@eecs.umich.edu break; 3703978Sgblack@eecs.umich.edu case MISCREG_TNPC: 3713978Sgblack@eecs.umich.edu ccprintf(os, "%%tnpc"); 3723978Sgblack@eecs.umich.edu break; 3733978Sgblack@eecs.umich.edu case MISCREG_TSTATE: 3743978Sgblack@eecs.umich.edu ccprintf(os, "%%tstate"); 3753978Sgblack@eecs.umich.edu break; 3763978Sgblack@eecs.umich.edu case MISCREG_TT: 3773978Sgblack@eecs.umich.edu ccprintf(os, "%%tt"); 3783978Sgblack@eecs.umich.edu break; 3793978Sgblack@eecs.umich.edu case MISCREG_TICK: 3803978Sgblack@eecs.umich.edu ccprintf(os, "%%tick"); 3813978Sgblack@eecs.umich.edu break; 3823978Sgblack@eecs.umich.edu case MISCREG_TBA: 3833978Sgblack@eecs.umich.edu ccprintf(os, "%%tba"); 3843978Sgblack@eecs.umich.edu break; 3853978Sgblack@eecs.umich.edu case MISCREG_PSTATE: 3863978Sgblack@eecs.umich.edu ccprintf(os, "%%pstate"); 3873978Sgblack@eecs.umich.edu break; 3883978Sgblack@eecs.umich.edu case MISCREG_TL: 3893978Sgblack@eecs.umich.edu ccprintf(os, "%%tl"); 3903978Sgblack@eecs.umich.edu break; 3913978Sgblack@eecs.umich.edu case MISCREG_PIL: 3923978Sgblack@eecs.umich.edu ccprintf(os, "%%pil"); 3933978Sgblack@eecs.umich.edu break; 3943978Sgblack@eecs.umich.edu case MISCREG_CWP: 3953978Sgblack@eecs.umich.edu ccprintf(os, "%%cwp"); 3963978Sgblack@eecs.umich.edu break; 3973978Sgblack@eecs.umich.edu case MISCREG_GL: 3983978Sgblack@eecs.umich.edu ccprintf(os, "%%gl"); 3993978Sgblack@eecs.umich.edu break; 4003978Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 4013978Sgblack@eecs.umich.edu ccprintf(os, "%%hpstate"); 4023978Sgblack@eecs.umich.edu break; 4033978Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 4043978Sgblack@eecs.umich.edu ccprintf(os, "%%htstate"); 4053978Sgblack@eecs.umich.edu break; 4063978Sgblack@eecs.umich.edu case MISCREG_HINTP: 4073978Sgblack@eecs.umich.edu ccprintf(os, "%%hintp"); 4083978Sgblack@eecs.umich.edu break; 4093978Sgblack@eecs.umich.edu case MISCREG_HTBA: 4103978Sgblack@eecs.umich.edu ccprintf(os, "%%htba"); 4113978Sgblack@eecs.umich.edu break; 4123978Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 4133978Sgblack@eecs.umich.edu ccprintf(os, "%%hstick_cmpr"); 4143978Sgblack@eecs.umich.edu break; 4153978Sgblack@eecs.umich.edu case MISCREG_HVER: 4163978Sgblack@eecs.umich.edu ccprintf(os, "%%hver"); 4173978Sgblack@eecs.umich.edu break; 4183978Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 4193978Sgblack@eecs.umich.edu ccprintf(os, "%%strand_sts_reg"); 4203978Sgblack@eecs.umich.edu break; 4213978Sgblack@eecs.umich.edu case MISCREG_FSR: 4223978Sgblack@eecs.umich.edu ccprintf(os, "%%fsr"); 4233978Sgblack@eecs.umich.edu break; 4243978Sgblack@eecs.umich.edu default: 4253978Sgblack@eecs.umich.edu ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag); 4263978Sgblack@eecs.umich.edu } 4272469SN/A } 4282469SN/A } 4292469SN/A 4302224SN/A std::string SparcStaticInst::generateDisassembly(Addr pc, 4312224SN/A const SymbolTable *symtab) const 4322030SN/A { 4332224SN/A std::stringstream ss; 4342030SN/A 4352516SN/A printMnemonic(ss, mnemonic); 4362030SN/A 4372224SN/A // just print the first two source regs... if there's 4382224SN/A // a third one, it's a read-modify-write dest (Rc), 4392224SN/A // e.g. for CMOVxx 4402224SN/A if(_numSrcRegs > 0) 4412224SN/A { 4422224SN/A printReg(ss, _srcRegIdx[0]); 4432224SN/A } 4442224SN/A if(_numSrcRegs > 1) 4452224SN/A { 4462224SN/A ss << ","; 4472224SN/A printReg(ss, _srcRegIdx[1]); 4482224SN/A } 4492224SN/A 4502224SN/A // just print the first dest... if there's a second one, 4512224SN/A // it's generally implicit 4522224SN/A if(_numDestRegs > 0) 4532224SN/A { 4542030SN/A if(_numSrcRegs > 0) 4552224SN/A ss << ","; 4562224SN/A printReg(ss, _destRegIdx[0]); 4572224SN/A } 4582030SN/A 4592224SN/A return ss.str(); 4602030SN/A } 4612030SN/A 4624004Sgblack@eecs.umich.edu bool passesFpCondition(uint32_t fcc, uint32_t condition) 4634004Sgblack@eecs.umich.edu { 4644004Sgblack@eecs.umich.edu bool u = (fcc == 3); 4654004Sgblack@eecs.umich.edu bool g = (fcc == 2); 4664004Sgblack@eecs.umich.edu bool l = (fcc == 1); 4674004Sgblack@eecs.umich.edu bool e = (fcc == 0); 4684004Sgblack@eecs.umich.edu switch(condition) 4694004Sgblack@eecs.umich.edu { 4704004Sgblack@eecs.umich.edu case FAlways: 4714004Sgblack@eecs.umich.edu return 1; 4724004Sgblack@eecs.umich.edu case FNever: 4734004Sgblack@eecs.umich.edu return 0; 4744004Sgblack@eecs.umich.edu case FUnordered: 4754004Sgblack@eecs.umich.edu return u; 4764004Sgblack@eecs.umich.edu case FGreater: 4774004Sgblack@eecs.umich.edu return g; 4784004Sgblack@eecs.umich.edu case FUnorderedOrGreater: 4794004Sgblack@eecs.umich.edu return u || g; 4804004Sgblack@eecs.umich.edu case FLess: 4814004Sgblack@eecs.umich.edu return l; 4824004Sgblack@eecs.umich.edu case FUnorderedOrLess: 4834004Sgblack@eecs.umich.edu return u || l; 4844004Sgblack@eecs.umich.edu case FLessOrGreater: 4854004Sgblack@eecs.umich.edu return l || g; 4864004Sgblack@eecs.umich.edu case FNotEqual: 4874004Sgblack@eecs.umich.edu return l || g || u; 4884004Sgblack@eecs.umich.edu case FEqual: 4894004Sgblack@eecs.umich.edu return e; 4904004Sgblack@eecs.umich.edu case FUnorderedOrEqual: 4914004Sgblack@eecs.umich.edu return u || e; 4924004Sgblack@eecs.umich.edu case FGreaterOrEqual: 4934004Sgblack@eecs.umich.edu return g || e; 4944004Sgblack@eecs.umich.edu case FUnorderedOrGreaterOrEqual: 4954004Sgblack@eecs.umich.edu return u || g || e; 4964004Sgblack@eecs.umich.edu case FLessOrEqual: 4974004Sgblack@eecs.umich.edu return l || e; 4984004Sgblack@eecs.umich.edu case FUnorderedOrLessOrEqual: 4994004Sgblack@eecs.umich.edu return u || l || e; 5004004Sgblack@eecs.umich.edu case FOrdered: 5014004Sgblack@eecs.umich.edu return e || l || g; 5024004Sgblack@eecs.umich.edu } 5034004Sgblack@eecs.umich.edu panic("Tried testing condition nonexistant " 5044004Sgblack@eecs.umich.edu "condition code %d", condition); 5054004Sgblack@eecs.umich.edu } 5064004Sgblack@eecs.umich.edu 5072482SN/A bool passesCondition(uint32_t codes, uint32_t condition) 5082030SN/A { 5092482SN/A CondCodes condCodes; 5103603Ssaidi@eecs.umich.edu condCodes.bits = 0; 5113603Ssaidi@eecs.umich.edu condCodes.c = codes & 0x1 ? 1 : 0; 5123603Ssaidi@eecs.umich.edu condCodes.v = codes & 0x2 ? 1 : 0; 5133603Ssaidi@eecs.umich.edu condCodes.z = codes & 0x4 ? 1 : 0; 5143603Ssaidi@eecs.umich.edu condCodes.n = codes & 0x8 ? 1 : 0; 5153603Ssaidi@eecs.umich.edu 5162224SN/A switch(condition) 5172224SN/A { 5182224SN/A case Always: 5192224SN/A return true; 5202224SN/A case Never: 5212224SN/A return false; 5222224SN/A case NotEqual: 5232482SN/A return !condCodes.z; 5242224SN/A case Equal: 5252482SN/A return condCodes.z; 5262224SN/A case Greater: 5272482SN/A return !(condCodes.z | (condCodes.n ^ condCodes.v)); 5282224SN/A case LessOrEqual: 5292482SN/A return condCodes.z | (condCodes.n ^ condCodes.v); 5302224SN/A case GreaterOrEqual: 5312482SN/A return !(condCodes.n ^ condCodes.v); 5322224SN/A case Less: 5332482SN/A return (condCodes.n ^ condCodes.v); 5342224SN/A case GreaterUnsigned: 5352482SN/A return !(condCodes.c | condCodes.z); 5362224SN/A case LessOrEqualUnsigned: 5372482SN/A return (condCodes.c | condCodes.z); 5382224SN/A case CarryClear: 5392482SN/A return !condCodes.c; 5402224SN/A case CarrySet: 5412482SN/A return condCodes.c; 5422224SN/A case Positive: 5432482SN/A return !condCodes.n; 5442224SN/A case Negative: 5452482SN/A return condCodes.n; 5462224SN/A case OverflowClear: 5472482SN/A return !condCodes.v; 5482224SN/A case OverflowSet: 5492482SN/A return condCodes.v; 5502224SN/A } 5512469SN/A panic("Tried testing condition nonexistant " 5522469SN/A "condition code %d", condition); 5532030SN/A } 5542030SN/A}}; 5552030SN/A 5563931Ssaidi@eecs.umich.eduoutput exec {{ 5573931Ssaidi@eecs.umich.edu /// Check "FP enabled" machine status bit. Called when executing any FP 5583931Ssaidi@eecs.umich.edu /// instruction in full-system mode. 5593931Ssaidi@eecs.umich.edu /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled 5603931Ssaidi@eecs.umich.edu /// if not. Non-full-system mode: always returns NoFault. 5613931Ssaidi@eecs.umich.edu#if FULL_SYSTEM 5623931Ssaidi@eecs.umich.edu inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 5633931Ssaidi@eecs.umich.edu { 5643931Ssaidi@eecs.umich.edu Fault fault = NoFault; // dummy... this ipr access should not fault 5654172Ssaidi@eecs.umich.edu if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && 5664172Ssaidi@eecs.umich.edu xc->readMiscReg(MISCREG_FPRS) & 0x4) 5673931Ssaidi@eecs.umich.edu return NoFault; 5683931Ssaidi@eecs.umich.edu else 5693931Ssaidi@eecs.umich.edu return new FpDisabled; 5703931Ssaidi@eecs.umich.edu } 5713931Ssaidi@eecs.umich.edu#else 5723931Ssaidi@eecs.umich.edu inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) 5733931Ssaidi@eecs.umich.edu { 5743931Ssaidi@eecs.umich.edu return NoFault; 5753931Ssaidi@eecs.umich.edu } 5763931Ssaidi@eecs.umich.edu#endif 5773931Ssaidi@eecs.umich.edu}}; 5783931Ssaidi@eecs.umich.edu 5793931Ssaidi@eecs.umich.edu 580